spi-fsl-qspi.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale QuadSPI driver.
  4. *
  5. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  6. * Copyright (C) 2018 Bootlin
  7. * Copyright (C) 2018 exceet electronics GmbH
  8. * Copyright (C) 2018 Kontron Electronics GmbH
  9. *
  10. * Transition to SPI MEM interface:
  11. * Authors:
  12. * Boris Brezillon <bbrezillon@kernel.org>
  13. * Frieder Schrempf <frieder.schrempf@kontron.de>
  14. * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  15. * Suresh Gupta <suresh.gupta@nxp.com>
  16. *
  17. * Based on the original fsl-quadspi.c SPI NOR driver:
  18. * Author: Freescale Semiconductor, Inc.
  19. *
  20. */
  21. #include <linux/bitops.h>
  22. #include <linux/clk.h>
  23. #include <linux/completion.h>
  24. #include <linux/delay.h>
  25. #include <linux/err.h>
  26. #include <linux/errno.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/io.h>
  29. #include <linux/iopoll.h>
  30. #include <linux/jiffies.h>
  31. #include <linux/kernel.h>
  32. #include <linux/module.h>
  33. #include <linux/mutex.h>
  34. #include <linux/of.h>
  35. #include <linux/of_device.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/pm_qos.h>
  38. #include <linux/sizes.h>
  39. #include <linux/spi/spi.h>
  40. #include <linux/spi/spi-mem.h>
  41. /*
  42. * The driver only uses one single LUT entry, that is updated on
  43. * each call of exec_op(). Index 0 is preset at boot with a basic
  44. * read operation, so let's use the last entry (15).
  45. */
  46. #define SEQID_LUT 15
  47. /* Registers used by the driver */
  48. #define QUADSPI_MCR 0x00
  49. #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
  50. #define QUADSPI_MCR_MDIS_MASK BIT(14)
  51. #define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
  52. #define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
  53. #define QUADSPI_MCR_DDR_EN_MASK BIT(7)
  54. #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
  55. #define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
  56. #define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
  57. #define QUADSPI_IPCR 0x08
  58. #define QUADSPI_IPCR_SEQID(x) ((x) << 24)
  59. #define QUADSPI_FLSHCR 0x0c
  60. #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
  61. #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
  62. #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
  63. #define QUADSPI_BUF0CR 0x10
  64. #define QUADSPI_BUF1CR 0x14
  65. #define QUADSPI_BUF2CR 0x18
  66. #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
  67. #define QUADSPI_BUF3CR 0x1c
  68. #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
  69. #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
  70. #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
  71. #define QUADSPI_BFGENCR 0x20
  72. #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
  73. #define QUADSPI_BUF0IND 0x30
  74. #define QUADSPI_BUF1IND 0x34
  75. #define QUADSPI_BUF2IND 0x38
  76. #define QUADSPI_SFAR 0x100
  77. #define QUADSPI_SMPR 0x108
  78. #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
  79. #define QUADSPI_SMPR_FSDLY_MASK BIT(6)
  80. #define QUADSPI_SMPR_FSPHS_MASK BIT(5)
  81. #define QUADSPI_SMPR_HSENA_MASK BIT(0)
  82. #define QUADSPI_RBCT 0x110
  83. #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
  84. #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
  85. #define QUADSPI_TBDR 0x154
  86. #define QUADSPI_SR 0x15c
  87. #define QUADSPI_SR_IP_ACC_MASK BIT(1)
  88. #define QUADSPI_SR_AHB_ACC_MASK BIT(2)
  89. #define QUADSPI_FR 0x160
  90. #define QUADSPI_FR_TFF_MASK BIT(0)
  91. #define QUADSPI_RSER 0x164
  92. #define QUADSPI_RSER_TFIE BIT(0)
  93. #define QUADSPI_SPTRCLR 0x16c
  94. #define QUADSPI_SPTRCLR_IPPTRC BIT(8)
  95. #define QUADSPI_SPTRCLR_BFPTRC BIT(0)
  96. #define QUADSPI_SFA1AD 0x180
  97. #define QUADSPI_SFA2AD 0x184
  98. #define QUADSPI_SFB1AD 0x188
  99. #define QUADSPI_SFB2AD 0x18c
  100. #define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
  101. #define QUADSPI_LUTKEY 0x300
  102. #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
  103. #define QUADSPI_LCKCR 0x304
  104. #define QUADSPI_LCKER_LOCK BIT(0)
  105. #define QUADSPI_LCKER_UNLOCK BIT(1)
  106. #define QUADSPI_LUT_BASE 0x310
  107. #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  108. #define QUADSPI_LUT_REG(idx) \
  109. (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
  110. /* Instruction set for the LUT register */
  111. #define LUT_STOP 0
  112. #define LUT_CMD 1
  113. #define LUT_ADDR 2
  114. #define LUT_DUMMY 3
  115. #define LUT_MODE 4
  116. #define LUT_MODE2 5
  117. #define LUT_MODE4 6
  118. #define LUT_FSL_READ 7
  119. #define LUT_FSL_WRITE 8
  120. #define LUT_JMP_ON_CS 9
  121. #define LUT_ADDR_DDR 10
  122. #define LUT_MODE_DDR 11
  123. #define LUT_MODE2_DDR 12
  124. #define LUT_MODE4_DDR 13
  125. #define LUT_FSL_READ_DDR 14
  126. #define LUT_FSL_WRITE_DDR 15
  127. #define LUT_DATA_LEARN 16
  128. /*
  129. * The PAD definitions for LUT register.
  130. *
  131. * The pad stands for the number of IO lines [0:3].
  132. * For example, the quad read needs four IO lines,
  133. * so you should use LUT_PAD(4).
  134. */
  135. #define LUT_PAD(x) (fls(x) - 1)
  136. /*
  137. * Macro for constructing the LUT entries with the following
  138. * register layout:
  139. *
  140. * ---------------------------------------------------
  141. * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  142. * ---------------------------------------------------
  143. */
  144. #define LUT_DEF(idx, ins, pad, opr) \
  145. ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
  146. /* Controller needs driver to swap endianness */
  147. #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
  148. /* Controller needs 4x internal clock */
  149. #define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
  150. /*
  151. * TKT253890, the controller needs the driver to fill the txfifo with
  152. * 16 bytes at least to trigger a data transfer, even though the extra
  153. * data won't be transferred.
  154. */
  155. #define QUADSPI_QUIRK_TKT253890 BIT(2)
  156. /* TKT245618, the controller cannot wake up from wait mode */
  157. #define QUADSPI_QUIRK_TKT245618 BIT(3)
  158. /*
  159. * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
  160. * internally. No need to add it when setting SFXXAD and SFAR registers
  161. */
  162. #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
  163. /*
  164. * Controller uses TDH bits in register QUADSPI_FLSHCR.
  165. * They need to be set in accordance with the DDR/SDR mode.
  166. */
  167. #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
  168. struct fsl_qspi_devtype_data {
  169. unsigned int rxfifo;
  170. unsigned int txfifo;
  171. int invalid_mstrid;
  172. unsigned int ahb_buf_size;
  173. unsigned int quirks;
  174. bool little_endian;
  175. };
  176. static const struct fsl_qspi_devtype_data vybrid_data = {
  177. .rxfifo = SZ_128,
  178. .txfifo = SZ_64,
  179. .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
  180. .ahb_buf_size = SZ_1K,
  181. .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
  182. .little_endian = true,
  183. };
  184. static const struct fsl_qspi_devtype_data imx6sx_data = {
  185. .rxfifo = SZ_128,
  186. .txfifo = SZ_512,
  187. .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
  188. .ahb_buf_size = SZ_1K,
  189. .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
  190. .little_endian = true,
  191. };
  192. static const struct fsl_qspi_devtype_data imx7d_data = {
  193. .rxfifo = SZ_128,
  194. .txfifo = SZ_512,
  195. .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
  196. .ahb_buf_size = SZ_1K,
  197. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  198. QUADSPI_QUIRK_USE_TDH_SETTING,
  199. .little_endian = true,
  200. };
  201. static const struct fsl_qspi_devtype_data imx6ul_data = {
  202. .rxfifo = SZ_128,
  203. .txfifo = SZ_512,
  204. .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
  205. .ahb_buf_size = SZ_1K,
  206. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  207. QUADSPI_QUIRK_USE_TDH_SETTING,
  208. .little_endian = true,
  209. };
  210. static const struct fsl_qspi_devtype_data ls1021a_data = {
  211. .rxfifo = SZ_128,
  212. .txfifo = SZ_64,
  213. .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
  214. .ahb_buf_size = SZ_1K,
  215. .quirks = 0,
  216. .little_endian = false,
  217. };
  218. static const struct fsl_qspi_devtype_data ls2080a_data = {
  219. .rxfifo = SZ_128,
  220. .txfifo = SZ_64,
  221. .ahb_buf_size = SZ_1K,
  222. .invalid_mstrid = 0x0,
  223. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
  224. .little_endian = true,
  225. };
  226. struct fsl_qspi {
  227. void __iomem *iobase;
  228. void __iomem *ahb_addr;
  229. u32 memmap_phy;
  230. struct clk *clk, *clk_en;
  231. struct device *dev;
  232. struct completion c;
  233. const struct fsl_qspi_devtype_data *devtype_data;
  234. struct mutex lock;
  235. struct pm_qos_request pm_qos_req;
  236. int selected;
  237. };
  238. static inline int needs_swap_endian(struct fsl_qspi *q)
  239. {
  240. return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
  241. }
  242. static inline int needs_4x_clock(struct fsl_qspi *q)
  243. {
  244. return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
  245. }
  246. static inline int needs_fill_txfifo(struct fsl_qspi *q)
  247. {
  248. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
  249. }
  250. static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
  251. {
  252. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
  253. }
  254. static inline int needs_amba_base_offset(struct fsl_qspi *q)
  255. {
  256. return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
  257. }
  258. static inline int needs_tdh_setting(struct fsl_qspi *q)
  259. {
  260. return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
  261. }
  262. /*
  263. * An IC bug makes it necessary to rearrange the 32-bit data.
  264. * Later chips, such as IMX6SLX, have fixed this bug.
  265. */
  266. static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
  267. {
  268. return needs_swap_endian(q) ? __swab32(a) : a;
  269. }
  270. /*
  271. * R/W functions for big- or little-endian registers:
  272. * The QSPI controller's endianness is independent of
  273. * the CPU core's endianness. So far, although the CPU
  274. * core is little-endian the QSPI controller can use
  275. * big-endian or little-endian.
  276. */
  277. static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
  278. {
  279. if (q->devtype_data->little_endian)
  280. iowrite32(val, addr);
  281. else
  282. iowrite32be(val, addr);
  283. }
  284. static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
  285. {
  286. if (q->devtype_data->little_endian)
  287. return ioread32(addr);
  288. return ioread32be(addr);
  289. }
  290. static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
  291. {
  292. struct fsl_qspi *q = dev_id;
  293. u32 reg;
  294. /* clear interrupt */
  295. reg = qspi_readl(q, q->iobase + QUADSPI_FR);
  296. qspi_writel(q, reg, q->iobase + QUADSPI_FR);
  297. if (reg & QUADSPI_FR_TFF_MASK)
  298. complete(&q->c);
  299. dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
  300. return IRQ_HANDLED;
  301. }
  302. static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
  303. {
  304. switch (width) {
  305. case 1:
  306. case 2:
  307. case 4:
  308. return 0;
  309. }
  310. return -ENOTSUPP;
  311. }
  312. static bool fsl_qspi_supports_op(struct spi_mem *mem,
  313. const struct spi_mem_op *op)
  314. {
  315. struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
  316. int ret;
  317. ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
  318. if (op->addr.nbytes)
  319. ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
  320. if (op->dummy.nbytes)
  321. ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
  322. if (op->data.nbytes)
  323. ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
  324. if (ret)
  325. return false;
  326. /*
  327. * The number of instructions needed for the op, needs
  328. * to fit into a single LUT entry.
  329. */
  330. if (op->addr.nbytes +
  331. (op->dummy.nbytes ? 1:0) +
  332. (op->data.nbytes ? 1:0) > 6)
  333. return false;
  334. /* Max 64 dummy clock cycles supported */
  335. if (op->dummy.nbytes &&
  336. (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  337. return false;
  338. /* Max data length, check controller limits and alignment */
  339. if (op->data.dir == SPI_MEM_DATA_IN &&
  340. (op->data.nbytes > q->devtype_data->ahb_buf_size ||
  341. (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
  342. !IS_ALIGNED(op->data.nbytes, 8))))
  343. return false;
  344. if (op->data.dir == SPI_MEM_DATA_OUT &&
  345. op->data.nbytes > q->devtype_data->txfifo)
  346. return false;
  347. return spi_mem_default_supports_op(mem, op);
  348. }
  349. static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
  350. const struct spi_mem_op *op)
  351. {
  352. void __iomem *base = q->iobase;
  353. u32 lutval[4] = {};
  354. int lutidx = 1, i;
  355. lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  356. op->cmd.opcode);
  357. /*
  358. * For some unknown reason, using LUT_ADDR doesn't work in some
  359. * cases (at least with only one byte long addresses), so
  360. * let's use LUT_MODE to write the address bytes one by one
  361. */
  362. for (i = 0; i < op->addr.nbytes; i++) {
  363. u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
  364. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
  365. LUT_PAD(op->addr.buswidth),
  366. addrbyte);
  367. lutidx++;
  368. }
  369. if (op->dummy.nbytes) {
  370. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  371. LUT_PAD(op->dummy.buswidth),
  372. op->dummy.nbytes * 8 /
  373. op->dummy.buswidth);
  374. lutidx++;
  375. }
  376. if (op->data.nbytes) {
  377. lutval[lutidx / 2] |= LUT_DEF(lutidx,
  378. op->data.dir == SPI_MEM_DATA_IN ?
  379. LUT_FSL_READ : LUT_FSL_WRITE,
  380. LUT_PAD(op->data.buswidth),
  381. 0);
  382. lutidx++;
  383. }
  384. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
  385. /* unlock LUT */
  386. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  387. qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
  388. /* fill LUT */
  389. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  390. qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
  391. /* lock LUT */
  392. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  393. qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
  394. }
  395. static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
  396. {
  397. int ret;
  398. ret = clk_prepare_enable(q->clk_en);
  399. if (ret)
  400. return ret;
  401. ret = clk_prepare_enable(q->clk);
  402. if (ret) {
  403. clk_disable_unprepare(q->clk_en);
  404. return ret;
  405. }
  406. if (needs_wakeup_wait_mode(q))
  407. cpu_latency_qos_add_request(&q->pm_qos_req, 0);
  408. return 0;
  409. }
  410. static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
  411. {
  412. if (needs_wakeup_wait_mode(q))
  413. cpu_latency_qos_remove_request(&q->pm_qos_req);
  414. clk_disable_unprepare(q->clk);
  415. clk_disable_unprepare(q->clk_en);
  416. }
  417. /*
  418. * If we have changed the content of the flash by writing or erasing, or if we
  419. * read from flash with a different offset into the page buffer, we need to
  420. * invalidate the AHB buffer. If we do not do so, we may read out the wrong
  421. * data. The spec tells us reset the AHB domain and Serial Flash domain at
  422. * the same time.
  423. */
  424. static void fsl_qspi_invalidate(struct fsl_qspi *q)
  425. {
  426. u32 reg;
  427. reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
  428. reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
  429. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  430. /*
  431. * The minimum delay : 1 AHB + 2 SFCK clocks.
  432. * Delay 1 us is enough.
  433. */
  434. udelay(1);
  435. reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
  436. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  437. }
  438. static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
  439. {
  440. unsigned long rate = spi->max_speed_hz;
  441. int ret;
  442. if (q->selected == spi->chip_select)
  443. return;
  444. if (needs_4x_clock(q))
  445. rate *= 4;
  446. fsl_qspi_clk_disable_unprep(q);
  447. ret = clk_set_rate(q->clk, rate);
  448. if (ret)
  449. return;
  450. ret = fsl_qspi_clk_prep_enable(q);
  451. if (ret)
  452. return;
  453. q->selected = spi->chip_select;
  454. fsl_qspi_invalidate(q);
  455. }
  456. static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
  457. {
  458. memcpy_fromio(op->data.buf.in,
  459. q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
  460. op->data.nbytes);
  461. }
  462. static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
  463. const struct spi_mem_op *op)
  464. {
  465. void __iomem *base = q->iobase;
  466. int i;
  467. u32 val;
  468. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  469. memcpy(&val, op->data.buf.out + i, 4);
  470. val = fsl_qspi_endian_xchg(q, val);
  471. qspi_writel(q, val, base + QUADSPI_TBDR);
  472. }
  473. if (i < op->data.nbytes) {
  474. memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
  475. val = fsl_qspi_endian_xchg(q, val);
  476. qspi_writel(q, val, base + QUADSPI_TBDR);
  477. }
  478. if (needs_fill_txfifo(q)) {
  479. for (i = op->data.nbytes; i < 16; i += 4)
  480. qspi_writel(q, 0, base + QUADSPI_TBDR);
  481. }
  482. }
  483. static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
  484. const struct spi_mem_op *op)
  485. {
  486. void __iomem *base = q->iobase;
  487. int i;
  488. u8 *buf = op->data.buf.in;
  489. u32 val;
  490. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  491. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  492. val = fsl_qspi_endian_xchg(q, val);
  493. memcpy(buf + i, &val, 4);
  494. }
  495. if (i < op->data.nbytes) {
  496. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  497. val = fsl_qspi_endian_xchg(q, val);
  498. memcpy(buf + i, &val, op->data.nbytes - i);
  499. }
  500. }
  501. static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
  502. {
  503. void __iomem *base = q->iobase;
  504. int err = 0;
  505. init_completion(&q->c);
  506. /*
  507. * Always start the sequence at the same index since we update
  508. * the LUT at each exec_op() call. And also specify the DATA
  509. * length, since it's has not been specified in the LUT.
  510. */
  511. qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
  512. base + QUADSPI_IPCR);
  513. /* Wait for the interrupt. */
  514. if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
  515. err = -ETIMEDOUT;
  516. if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  517. fsl_qspi_read_rxfifo(q, op);
  518. return err;
  519. }
  520. static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
  521. u32 mask, u32 delay_us, u32 timeout_us)
  522. {
  523. u32 reg;
  524. if (!q->devtype_data->little_endian)
  525. mask = (u32)cpu_to_be32(mask);
  526. return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
  527. timeout_us);
  528. }
  529. static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
  530. {
  531. struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
  532. void __iomem *base = q->iobase;
  533. u32 addr_offset = 0;
  534. int err = 0;
  535. int invalid_mstrid = q->devtype_data->invalid_mstrid;
  536. mutex_lock(&q->lock);
  537. /* wait for the controller being ready */
  538. fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
  539. QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
  540. fsl_qspi_select_mem(q, mem->spi);
  541. if (needs_amba_base_offset(q))
  542. addr_offset = q->memmap_phy;
  543. qspi_writel(q,
  544. q->selected * q->devtype_data->ahb_buf_size + addr_offset,
  545. base + QUADSPI_SFAR);
  546. qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
  547. QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
  548. base + QUADSPI_MCR);
  549. qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
  550. base + QUADSPI_SPTRCLR);
  551. qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);
  552. qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);
  553. qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);
  554. fsl_qspi_prepare_lut(q, op);
  555. /*
  556. * If we have large chunks of data, we read them through the AHB bus
  557. * by accessing the mapped memory. In all other cases we use
  558. * IP commands to access the flash.
  559. */
  560. if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
  561. op->data.dir == SPI_MEM_DATA_IN) {
  562. fsl_qspi_read_ahb(q, op);
  563. } else {
  564. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
  565. QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
  566. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  567. fsl_qspi_fill_txfifo(q, op);
  568. err = fsl_qspi_do_op(q, op);
  569. }
  570. /* Invalidate the data in the AHB buffer. */
  571. fsl_qspi_invalidate(q);
  572. mutex_unlock(&q->lock);
  573. return err;
  574. }
  575. static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
  576. {
  577. struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
  578. if (op->data.dir == SPI_MEM_DATA_OUT) {
  579. if (op->data.nbytes > q->devtype_data->txfifo)
  580. op->data.nbytes = q->devtype_data->txfifo;
  581. } else {
  582. if (op->data.nbytes > q->devtype_data->ahb_buf_size)
  583. op->data.nbytes = q->devtype_data->ahb_buf_size;
  584. else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
  585. op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  586. }
  587. return 0;
  588. }
  589. static int fsl_qspi_default_setup(struct fsl_qspi *q)
  590. {
  591. void __iomem *base = q->iobase;
  592. u32 reg, addr_offset = 0;
  593. int ret;
  594. /* disable and unprepare clock to avoid glitch pass to controller */
  595. fsl_qspi_clk_disable_unprep(q);
  596. /* the default frequency, we will change it later if necessary. */
  597. ret = clk_set_rate(q->clk, 66000000);
  598. if (ret)
  599. return ret;
  600. ret = fsl_qspi_clk_prep_enable(q);
  601. if (ret)
  602. return ret;
  603. /* Reset the module */
  604. qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
  605. base + QUADSPI_MCR);
  606. udelay(1);
  607. /* Disable the module */
  608. qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
  609. base + QUADSPI_MCR);
  610. /*
  611. * Previous boot stages (BootROM, bootloader) might have used DDR
  612. * mode and did not clear the TDH bits. As we currently use SDR mode
  613. * only, clear the TDH bits if necessary.
  614. */
  615. if (needs_tdh_setting(q))
  616. qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
  617. ~QUADSPI_FLSHCR_TDH_MASK,
  618. base + QUADSPI_FLSHCR);
  619. reg = qspi_readl(q, base + QUADSPI_SMPR);
  620. qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
  621. | QUADSPI_SMPR_FSPHS_MASK
  622. | QUADSPI_SMPR_HSENA_MASK
  623. | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
  624. /* We only use the buffer3 for AHB read */
  625. qspi_writel(q, 0, base + QUADSPI_BUF0IND);
  626. qspi_writel(q, 0, base + QUADSPI_BUF1IND);
  627. qspi_writel(q, 0, base + QUADSPI_BUF2IND);
  628. qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
  629. q->iobase + QUADSPI_BFGENCR);
  630. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
  631. qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
  632. QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
  633. base + QUADSPI_BUF3CR);
  634. if (needs_amba_base_offset(q))
  635. addr_offset = q->memmap_phy;
  636. /*
  637. * In HW there can be a maximum of four chips on two buses with
  638. * two chip selects on each bus. We use four chip selects in SW
  639. * to differentiate between the four chips.
  640. * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
  641. * SFB2AD accordingly.
  642. */
  643. qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
  644. base + QUADSPI_SFA1AD);
  645. qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
  646. base + QUADSPI_SFA2AD);
  647. qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
  648. base + QUADSPI_SFB1AD);
  649. qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
  650. base + QUADSPI_SFB2AD);
  651. q->selected = -1;
  652. /* Enable the module */
  653. qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
  654. base + QUADSPI_MCR);
  655. /* clear all interrupt status */
  656. qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
  657. /* enable the interrupt */
  658. qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
  659. return 0;
  660. }
  661. static const char *fsl_qspi_get_name(struct spi_mem *mem)
  662. {
  663. struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
  664. struct device *dev = &mem->spi->dev;
  665. const char *name;
  666. /*
  667. * In order to keep mtdparts compatible with the old MTD driver at
  668. * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
  669. * platform_device of the controller.
  670. */
  671. if (of_get_available_child_count(q->dev->of_node) == 1)
  672. return dev_name(q->dev);
  673. name = devm_kasprintf(dev, GFP_KERNEL,
  674. "%s-%d", dev_name(q->dev),
  675. mem->spi->chip_select);
  676. if (!name) {
  677. dev_err(dev, "failed to get memory for custom flash name\n");
  678. return ERR_PTR(-ENOMEM);
  679. }
  680. return name;
  681. }
  682. static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
  683. .adjust_op_size = fsl_qspi_adjust_op_size,
  684. .supports_op = fsl_qspi_supports_op,
  685. .exec_op = fsl_qspi_exec_op,
  686. .get_name = fsl_qspi_get_name,
  687. };
  688. static int fsl_qspi_probe(struct platform_device *pdev)
  689. {
  690. struct spi_controller *ctlr;
  691. struct device *dev = &pdev->dev;
  692. struct device_node *np = dev->of_node;
  693. struct resource *res;
  694. struct fsl_qspi *q;
  695. int ret;
  696. ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));
  697. if (!ctlr)
  698. return -ENOMEM;
  699. ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
  700. SPI_TX_DUAL | SPI_TX_QUAD;
  701. q = spi_controller_get_devdata(ctlr);
  702. q->dev = dev;
  703. q->devtype_data = of_device_get_match_data(dev);
  704. if (!q->devtype_data) {
  705. ret = -ENODEV;
  706. goto err_put_ctrl;
  707. }
  708. platform_set_drvdata(pdev, q);
  709. /* find the resources */
  710. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
  711. q->iobase = devm_ioremap_resource(dev, res);
  712. if (IS_ERR(q->iobase)) {
  713. ret = PTR_ERR(q->iobase);
  714. goto err_put_ctrl;
  715. }
  716. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  717. "QuadSPI-memory");
  718. q->memmap_phy = res->start;
  719. /* Since there are 4 cs, map size required is 4 times ahb_buf_size */
  720. q->ahb_addr = devm_ioremap(dev, q->memmap_phy,
  721. (q->devtype_data->ahb_buf_size * 4));
  722. if (!q->ahb_addr) {
  723. ret = -ENOMEM;
  724. goto err_put_ctrl;
  725. }
  726. /* find the clocks */
  727. q->clk_en = devm_clk_get(dev, "qspi_en");
  728. if (IS_ERR(q->clk_en)) {
  729. ret = PTR_ERR(q->clk_en);
  730. goto err_put_ctrl;
  731. }
  732. q->clk = devm_clk_get(dev, "qspi");
  733. if (IS_ERR(q->clk)) {
  734. ret = PTR_ERR(q->clk);
  735. goto err_put_ctrl;
  736. }
  737. ret = fsl_qspi_clk_prep_enable(q);
  738. if (ret) {
  739. dev_err(dev, "can not enable the clock\n");
  740. goto err_put_ctrl;
  741. }
  742. /* find the irq */
  743. ret = platform_get_irq(pdev, 0);
  744. if (ret < 0)
  745. goto err_disable_clk;
  746. ret = devm_request_irq(dev, ret,
  747. fsl_qspi_irq_handler, 0, pdev->name, q);
  748. if (ret) {
  749. dev_err(dev, "failed to request irq: %d\n", ret);
  750. goto err_disable_clk;
  751. }
  752. mutex_init(&q->lock);
  753. ctlr->bus_num = -1;
  754. ctlr->num_chipselect = 4;
  755. ctlr->mem_ops = &fsl_qspi_mem_ops;
  756. fsl_qspi_default_setup(q);
  757. ctlr->dev.of_node = np;
  758. ret = devm_spi_register_controller(dev, ctlr);
  759. if (ret)
  760. goto err_destroy_mutex;
  761. return 0;
  762. err_destroy_mutex:
  763. mutex_destroy(&q->lock);
  764. err_disable_clk:
  765. fsl_qspi_clk_disable_unprep(q);
  766. err_put_ctrl:
  767. spi_controller_put(ctlr);
  768. dev_err(dev, "Freescale QuadSPI probe failed\n");
  769. return ret;
  770. }
  771. static int fsl_qspi_remove(struct platform_device *pdev)
  772. {
  773. struct fsl_qspi *q = platform_get_drvdata(pdev);
  774. /* disable the hardware */
  775. qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
  776. qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
  777. fsl_qspi_clk_disable_unprep(q);
  778. mutex_destroy(&q->lock);
  779. return 0;
  780. }
  781. static int fsl_qspi_suspend(struct device *dev)
  782. {
  783. return 0;
  784. }
  785. static int fsl_qspi_resume(struct device *dev)
  786. {
  787. struct fsl_qspi *q = dev_get_drvdata(dev);
  788. fsl_qspi_default_setup(q);
  789. return 0;
  790. }
  791. static const struct of_device_id fsl_qspi_dt_ids[] = {
  792. { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
  793. { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
  794. { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
  795. { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
  796. { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
  797. { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
  798. { /* sentinel */ }
  799. };
  800. MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
  801. static const struct dev_pm_ops fsl_qspi_pm_ops = {
  802. .suspend = fsl_qspi_suspend,
  803. .resume = fsl_qspi_resume,
  804. };
  805. static struct platform_driver fsl_qspi_driver = {
  806. .driver = {
  807. .name = "fsl-quadspi",
  808. .of_match_table = fsl_qspi_dt_ids,
  809. .pm = &fsl_qspi_pm_ops,
  810. },
  811. .probe = fsl_qspi_probe,
  812. .remove = fsl_qspi_remove,
  813. };
  814. module_platform_driver(fsl_qspi_driver);
  815. MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
  816. MODULE_AUTHOR("Freescale Semiconductor Inc.");
  817. MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>");
  818. MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
  819. MODULE_AUTHOR("Yogesh Gaur <yogeshnarayan.gaur@nxp.com>");
  820. MODULE_AUTHOR("Suresh Gupta <suresh.gupta@nxp.com>");
  821. MODULE_LICENSE("GPL v2");