spi-fsl-lpspi.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Freescale i.MX7ULP LPSPI driver
  4. //
  5. // Copyright 2016 Freescale Semiconductor, Inc.
  6. // Copyright 2018 NXP Semiconductors
  7. #include <linux/clk.h>
  8. #include <linux/completion.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/err.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/irq.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/pinctrl/consumer.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/platform_data/dma-imx.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/slab.h>
  25. #include <linux/spi/spi.h>
  26. #include <linux/spi/spi_bitbang.h>
  27. #include <linux/types.h>
  28. #define DRIVER_NAME "fsl_lpspi"
  29. #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
  30. /* The maximum bytes that edma can transfer once.*/
  31. #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
  32. /* i.MX7ULP LPSPI registers */
  33. #define IMX7ULP_VERID 0x0
  34. #define IMX7ULP_PARAM 0x4
  35. #define IMX7ULP_CR 0x10
  36. #define IMX7ULP_SR 0x14
  37. #define IMX7ULP_IER 0x18
  38. #define IMX7ULP_DER 0x1c
  39. #define IMX7ULP_CFGR0 0x20
  40. #define IMX7ULP_CFGR1 0x24
  41. #define IMX7ULP_DMR0 0x30
  42. #define IMX7ULP_DMR1 0x34
  43. #define IMX7ULP_CCR 0x40
  44. #define IMX7ULP_FCR 0x58
  45. #define IMX7ULP_FSR 0x5c
  46. #define IMX7ULP_TCR 0x60
  47. #define IMX7ULP_TDR 0x64
  48. #define IMX7ULP_RSR 0x70
  49. #define IMX7ULP_RDR 0x74
  50. /* General control register field define */
  51. #define CR_RRF BIT(9)
  52. #define CR_RTF BIT(8)
  53. #define CR_RST BIT(1)
  54. #define CR_MEN BIT(0)
  55. #define SR_MBF BIT(24)
  56. #define SR_TCF BIT(10)
  57. #define SR_FCF BIT(9)
  58. #define SR_RDF BIT(1)
  59. #define SR_TDF BIT(0)
  60. #define IER_TCIE BIT(10)
  61. #define IER_FCIE BIT(9)
  62. #define IER_RDIE BIT(1)
  63. #define IER_TDIE BIT(0)
  64. #define DER_RDDE BIT(1)
  65. #define DER_TDDE BIT(0)
  66. #define CFGR1_PCSCFG BIT(27)
  67. #define CFGR1_PINCFG (BIT(24)|BIT(25))
  68. #define CFGR1_PCSPOL BIT(8)
  69. #define CFGR1_NOSTALL BIT(3)
  70. #define CFGR1_MASTER BIT(0)
  71. #define FSR_TXCOUNT (0xFF)
  72. #define RSR_RXEMPTY BIT(1)
  73. #define TCR_CPOL BIT(31)
  74. #define TCR_CPHA BIT(30)
  75. #define TCR_CONT BIT(21)
  76. #define TCR_CONTC BIT(20)
  77. #define TCR_RXMSK BIT(19)
  78. #define TCR_TXMSK BIT(18)
  79. struct lpspi_config {
  80. u8 bpw;
  81. u8 chip_select;
  82. u8 prescale;
  83. u16 mode;
  84. u32 speed_hz;
  85. };
  86. struct fsl_lpspi_data {
  87. struct device *dev;
  88. void __iomem *base;
  89. unsigned long base_phys;
  90. struct clk *clk_ipg;
  91. struct clk *clk_per;
  92. bool is_slave;
  93. bool is_only_cs1;
  94. bool is_first_byte;
  95. void *rx_buf;
  96. const void *tx_buf;
  97. void (*tx)(struct fsl_lpspi_data *);
  98. void (*rx)(struct fsl_lpspi_data *);
  99. u32 remain;
  100. u8 watermark;
  101. u8 txfifosize;
  102. u8 rxfifosize;
  103. struct lpspi_config config;
  104. struct completion xfer_done;
  105. bool slave_aborted;
  106. /* DMA */
  107. bool usedma;
  108. struct completion dma_rx_completion;
  109. struct completion dma_tx_completion;
  110. };
  111. static const struct of_device_id fsl_lpspi_dt_ids[] = {
  112. { .compatible = "fsl,imx7ulp-spi", },
  113. { /* sentinel */ }
  114. };
  115. MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
  116. #define LPSPI_BUF_RX(type) \
  117. static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
  118. { \
  119. unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
  120. \
  121. if (fsl_lpspi->rx_buf) { \
  122. *(type *)fsl_lpspi->rx_buf = val; \
  123. fsl_lpspi->rx_buf += sizeof(type); \
  124. } \
  125. }
  126. #define LPSPI_BUF_TX(type) \
  127. static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
  128. { \
  129. type val = 0; \
  130. \
  131. if (fsl_lpspi->tx_buf) { \
  132. val = *(type *)fsl_lpspi->tx_buf; \
  133. fsl_lpspi->tx_buf += sizeof(type); \
  134. } \
  135. \
  136. fsl_lpspi->remain -= sizeof(type); \
  137. writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
  138. }
  139. LPSPI_BUF_RX(u8)
  140. LPSPI_BUF_TX(u8)
  141. LPSPI_BUF_RX(u16)
  142. LPSPI_BUF_TX(u16)
  143. LPSPI_BUF_RX(u32)
  144. LPSPI_BUF_TX(u32)
  145. static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
  146. unsigned int enable)
  147. {
  148. writel(enable, fsl_lpspi->base + IMX7ULP_IER);
  149. }
  150. static int fsl_lpspi_bytes_per_word(const int bpw)
  151. {
  152. return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
  153. }
  154. static bool fsl_lpspi_can_dma(struct spi_controller *controller,
  155. struct spi_device *spi,
  156. struct spi_transfer *transfer)
  157. {
  158. unsigned int bytes_per_word;
  159. if (!controller->dma_rx)
  160. return false;
  161. bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
  162. switch (bytes_per_word) {
  163. case 1:
  164. case 2:
  165. case 4:
  166. break;
  167. default:
  168. return false;
  169. }
  170. return true;
  171. }
  172. static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
  173. {
  174. struct fsl_lpspi_data *fsl_lpspi =
  175. spi_controller_get_devdata(controller);
  176. int ret;
  177. ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
  178. if (ret < 0) {
  179. dev_err(fsl_lpspi->dev, "failed to enable clock\n");
  180. return ret;
  181. }
  182. return 0;
  183. }
  184. static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
  185. {
  186. struct fsl_lpspi_data *fsl_lpspi =
  187. spi_controller_get_devdata(controller);
  188. pm_runtime_mark_last_busy(fsl_lpspi->dev);
  189. pm_runtime_put_autosuspend(fsl_lpspi->dev);
  190. return 0;
  191. }
  192. static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
  193. {
  194. u8 txfifo_cnt;
  195. u32 temp;
  196. txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
  197. while (txfifo_cnt < fsl_lpspi->txfifosize) {
  198. if (!fsl_lpspi->remain)
  199. break;
  200. fsl_lpspi->tx(fsl_lpspi);
  201. txfifo_cnt++;
  202. }
  203. if (txfifo_cnt < fsl_lpspi->txfifosize) {
  204. if (!fsl_lpspi->is_slave) {
  205. temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
  206. temp &= ~TCR_CONTC;
  207. writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
  208. }
  209. fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
  210. } else
  211. fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
  212. }
  213. static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
  214. {
  215. while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
  216. fsl_lpspi->rx(fsl_lpspi);
  217. }
  218. static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
  219. {
  220. u32 temp = 0;
  221. temp |= fsl_lpspi->config.bpw - 1;
  222. temp |= (fsl_lpspi->config.mode & 0x3) << 30;
  223. temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
  224. if (!fsl_lpspi->is_slave) {
  225. temp |= fsl_lpspi->config.prescale << 27;
  226. /*
  227. * Set TCR_CONT will keep SS asserted after current transfer.
  228. * For the first transfer, clear TCR_CONTC to assert SS.
  229. * For subsequent transfer, set TCR_CONTC to keep SS asserted.
  230. */
  231. if (!fsl_lpspi->usedma) {
  232. temp |= TCR_CONT;
  233. if (fsl_lpspi->is_first_byte)
  234. temp &= ~TCR_CONTC;
  235. else
  236. temp |= TCR_CONTC;
  237. }
  238. }
  239. writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
  240. dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
  241. }
  242. static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
  243. {
  244. u32 temp;
  245. if (!fsl_lpspi->usedma)
  246. temp = fsl_lpspi->watermark >> 1 |
  247. (fsl_lpspi->watermark >> 1) << 16;
  248. else
  249. temp = fsl_lpspi->watermark >> 1;
  250. writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
  251. dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
  252. }
  253. static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
  254. {
  255. struct lpspi_config config = fsl_lpspi->config;
  256. unsigned int perclk_rate, scldiv;
  257. u8 prescale;
  258. perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
  259. if (config.speed_hz > perclk_rate / 2) {
  260. dev_err(fsl_lpspi->dev,
  261. "per-clk should be at least two times of transfer speed");
  262. return -EINVAL;
  263. }
  264. for (prescale = 0; prescale < 8; prescale++) {
  265. scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2;
  266. if (scldiv < 256) {
  267. fsl_lpspi->config.prescale = prescale;
  268. break;
  269. }
  270. }
  271. if (scldiv >= 256)
  272. return -EINVAL;
  273. writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
  274. fsl_lpspi->base + IMX7ULP_CCR);
  275. dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
  276. perclk_rate, config.speed_hz, prescale, scldiv);
  277. return 0;
  278. }
  279. static int fsl_lpspi_dma_configure(struct spi_controller *controller)
  280. {
  281. int ret;
  282. enum dma_slave_buswidth buswidth;
  283. struct dma_slave_config rx = {}, tx = {};
  284. struct fsl_lpspi_data *fsl_lpspi =
  285. spi_controller_get_devdata(controller);
  286. switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
  287. case 4:
  288. buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
  289. break;
  290. case 2:
  291. buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
  292. break;
  293. case 1:
  294. buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
  295. break;
  296. default:
  297. return -EINVAL;
  298. }
  299. tx.direction = DMA_MEM_TO_DEV;
  300. tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
  301. tx.dst_addr_width = buswidth;
  302. tx.dst_maxburst = 1;
  303. ret = dmaengine_slave_config(controller->dma_tx, &tx);
  304. if (ret) {
  305. dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
  306. ret);
  307. return ret;
  308. }
  309. rx.direction = DMA_DEV_TO_MEM;
  310. rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
  311. rx.src_addr_width = buswidth;
  312. rx.src_maxburst = 1;
  313. ret = dmaengine_slave_config(controller->dma_rx, &rx);
  314. if (ret) {
  315. dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
  316. ret);
  317. return ret;
  318. }
  319. return 0;
  320. }
  321. static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
  322. {
  323. u32 temp;
  324. int ret;
  325. if (!fsl_lpspi->is_slave) {
  326. ret = fsl_lpspi_set_bitrate(fsl_lpspi);
  327. if (ret)
  328. return ret;
  329. }
  330. fsl_lpspi_set_watermark(fsl_lpspi);
  331. if (!fsl_lpspi->is_slave)
  332. temp = CFGR1_MASTER;
  333. else
  334. temp = CFGR1_PINCFG;
  335. if (fsl_lpspi->config.mode & SPI_CS_HIGH)
  336. temp |= CFGR1_PCSPOL;
  337. writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
  338. temp = readl(fsl_lpspi->base + IMX7ULP_CR);
  339. temp |= CR_RRF | CR_RTF | CR_MEN;
  340. writel(temp, fsl_lpspi->base + IMX7ULP_CR);
  341. temp = 0;
  342. if (fsl_lpspi->usedma)
  343. temp = DER_TDDE | DER_RDDE;
  344. writel(temp, fsl_lpspi->base + IMX7ULP_DER);
  345. return 0;
  346. }
  347. static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
  348. struct spi_device *spi,
  349. struct spi_transfer *t)
  350. {
  351. struct fsl_lpspi_data *fsl_lpspi =
  352. spi_controller_get_devdata(spi->controller);
  353. if (t == NULL)
  354. return -EINVAL;
  355. fsl_lpspi->config.mode = spi->mode;
  356. fsl_lpspi->config.bpw = t->bits_per_word;
  357. fsl_lpspi->config.speed_hz = t->speed_hz;
  358. if (fsl_lpspi->is_only_cs1)
  359. fsl_lpspi->config.chip_select = 1;
  360. else
  361. fsl_lpspi->config.chip_select = spi->chip_select;
  362. if (!fsl_lpspi->config.speed_hz)
  363. fsl_lpspi->config.speed_hz = spi->max_speed_hz;
  364. if (!fsl_lpspi->config.bpw)
  365. fsl_lpspi->config.bpw = spi->bits_per_word;
  366. /* Initialize the functions for transfer */
  367. if (fsl_lpspi->config.bpw <= 8) {
  368. fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
  369. fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
  370. } else if (fsl_lpspi->config.bpw <= 16) {
  371. fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
  372. fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
  373. } else {
  374. fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
  375. fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
  376. }
  377. if (t->len <= fsl_lpspi->txfifosize)
  378. fsl_lpspi->watermark = t->len;
  379. else
  380. fsl_lpspi->watermark = fsl_lpspi->txfifosize;
  381. if (fsl_lpspi_can_dma(controller, spi, t))
  382. fsl_lpspi->usedma = true;
  383. else
  384. fsl_lpspi->usedma = false;
  385. return fsl_lpspi_config(fsl_lpspi);
  386. }
  387. static int fsl_lpspi_slave_abort(struct spi_controller *controller)
  388. {
  389. struct fsl_lpspi_data *fsl_lpspi =
  390. spi_controller_get_devdata(controller);
  391. fsl_lpspi->slave_aborted = true;
  392. if (!fsl_lpspi->usedma)
  393. complete(&fsl_lpspi->xfer_done);
  394. else {
  395. complete(&fsl_lpspi->dma_tx_completion);
  396. complete(&fsl_lpspi->dma_rx_completion);
  397. }
  398. return 0;
  399. }
  400. static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
  401. {
  402. struct fsl_lpspi_data *fsl_lpspi =
  403. spi_controller_get_devdata(controller);
  404. if (fsl_lpspi->is_slave) {
  405. if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
  406. fsl_lpspi->slave_aborted) {
  407. dev_dbg(fsl_lpspi->dev, "interrupted\n");
  408. return -EINTR;
  409. }
  410. } else {
  411. if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
  412. dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
  413. return -ETIMEDOUT;
  414. }
  415. }
  416. return 0;
  417. }
  418. static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
  419. {
  420. u32 temp;
  421. if (!fsl_lpspi->usedma) {
  422. /* Disable all interrupt */
  423. fsl_lpspi_intctrl(fsl_lpspi, 0);
  424. }
  425. /* W1C for all flags in SR */
  426. temp = 0x3F << 8;
  427. writel(temp, fsl_lpspi->base + IMX7ULP_SR);
  428. /* Clear FIFO and disable module */
  429. temp = CR_RRF | CR_RTF;
  430. writel(temp, fsl_lpspi->base + IMX7ULP_CR);
  431. return 0;
  432. }
  433. static void fsl_lpspi_dma_rx_callback(void *cookie)
  434. {
  435. struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
  436. complete(&fsl_lpspi->dma_rx_completion);
  437. }
  438. static void fsl_lpspi_dma_tx_callback(void *cookie)
  439. {
  440. struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
  441. complete(&fsl_lpspi->dma_tx_completion);
  442. }
  443. static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
  444. int size)
  445. {
  446. unsigned long timeout = 0;
  447. /* Time with actual data transfer and CS change delay related to HW */
  448. timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
  449. /* Add extra second for scheduler related activities */
  450. timeout += 1;
  451. /* Double calculated timeout */
  452. return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
  453. }
  454. static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
  455. struct fsl_lpspi_data *fsl_lpspi,
  456. struct spi_transfer *transfer)
  457. {
  458. struct dma_async_tx_descriptor *desc_tx, *desc_rx;
  459. unsigned long transfer_timeout;
  460. unsigned long timeout;
  461. struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
  462. int ret;
  463. ret = fsl_lpspi_dma_configure(controller);
  464. if (ret)
  465. return ret;
  466. desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
  467. rx->sgl, rx->nents, DMA_DEV_TO_MEM,
  468. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  469. if (!desc_rx)
  470. return -EINVAL;
  471. desc_rx->callback = fsl_lpspi_dma_rx_callback;
  472. desc_rx->callback_param = (void *)fsl_lpspi;
  473. dmaengine_submit(desc_rx);
  474. reinit_completion(&fsl_lpspi->dma_rx_completion);
  475. dma_async_issue_pending(controller->dma_rx);
  476. desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
  477. tx->sgl, tx->nents, DMA_MEM_TO_DEV,
  478. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  479. if (!desc_tx) {
  480. dmaengine_terminate_all(controller->dma_tx);
  481. return -EINVAL;
  482. }
  483. desc_tx->callback = fsl_lpspi_dma_tx_callback;
  484. desc_tx->callback_param = (void *)fsl_lpspi;
  485. dmaengine_submit(desc_tx);
  486. reinit_completion(&fsl_lpspi->dma_tx_completion);
  487. dma_async_issue_pending(controller->dma_tx);
  488. fsl_lpspi->slave_aborted = false;
  489. if (!fsl_lpspi->is_slave) {
  490. transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
  491. transfer->len);
  492. /* Wait eDMA to finish the data transfer.*/
  493. timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
  494. transfer_timeout);
  495. if (!timeout) {
  496. dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
  497. dmaengine_terminate_all(controller->dma_tx);
  498. dmaengine_terminate_all(controller->dma_rx);
  499. fsl_lpspi_reset(fsl_lpspi);
  500. return -ETIMEDOUT;
  501. }
  502. timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
  503. transfer_timeout);
  504. if (!timeout) {
  505. dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
  506. dmaengine_terminate_all(controller->dma_tx);
  507. dmaengine_terminate_all(controller->dma_rx);
  508. fsl_lpspi_reset(fsl_lpspi);
  509. return -ETIMEDOUT;
  510. }
  511. } else {
  512. if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
  513. fsl_lpspi->slave_aborted) {
  514. dev_dbg(fsl_lpspi->dev,
  515. "I/O Error in DMA TX interrupted\n");
  516. dmaengine_terminate_all(controller->dma_tx);
  517. dmaengine_terminate_all(controller->dma_rx);
  518. fsl_lpspi_reset(fsl_lpspi);
  519. return -EINTR;
  520. }
  521. if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
  522. fsl_lpspi->slave_aborted) {
  523. dev_dbg(fsl_lpspi->dev,
  524. "I/O Error in DMA RX interrupted\n");
  525. dmaengine_terminate_all(controller->dma_tx);
  526. dmaengine_terminate_all(controller->dma_rx);
  527. fsl_lpspi_reset(fsl_lpspi);
  528. return -EINTR;
  529. }
  530. }
  531. fsl_lpspi_reset(fsl_lpspi);
  532. return 0;
  533. }
  534. static void fsl_lpspi_dma_exit(struct spi_controller *controller)
  535. {
  536. if (controller->dma_rx) {
  537. dma_release_channel(controller->dma_rx);
  538. controller->dma_rx = NULL;
  539. }
  540. if (controller->dma_tx) {
  541. dma_release_channel(controller->dma_tx);
  542. controller->dma_tx = NULL;
  543. }
  544. }
  545. static int fsl_lpspi_dma_init(struct device *dev,
  546. struct fsl_lpspi_data *fsl_lpspi,
  547. struct spi_controller *controller)
  548. {
  549. int ret;
  550. /* Prepare for TX DMA: */
  551. controller->dma_tx = dma_request_chan(dev, "tx");
  552. if (IS_ERR(controller->dma_tx)) {
  553. ret = PTR_ERR(controller->dma_tx);
  554. dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
  555. controller->dma_tx = NULL;
  556. goto err;
  557. }
  558. /* Prepare for RX DMA: */
  559. controller->dma_rx = dma_request_chan(dev, "rx");
  560. if (IS_ERR(controller->dma_rx)) {
  561. ret = PTR_ERR(controller->dma_rx);
  562. dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
  563. controller->dma_rx = NULL;
  564. goto err;
  565. }
  566. init_completion(&fsl_lpspi->dma_rx_completion);
  567. init_completion(&fsl_lpspi->dma_tx_completion);
  568. controller->can_dma = fsl_lpspi_can_dma;
  569. controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
  570. return 0;
  571. err:
  572. fsl_lpspi_dma_exit(controller);
  573. return ret;
  574. }
  575. static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
  576. struct spi_transfer *t)
  577. {
  578. struct fsl_lpspi_data *fsl_lpspi =
  579. spi_controller_get_devdata(controller);
  580. int ret;
  581. fsl_lpspi->tx_buf = t->tx_buf;
  582. fsl_lpspi->rx_buf = t->rx_buf;
  583. fsl_lpspi->remain = t->len;
  584. reinit_completion(&fsl_lpspi->xfer_done);
  585. fsl_lpspi->slave_aborted = false;
  586. fsl_lpspi_write_tx_fifo(fsl_lpspi);
  587. ret = fsl_lpspi_wait_for_completion(controller);
  588. if (ret)
  589. return ret;
  590. fsl_lpspi_reset(fsl_lpspi);
  591. return 0;
  592. }
  593. static int fsl_lpspi_transfer_one(struct spi_controller *controller,
  594. struct spi_device *spi,
  595. struct spi_transfer *t)
  596. {
  597. struct fsl_lpspi_data *fsl_lpspi =
  598. spi_controller_get_devdata(controller);
  599. int ret;
  600. fsl_lpspi->is_first_byte = true;
  601. ret = fsl_lpspi_setup_transfer(controller, spi, t);
  602. if (ret < 0)
  603. return ret;
  604. fsl_lpspi_set_cmd(fsl_lpspi);
  605. fsl_lpspi->is_first_byte = false;
  606. if (fsl_lpspi->usedma)
  607. ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
  608. else
  609. ret = fsl_lpspi_pio_transfer(controller, t);
  610. if (ret < 0)
  611. return ret;
  612. return 0;
  613. }
  614. static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
  615. {
  616. u32 temp_SR, temp_IER;
  617. struct fsl_lpspi_data *fsl_lpspi = dev_id;
  618. temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
  619. fsl_lpspi_intctrl(fsl_lpspi, 0);
  620. temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
  621. fsl_lpspi_read_rx_fifo(fsl_lpspi);
  622. if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
  623. fsl_lpspi_write_tx_fifo(fsl_lpspi);
  624. return IRQ_HANDLED;
  625. }
  626. if (temp_SR & SR_MBF ||
  627. readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
  628. writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
  629. fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
  630. return IRQ_HANDLED;
  631. }
  632. if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
  633. writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
  634. complete(&fsl_lpspi->xfer_done);
  635. return IRQ_HANDLED;
  636. }
  637. return IRQ_NONE;
  638. }
  639. #ifdef CONFIG_PM
  640. static int fsl_lpspi_runtime_resume(struct device *dev)
  641. {
  642. struct spi_controller *controller = dev_get_drvdata(dev);
  643. struct fsl_lpspi_data *fsl_lpspi;
  644. int ret;
  645. fsl_lpspi = spi_controller_get_devdata(controller);
  646. ret = clk_prepare_enable(fsl_lpspi->clk_per);
  647. if (ret)
  648. return ret;
  649. ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
  650. if (ret) {
  651. clk_disable_unprepare(fsl_lpspi->clk_per);
  652. return ret;
  653. }
  654. return 0;
  655. }
  656. static int fsl_lpspi_runtime_suspend(struct device *dev)
  657. {
  658. struct spi_controller *controller = dev_get_drvdata(dev);
  659. struct fsl_lpspi_data *fsl_lpspi;
  660. fsl_lpspi = spi_controller_get_devdata(controller);
  661. clk_disable_unprepare(fsl_lpspi->clk_per);
  662. clk_disable_unprepare(fsl_lpspi->clk_ipg);
  663. return 0;
  664. }
  665. #endif
  666. static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
  667. {
  668. struct device *dev = fsl_lpspi->dev;
  669. pm_runtime_enable(dev);
  670. pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
  671. pm_runtime_use_autosuspend(dev);
  672. return 0;
  673. }
  674. static int fsl_lpspi_probe(struct platform_device *pdev)
  675. {
  676. struct fsl_lpspi_data *fsl_lpspi;
  677. struct spi_controller *controller;
  678. struct resource *res;
  679. int ret, irq;
  680. u32 temp;
  681. bool is_slave;
  682. is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
  683. if (is_slave)
  684. controller = spi_alloc_slave(&pdev->dev,
  685. sizeof(struct fsl_lpspi_data));
  686. else
  687. controller = spi_alloc_master(&pdev->dev,
  688. sizeof(struct fsl_lpspi_data));
  689. if (!controller)
  690. return -ENOMEM;
  691. platform_set_drvdata(pdev, controller);
  692. fsl_lpspi = spi_controller_get_devdata(controller);
  693. fsl_lpspi->dev = &pdev->dev;
  694. fsl_lpspi->is_slave = is_slave;
  695. fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
  696. "fsl,spi-only-use-cs1-sel");
  697. controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
  698. controller->transfer_one = fsl_lpspi_transfer_one;
  699. controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
  700. controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
  701. controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  702. controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
  703. controller->dev.of_node = pdev->dev.of_node;
  704. controller->bus_num = pdev->id;
  705. controller->slave_abort = fsl_lpspi_slave_abort;
  706. if (!fsl_lpspi->is_slave)
  707. controller->use_gpio_descriptors = true;
  708. init_completion(&fsl_lpspi->xfer_done);
  709. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  710. fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
  711. if (IS_ERR(fsl_lpspi->base)) {
  712. ret = PTR_ERR(fsl_lpspi->base);
  713. goto out_controller_put;
  714. }
  715. fsl_lpspi->base_phys = res->start;
  716. irq = platform_get_irq(pdev, 0);
  717. if (irq < 0) {
  718. ret = irq;
  719. goto out_controller_put;
  720. }
  721. ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
  722. dev_name(&pdev->dev), fsl_lpspi);
  723. if (ret) {
  724. dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
  725. goto out_controller_put;
  726. }
  727. fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
  728. if (IS_ERR(fsl_lpspi->clk_per)) {
  729. ret = PTR_ERR(fsl_lpspi->clk_per);
  730. goto out_controller_put;
  731. }
  732. fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  733. if (IS_ERR(fsl_lpspi->clk_ipg)) {
  734. ret = PTR_ERR(fsl_lpspi->clk_ipg);
  735. goto out_controller_put;
  736. }
  737. /* enable the clock */
  738. ret = fsl_lpspi_init_rpm(fsl_lpspi);
  739. if (ret)
  740. goto out_controller_put;
  741. ret = pm_runtime_get_sync(fsl_lpspi->dev);
  742. if (ret < 0) {
  743. dev_err(fsl_lpspi->dev, "failed to enable clock\n");
  744. goto out_pm_get;
  745. }
  746. temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
  747. fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
  748. fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
  749. ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
  750. if (ret == -EPROBE_DEFER)
  751. goto out_pm_get;
  752. if (ret < 0)
  753. dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
  754. ret = devm_spi_register_controller(&pdev->dev, controller);
  755. if (ret < 0) {
  756. dev_err(&pdev->dev, "spi_register_controller error.\n");
  757. goto out_pm_get;
  758. }
  759. pm_runtime_mark_last_busy(fsl_lpspi->dev);
  760. pm_runtime_put_autosuspend(fsl_lpspi->dev);
  761. return 0;
  762. out_pm_get:
  763. pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
  764. pm_runtime_put_sync(fsl_lpspi->dev);
  765. pm_runtime_disable(fsl_lpspi->dev);
  766. out_controller_put:
  767. spi_controller_put(controller);
  768. return ret;
  769. }
  770. static int fsl_lpspi_remove(struct platform_device *pdev)
  771. {
  772. struct spi_controller *controller = platform_get_drvdata(pdev);
  773. struct fsl_lpspi_data *fsl_lpspi =
  774. spi_controller_get_devdata(controller);
  775. pm_runtime_disable(fsl_lpspi->dev);
  776. return 0;
  777. }
  778. static int __maybe_unused fsl_lpspi_suspend(struct device *dev)
  779. {
  780. int ret;
  781. pinctrl_pm_select_sleep_state(dev);
  782. ret = pm_runtime_force_suspend(dev);
  783. return ret;
  784. }
  785. static int __maybe_unused fsl_lpspi_resume(struct device *dev)
  786. {
  787. int ret;
  788. ret = pm_runtime_force_resume(dev);
  789. if (ret) {
  790. dev_err(dev, "Error in resume: %d\n", ret);
  791. return ret;
  792. }
  793. pinctrl_pm_select_default_state(dev);
  794. return 0;
  795. }
  796. static const struct dev_pm_ops fsl_lpspi_pm_ops = {
  797. SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
  798. fsl_lpspi_runtime_resume, NULL)
  799. SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
  800. };
  801. static struct platform_driver fsl_lpspi_driver = {
  802. .driver = {
  803. .name = DRIVER_NAME,
  804. .of_match_table = fsl_lpspi_dt_ids,
  805. .pm = &fsl_lpspi_pm_ops,
  806. },
  807. .probe = fsl_lpspi_probe,
  808. .remove = fsl_lpspi_remove,
  809. };
  810. module_platform_driver(fsl_lpspi_driver);
  811. MODULE_DESCRIPTION("LPSPI Controller driver");
  812. MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
  813. MODULE_LICENSE("GPL");