spi-fsl-lib.h 3.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Freescale SPI/eSPI controller driver library.
  4. *
  5. * Maintainer: Kumar Gala
  6. *
  7. * Copyright 2010 Freescale Semiconductor, Inc.
  8. * Copyright (C) 2006 Polycom, Inc.
  9. *
  10. * CPM SPI and QE buffer descriptors mode support:
  11. * Copyright (c) 2009 MontaVista Software, Inc.
  12. * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  13. */
  14. #ifndef __SPI_FSL_LIB_H__
  15. #define __SPI_FSL_LIB_H__
  16. #include <asm/io.h>
  17. /* SPI/eSPI Controller driver's private data. */
  18. struct mpc8xxx_spi {
  19. struct device *dev;
  20. void __iomem *reg_base;
  21. /* rx & tx bufs from the spi_transfer */
  22. const void *tx;
  23. void *rx;
  24. int subblock;
  25. struct spi_pram __iomem *pram;
  26. #ifdef CONFIG_FSL_SOC
  27. struct cpm_buf_desc __iomem *tx_bd;
  28. struct cpm_buf_desc __iomem *rx_bd;
  29. #endif
  30. struct spi_transfer *xfer_in_progress;
  31. /* dma addresses for CPM transfers */
  32. dma_addr_t tx_dma;
  33. dma_addr_t rx_dma;
  34. bool map_tx_dma;
  35. bool map_rx_dma;
  36. dma_addr_t dma_dummy_tx;
  37. dma_addr_t dma_dummy_rx;
  38. /* functions to deal with different sized buffers */
  39. void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
  40. u32(*get_tx) (struct mpc8xxx_spi *);
  41. unsigned int count;
  42. unsigned int irq;
  43. unsigned nsecs; /* (clock cycle time)/2 */
  44. u32 spibrg; /* SPIBRG input clock */
  45. u32 rx_shift; /* RX data reg shift when in qe mode */
  46. u32 tx_shift; /* TX data reg shift when in qe mode */
  47. unsigned int flags;
  48. #if IS_ENABLED(CONFIG_SPI_FSL_SPI)
  49. int type;
  50. int native_chipselects;
  51. u8 max_bits_per_word;
  52. void (*set_shifts)(u32 *rx_shift, u32 *tx_shift,
  53. int bits_per_word, int msb_first);
  54. #endif
  55. struct completion done;
  56. };
  57. struct spi_mpc8xxx_cs {
  58. /* functions to deal with different sized buffers */
  59. void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
  60. u32 (*get_tx) (struct mpc8xxx_spi *);
  61. u32 rx_shift; /* RX data reg shift when in qe mode */
  62. u32 tx_shift; /* TX data reg shift when in qe mode */
  63. u32 hw_mode; /* Holds HW mode register settings */
  64. };
  65. static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
  66. {
  67. iowrite32be(val, reg);
  68. }
  69. static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
  70. {
  71. return ioread32be(reg);
  72. }
  73. struct mpc8xxx_spi_probe_info {
  74. struct fsl_spi_platform_data pdata;
  75. __be32 __iomem *immr_spi_cs;
  76. };
  77. extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi);
  78. extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi);
  79. extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi);
  80. extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
  81. extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
  82. extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
  83. extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
  84. struct fsl_spi_platform_data *pdata);
  85. extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
  86. struct spi_transfer *t, unsigned int len);
  87. extern const char *mpc8xxx_spi_strmode(unsigned int flags);
  88. extern void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
  89. unsigned int irq);
  90. extern int mpc8xxx_spi_remove(struct device *dev);
  91. extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev);
  92. #endif /* __SPI_FSL_LIB_H__ */