spi-fsl-espi.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale eSPI controller driver.
  4. *
  5. * Copyright 2010 Freescale Semiconductor, Inc.
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/err.h>
  9. #include <linux/fsl_devices.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/module.h>
  12. #include <linux/mm.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/pm_runtime.h>
  20. #include <sysdev/fsl_soc.h>
  21. /* eSPI Controller registers */
  22. #define ESPI_SPMODE 0x00 /* eSPI mode register */
  23. #define ESPI_SPIE 0x04 /* eSPI event register */
  24. #define ESPI_SPIM 0x08 /* eSPI mask register */
  25. #define ESPI_SPCOM 0x0c /* eSPI command register */
  26. #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
  27. #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
  28. #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
  29. #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
  30. /* eSPI Controller mode register definitions */
  31. #define SPMODE_ENABLE BIT(31)
  32. #define SPMODE_LOOP BIT(30)
  33. #define SPMODE_TXTHR(x) ((x) << 8)
  34. #define SPMODE_RXTHR(x) ((x) << 0)
  35. /* eSPI Controller CS mode register definitions */
  36. #define CSMODE_CI_INACTIVEHIGH BIT(31)
  37. #define CSMODE_CP_BEGIN_EDGECLK BIT(30)
  38. #define CSMODE_REV BIT(29)
  39. #define CSMODE_DIV16 BIT(28)
  40. #define CSMODE_PM(x) ((x) << 24)
  41. #define CSMODE_POL_1 BIT(20)
  42. #define CSMODE_LEN(x) ((x) << 16)
  43. #define CSMODE_BEF(x) ((x) << 12)
  44. #define CSMODE_AFT(x) ((x) << 8)
  45. #define CSMODE_CG(x) ((x) << 3)
  46. #define FSL_ESPI_FIFO_SIZE 32
  47. #define FSL_ESPI_RXTHR 15
  48. /* Default mode/csmode for eSPI controller */
  49. #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR))
  50. #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
  51. | CSMODE_AFT(0) | CSMODE_CG(1))
  52. /* SPIE register values */
  53. #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
  54. #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
  55. #define SPIE_TXE BIT(15) /* TX FIFO empty */
  56. #define SPIE_DON BIT(14) /* TX done */
  57. #define SPIE_RXT BIT(13) /* RX FIFO threshold */
  58. #define SPIE_RXF BIT(12) /* RX FIFO full */
  59. #define SPIE_TXT BIT(11) /* TX FIFO threshold*/
  60. #define SPIE_RNE BIT(9) /* RX FIFO not empty */
  61. #define SPIE_TNF BIT(8) /* TX FIFO not full */
  62. /* SPIM register values */
  63. #define SPIM_TXE BIT(15) /* TX FIFO empty */
  64. #define SPIM_DON BIT(14) /* TX done */
  65. #define SPIM_RXT BIT(13) /* RX FIFO threshold */
  66. #define SPIM_RXF BIT(12) /* RX FIFO full */
  67. #define SPIM_TXT BIT(11) /* TX FIFO threshold*/
  68. #define SPIM_RNE BIT(9) /* RX FIFO not empty */
  69. #define SPIM_TNF BIT(8) /* TX FIFO not full */
  70. /* SPCOM register values */
  71. #define SPCOM_CS(x) ((x) << 30)
  72. #define SPCOM_DO BIT(28) /* Dual output */
  73. #define SPCOM_TO BIT(27) /* TX only */
  74. #define SPCOM_RXSKIP(x) ((x) << 16)
  75. #define SPCOM_TRANLEN(x) ((x) << 0)
  76. #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
  77. #define AUTOSUSPEND_TIMEOUT 2000
  78. struct fsl_espi {
  79. struct device *dev;
  80. void __iomem *reg_base;
  81. struct list_head *m_transfers;
  82. struct spi_transfer *tx_t;
  83. unsigned int tx_pos;
  84. bool tx_done;
  85. struct spi_transfer *rx_t;
  86. unsigned int rx_pos;
  87. bool rx_done;
  88. bool swab;
  89. unsigned int rxskip;
  90. spinlock_t lock;
  91. u32 spibrg; /* SPIBRG input clock */
  92. struct completion done;
  93. };
  94. struct fsl_espi_cs {
  95. u32 hw_mode;
  96. };
  97. static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset)
  98. {
  99. return ioread32be(espi->reg_base + offset);
  100. }
  101. static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset)
  102. {
  103. return ioread16be(espi->reg_base + offset);
  104. }
  105. static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset)
  106. {
  107. return ioread8(espi->reg_base + offset);
  108. }
  109. static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset,
  110. u32 val)
  111. {
  112. iowrite32be(val, espi->reg_base + offset);
  113. }
  114. static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset,
  115. u16 val)
  116. {
  117. iowrite16be(val, espi->reg_base + offset);
  118. }
  119. static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset,
  120. u8 val)
  121. {
  122. iowrite8(val, espi->reg_base + offset);
  123. }
  124. static int fsl_espi_check_message(struct spi_message *m)
  125. {
  126. struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
  127. struct spi_transfer *t, *first;
  128. if (m->frame_length > SPCOM_TRANLEN_MAX) {
  129. dev_err(espi->dev, "message too long, size is %u bytes\n",
  130. m->frame_length);
  131. return -EMSGSIZE;
  132. }
  133. first = list_first_entry(&m->transfers, struct spi_transfer,
  134. transfer_list);
  135. list_for_each_entry(t, &m->transfers, transfer_list) {
  136. if (first->bits_per_word != t->bits_per_word ||
  137. first->speed_hz != t->speed_hz) {
  138. dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
  139. return -EINVAL;
  140. }
  141. }
  142. /* ESPI supports MSB-first transfers for word size 8 / 16 only */
  143. if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 &&
  144. first->bits_per_word != 16) {
  145. dev_err(espi->dev,
  146. "MSB-first transfer not supported for wordsize %u\n",
  147. first->bits_per_word);
  148. return -EINVAL;
  149. }
  150. return 0;
  151. }
  152. static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m)
  153. {
  154. struct spi_transfer *t;
  155. unsigned int i = 0, rxskip = 0;
  156. /*
  157. * prerequisites for ESPI rxskip mode:
  158. * - message has two transfers
  159. * - first transfer is a write and second is a read
  160. *
  161. * In addition the current low-level transfer mechanism requires
  162. * that the rxskip bytes fit into the TX FIFO. Else the transfer
  163. * would hang because after the first FSL_ESPI_FIFO_SIZE bytes
  164. * the TX FIFO isn't re-filled.
  165. */
  166. list_for_each_entry(t, &m->transfers, transfer_list) {
  167. if (i == 0) {
  168. if (!t->tx_buf || t->rx_buf ||
  169. t->len > FSL_ESPI_FIFO_SIZE)
  170. return 0;
  171. rxskip = t->len;
  172. } else if (i == 1) {
  173. if (t->tx_buf || !t->rx_buf)
  174. return 0;
  175. }
  176. i++;
  177. }
  178. return i == 2 ? rxskip : 0;
  179. }
  180. static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)
  181. {
  182. u32 tx_fifo_avail;
  183. unsigned int tx_left;
  184. const void *tx_buf;
  185. /* if events is zero transfer has not started and tx fifo is empty */
  186. tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE;
  187. start:
  188. tx_left = espi->tx_t->len - espi->tx_pos;
  189. tx_buf = espi->tx_t->tx_buf;
  190. while (tx_fifo_avail >= min(4U, tx_left) && tx_left) {
  191. if (tx_left >= 4) {
  192. if (!tx_buf)
  193. fsl_espi_write_reg(espi, ESPI_SPITF, 0);
  194. else if (espi->swab)
  195. fsl_espi_write_reg(espi, ESPI_SPITF,
  196. swahb32p(tx_buf + espi->tx_pos));
  197. else
  198. fsl_espi_write_reg(espi, ESPI_SPITF,
  199. *(u32 *)(tx_buf + espi->tx_pos));
  200. espi->tx_pos += 4;
  201. tx_left -= 4;
  202. tx_fifo_avail -= 4;
  203. } else if (tx_left >= 2 && tx_buf && espi->swab) {
  204. fsl_espi_write_reg16(espi, ESPI_SPITF,
  205. swab16p(tx_buf + espi->tx_pos));
  206. espi->tx_pos += 2;
  207. tx_left -= 2;
  208. tx_fifo_avail -= 2;
  209. } else {
  210. if (!tx_buf)
  211. fsl_espi_write_reg8(espi, ESPI_SPITF, 0);
  212. else
  213. fsl_espi_write_reg8(espi, ESPI_SPITF,
  214. *(u8 *)(tx_buf + espi->tx_pos));
  215. espi->tx_pos += 1;
  216. tx_left -= 1;
  217. tx_fifo_avail -= 1;
  218. }
  219. }
  220. if (!tx_left) {
  221. /* Last transfer finished, in rxskip mode only one is needed */
  222. if (list_is_last(&espi->tx_t->transfer_list,
  223. espi->m_transfers) || espi->rxskip) {
  224. espi->tx_done = true;
  225. return;
  226. }
  227. espi->tx_t = list_next_entry(espi->tx_t, transfer_list);
  228. espi->tx_pos = 0;
  229. /* continue with next transfer if tx fifo is not full */
  230. if (tx_fifo_avail)
  231. goto start;
  232. }
  233. }
  234. static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events)
  235. {
  236. u32 rx_fifo_avail = SPIE_RXCNT(events);
  237. unsigned int rx_left;
  238. void *rx_buf;
  239. start:
  240. rx_left = espi->rx_t->len - espi->rx_pos;
  241. rx_buf = espi->rx_t->rx_buf;
  242. while (rx_fifo_avail >= min(4U, rx_left) && rx_left) {
  243. if (rx_left >= 4) {
  244. u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF);
  245. if (rx_buf && espi->swab)
  246. *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val);
  247. else if (rx_buf)
  248. *(u32 *)(rx_buf + espi->rx_pos) = val;
  249. espi->rx_pos += 4;
  250. rx_left -= 4;
  251. rx_fifo_avail -= 4;
  252. } else if (rx_left >= 2 && rx_buf && espi->swab) {
  253. u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF);
  254. *(u16 *)(rx_buf + espi->rx_pos) = swab16(val);
  255. espi->rx_pos += 2;
  256. rx_left -= 2;
  257. rx_fifo_avail -= 2;
  258. } else {
  259. u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF);
  260. if (rx_buf)
  261. *(u8 *)(rx_buf + espi->rx_pos) = val;
  262. espi->rx_pos += 1;
  263. rx_left -= 1;
  264. rx_fifo_avail -= 1;
  265. }
  266. }
  267. if (!rx_left) {
  268. if (list_is_last(&espi->rx_t->transfer_list,
  269. espi->m_transfers)) {
  270. espi->rx_done = true;
  271. return;
  272. }
  273. espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
  274. espi->rx_pos = 0;
  275. /* continue with next transfer if rx fifo is not empty */
  276. if (rx_fifo_avail)
  277. goto start;
  278. }
  279. }
  280. static void fsl_espi_setup_transfer(struct spi_device *spi,
  281. struct spi_transfer *t)
  282. {
  283. struct fsl_espi *espi = spi_master_get_devdata(spi->master);
  284. int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
  285. u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz;
  286. struct fsl_espi_cs *cs = spi_get_ctldata(spi);
  287. u32 hw_mode_old = cs->hw_mode;
  288. /* mask out bits we are going to set */
  289. cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
  290. cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
  291. pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1;
  292. if (pm > 15) {
  293. cs->hw_mode |= CSMODE_DIV16;
  294. pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1;
  295. }
  296. cs->hw_mode |= CSMODE_PM(pm);
  297. /* don't write the mode register if the mode doesn't change */
  298. if (cs->hw_mode != hw_mode_old)
  299. fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select),
  300. cs->hw_mode);
  301. }
  302. static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
  303. {
  304. struct fsl_espi *espi = spi_master_get_devdata(spi->master);
  305. unsigned int rx_len = t->len;
  306. u32 mask, spcom;
  307. int ret;
  308. reinit_completion(&espi->done);
  309. /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
  310. spcom = SPCOM_CS(spi->chip_select);
  311. spcom |= SPCOM_TRANLEN(t->len - 1);
  312. /* configure RXSKIP mode */
  313. if (espi->rxskip) {
  314. spcom |= SPCOM_RXSKIP(espi->rxskip);
  315. rx_len = t->len - espi->rxskip;
  316. if (t->rx_nbits == SPI_NBITS_DUAL)
  317. spcom |= SPCOM_DO;
  318. }
  319. fsl_espi_write_reg(espi, ESPI_SPCOM, spcom);
  320. /* enable interrupts */
  321. mask = SPIM_DON;
  322. if (rx_len > FSL_ESPI_FIFO_SIZE)
  323. mask |= SPIM_RXT;
  324. fsl_espi_write_reg(espi, ESPI_SPIM, mask);
  325. /* Prevent filling the fifo from getting interrupted */
  326. spin_lock_irq(&espi->lock);
  327. fsl_espi_fill_tx_fifo(espi, 0);
  328. spin_unlock_irq(&espi->lock);
  329. /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
  330. ret = wait_for_completion_timeout(&espi->done, 2 * HZ);
  331. if (ret == 0)
  332. dev_err(espi->dev, "Transfer timed out!\n");
  333. /* disable rx ints */
  334. fsl_espi_write_reg(espi, ESPI_SPIM, 0);
  335. return ret == 0 ? -ETIMEDOUT : 0;
  336. }
  337. static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
  338. {
  339. struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
  340. struct spi_device *spi = m->spi;
  341. int ret;
  342. /* In case of LSB-first and bits_per_word > 8 byte-swap all words */
  343. espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8;
  344. espi->m_transfers = &m->transfers;
  345. espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer,
  346. transfer_list);
  347. espi->tx_pos = 0;
  348. espi->tx_done = false;
  349. espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer,
  350. transfer_list);
  351. espi->rx_pos = 0;
  352. espi->rx_done = false;
  353. espi->rxskip = fsl_espi_check_rxskip_mode(m);
  354. if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) {
  355. dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n");
  356. return -EINVAL;
  357. }
  358. /* In RXSKIP mode skip first transfer for reads */
  359. if (espi->rxskip)
  360. espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
  361. fsl_espi_setup_transfer(spi, trans);
  362. ret = fsl_espi_bufs(spi, trans);
  363. spi_transfer_delay_exec(trans);
  364. return ret;
  365. }
  366. static int fsl_espi_do_one_msg(struct spi_master *master,
  367. struct spi_message *m)
  368. {
  369. unsigned int delay_usecs = 0, rx_nbits = 0;
  370. unsigned int delay_nsecs = 0, delay_nsecs1 = 0;
  371. struct spi_transfer *t, trans = {};
  372. int ret;
  373. ret = fsl_espi_check_message(m);
  374. if (ret)
  375. goto out;
  376. list_for_each_entry(t, &m->transfers, transfer_list) {
  377. if (t->delay_usecs) {
  378. if (t->delay_usecs > delay_usecs) {
  379. delay_usecs = t->delay_usecs;
  380. delay_nsecs = delay_usecs * 1000;
  381. }
  382. } else {
  383. delay_nsecs1 = spi_delay_to_ns(&t->delay, t);
  384. if (delay_nsecs1 > delay_nsecs)
  385. delay_nsecs = delay_nsecs1;
  386. }
  387. if (t->rx_nbits > rx_nbits)
  388. rx_nbits = t->rx_nbits;
  389. }
  390. t = list_first_entry(&m->transfers, struct spi_transfer,
  391. transfer_list);
  392. trans.len = m->frame_length;
  393. trans.speed_hz = t->speed_hz;
  394. trans.bits_per_word = t->bits_per_word;
  395. trans.delay.value = delay_nsecs;
  396. trans.delay.unit = SPI_DELAY_UNIT_NSECS;
  397. trans.rx_nbits = rx_nbits;
  398. if (trans.len)
  399. ret = fsl_espi_trans(m, &trans);
  400. m->actual_length = ret ? 0 : trans.len;
  401. out:
  402. if (m->status == -EINPROGRESS)
  403. m->status = ret;
  404. spi_finalize_current_message(master);
  405. return ret;
  406. }
  407. static int fsl_espi_setup(struct spi_device *spi)
  408. {
  409. struct fsl_espi *espi;
  410. u32 loop_mode;
  411. struct fsl_espi_cs *cs = spi_get_ctldata(spi);
  412. if (!cs) {
  413. cs = kzalloc(sizeof(*cs), GFP_KERNEL);
  414. if (!cs)
  415. return -ENOMEM;
  416. spi_set_ctldata(spi, cs);
  417. }
  418. espi = spi_master_get_devdata(spi->master);
  419. pm_runtime_get_sync(espi->dev);
  420. cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select));
  421. /* mask out bits we are going to set */
  422. cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
  423. | CSMODE_REV);
  424. if (spi->mode & SPI_CPHA)
  425. cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
  426. if (spi->mode & SPI_CPOL)
  427. cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
  428. if (!(spi->mode & SPI_LSB_FIRST))
  429. cs->hw_mode |= CSMODE_REV;
  430. /* Handle the loop mode */
  431. loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE);
  432. loop_mode &= ~SPMODE_LOOP;
  433. if (spi->mode & SPI_LOOP)
  434. loop_mode |= SPMODE_LOOP;
  435. fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode);
  436. fsl_espi_setup_transfer(spi, NULL);
  437. pm_runtime_mark_last_busy(espi->dev);
  438. pm_runtime_put_autosuspend(espi->dev);
  439. return 0;
  440. }
  441. static void fsl_espi_cleanup(struct spi_device *spi)
  442. {
  443. struct fsl_espi_cs *cs = spi_get_ctldata(spi);
  444. kfree(cs);
  445. spi_set_ctldata(spi, NULL);
  446. }
  447. static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events)
  448. {
  449. if (!espi->rx_done)
  450. fsl_espi_read_rx_fifo(espi, events);
  451. if (!espi->tx_done)
  452. fsl_espi_fill_tx_fifo(espi, events);
  453. if (!espi->tx_done || !espi->rx_done)
  454. return;
  455. /* we're done, but check for errors before returning */
  456. events = fsl_espi_read_reg(espi, ESPI_SPIE);
  457. if (!(events & SPIE_DON))
  458. dev_err(espi->dev,
  459. "Transfer done but SPIE_DON isn't set!\n");
  460. if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) {
  461. dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n");
  462. dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n",
  463. SPIE_RXCNT(events), SPIE_TXCNT(events));
  464. }
  465. complete(&espi->done);
  466. }
  467. static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
  468. {
  469. struct fsl_espi *espi = context_data;
  470. u32 events, mask;
  471. spin_lock(&espi->lock);
  472. /* Get interrupt events(tx/rx) */
  473. events = fsl_espi_read_reg(espi, ESPI_SPIE);
  474. mask = fsl_espi_read_reg(espi, ESPI_SPIM);
  475. if (!(events & mask)) {
  476. spin_unlock(&espi->lock);
  477. return IRQ_NONE;
  478. }
  479. dev_vdbg(espi->dev, "%s: events %x\n", __func__, events);
  480. fsl_espi_cpu_irq(espi, events);
  481. /* Clear the events */
  482. fsl_espi_write_reg(espi, ESPI_SPIE, events);
  483. spin_unlock(&espi->lock);
  484. return IRQ_HANDLED;
  485. }
  486. #ifdef CONFIG_PM
  487. static int fsl_espi_runtime_suspend(struct device *dev)
  488. {
  489. struct spi_master *master = dev_get_drvdata(dev);
  490. struct fsl_espi *espi = spi_master_get_devdata(master);
  491. u32 regval;
  492. regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
  493. regval &= ~SPMODE_ENABLE;
  494. fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
  495. return 0;
  496. }
  497. static int fsl_espi_runtime_resume(struct device *dev)
  498. {
  499. struct spi_master *master = dev_get_drvdata(dev);
  500. struct fsl_espi *espi = spi_master_get_devdata(master);
  501. u32 regval;
  502. regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
  503. regval |= SPMODE_ENABLE;
  504. fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
  505. return 0;
  506. }
  507. #endif
  508. static size_t fsl_espi_max_message_size(struct spi_device *spi)
  509. {
  510. return SPCOM_TRANLEN_MAX;
  511. }
  512. static void fsl_espi_init_regs(struct device *dev, bool initial)
  513. {
  514. struct spi_master *master = dev_get_drvdata(dev);
  515. struct fsl_espi *espi = spi_master_get_devdata(master);
  516. struct device_node *nc;
  517. u32 csmode, cs, prop;
  518. int ret;
  519. /* SPI controller initializations */
  520. fsl_espi_write_reg(espi, ESPI_SPMODE, 0);
  521. fsl_espi_write_reg(espi, ESPI_SPIM, 0);
  522. fsl_espi_write_reg(espi, ESPI_SPCOM, 0);
  523. fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff);
  524. /* Init eSPI CS mode register */
  525. for_each_available_child_of_node(master->dev.of_node, nc) {
  526. /* get chip select */
  527. ret = of_property_read_u32(nc, "reg", &cs);
  528. if (ret || cs >= master->num_chipselect)
  529. continue;
  530. csmode = CSMODE_INIT_VAL;
  531. /* check if CSBEF is set in device tree */
  532. ret = of_property_read_u32(nc, "fsl,csbef", &prop);
  533. if (!ret) {
  534. csmode &= ~(CSMODE_BEF(0xf));
  535. csmode |= CSMODE_BEF(prop);
  536. }
  537. /* check if CSAFT is set in device tree */
  538. ret = of_property_read_u32(nc, "fsl,csaft", &prop);
  539. if (!ret) {
  540. csmode &= ~(CSMODE_AFT(0xf));
  541. csmode |= CSMODE_AFT(prop);
  542. }
  543. fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode);
  544. if (initial)
  545. dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode);
  546. }
  547. /* Enable SPI interface */
  548. fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE);
  549. }
  550. static int fsl_espi_probe(struct device *dev, struct resource *mem,
  551. unsigned int irq, unsigned int num_cs)
  552. {
  553. struct spi_master *master;
  554. struct fsl_espi *espi;
  555. int ret;
  556. master = spi_alloc_master(dev, sizeof(struct fsl_espi));
  557. if (!master)
  558. return -ENOMEM;
  559. dev_set_drvdata(dev, master);
  560. master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
  561. SPI_LSB_FIRST | SPI_LOOP;
  562. master->dev.of_node = dev->of_node;
  563. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
  564. master->setup = fsl_espi_setup;
  565. master->cleanup = fsl_espi_cleanup;
  566. master->transfer_one_message = fsl_espi_do_one_msg;
  567. master->auto_runtime_pm = true;
  568. master->max_message_size = fsl_espi_max_message_size;
  569. master->num_chipselect = num_cs;
  570. espi = spi_master_get_devdata(master);
  571. spin_lock_init(&espi->lock);
  572. espi->dev = dev;
  573. espi->spibrg = fsl_get_sys_freq();
  574. if (espi->spibrg == -1) {
  575. dev_err(dev, "Can't get sys frequency!\n");
  576. ret = -EINVAL;
  577. goto err_probe;
  578. }
  579. /* determined by clock divider fields DIV16/PM in register SPMODEx */
  580. master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16);
  581. master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4);
  582. init_completion(&espi->done);
  583. espi->reg_base = devm_ioremap_resource(dev, mem);
  584. if (IS_ERR(espi->reg_base)) {
  585. ret = PTR_ERR(espi->reg_base);
  586. goto err_probe;
  587. }
  588. /* Register for SPI Interrupt */
  589. ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi);
  590. if (ret)
  591. goto err_probe;
  592. fsl_espi_init_regs(dev, true);
  593. pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
  594. pm_runtime_use_autosuspend(dev);
  595. pm_runtime_set_active(dev);
  596. pm_runtime_enable(dev);
  597. pm_runtime_get_sync(dev);
  598. ret = devm_spi_register_master(dev, master);
  599. if (ret < 0)
  600. goto err_pm;
  601. dev_info(dev, "irq = %u\n", irq);
  602. pm_runtime_mark_last_busy(dev);
  603. pm_runtime_put_autosuspend(dev);
  604. return 0;
  605. err_pm:
  606. pm_runtime_put_noidle(dev);
  607. pm_runtime_disable(dev);
  608. pm_runtime_set_suspended(dev);
  609. err_probe:
  610. spi_master_put(master);
  611. return ret;
  612. }
  613. static int of_fsl_espi_get_chipselects(struct device *dev)
  614. {
  615. struct device_node *np = dev->of_node;
  616. u32 num_cs;
  617. int ret;
  618. ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs);
  619. if (ret) {
  620. dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
  621. return 0;
  622. }
  623. return num_cs;
  624. }
  625. static int of_fsl_espi_probe(struct platform_device *ofdev)
  626. {
  627. struct device *dev = &ofdev->dev;
  628. struct device_node *np = ofdev->dev.of_node;
  629. struct resource mem;
  630. unsigned int irq, num_cs;
  631. int ret;
  632. if (of_property_read_bool(np, "mode")) {
  633. dev_err(dev, "mode property is not supported on ESPI!\n");
  634. return -EINVAL;
  635. }
  636. num_cs = of_fsl_espi_get_chipselects(dev);
  637. if (!num_cs)
  638. return -EINVAL;
  639. ret = of_address_to_resource(np, 0, &mem);
  640. if (ret)
  641. return ret;
  642. irq = irq_of_parse_and_map(np, 0);
  643. if (!irq)
  644. return -EINVAL;
  645. return fsl_espi_probe(dev, &mem, irq, num_cs);
  646. }
  647. static int of_fsl_espi_remove(struct platform_device *dev)
  648. {
  649. pm_runtime_disable(&dev->dev);
  650. return 0;
  651. }
  652. #ifdef CONFIG_PM_SLEEP
  653. static int of_fsl_espi_suspend(struct device *dev)
  654. {
  655. struct spi_master *master = dev_get_drvdata(dev);
  656. int ret;
  657. ret = spi_master_suspend(master);
  658. if (ret)
  659. return ret;
  660. return pm_runtime_force_suspend(dev);
  661. }
  662. static int of_fsl_espi_resume(struct device *dev)
  663. {
  664. struct spi_master *master = dev_get_drvdata(dev);
  665. int ret;
  666. fsl_espi_init_regs(dev, false);
  667. ret = pm_runtime_force_resume(dev);
  668. if (ret < 0)
  669. return ret;
  670. return spi_master_resume(master);
  671. }
  672. #endif /* CONFIG_PM_SLEEP */
  673. static const struct dev_pm_ops espi_pm = {
  674. SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
  675. fsl_espi_runtime_resume, NULL)
  676. SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
  677. };
  678. static const struct of_device_id of_fsl_espi_match[] = {
  679. { .compatible = "fsl,mpc8536-espi" },
  680. {}
  681. };
  682. MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
  683. static struct platform_driver fsl_espi_driver = {
  684. .driver = {
  685. .name = "fsl_espi",
  686. .of_match_table = of_fsl_espi_match,
  687. .pm = &espi_pm,
  688. },
  689. .probe = of_fsl_espi_probe,
  690. .remove = of_fsl_espi_remove,
  691. };
  692. module_platform_driver(fsl_espi_driver);
  693. MODULE_AUTHOR("Mingkai Hu");
  694. MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
  695. MODULE_LICENSE("GPL");