spi-fsl-dspi.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright 2013 Freescale Semiconductor, Inc.
  4. // Copyright 2020 NXP
  5. //
  6. // Freescale DSPI driver
  7. // This file contains a driver for the Freescale DSPI
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of_device.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/regmap.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/spi/spi-fsl-dspi.h>
  20. #define DRIVER_NAME "fsl-dspi"
  21. #define SPI_MCR 0x00
  22. #define SPI_MCR_MASTER BIT(31)
  23. #define SPI_MCR_PCSIS(x) ((x) << 16)
  24. #define SPI_MCR_CLR_TXF BIT(11)
  25. #define SPI_MCR_CLR_RXF BIT(10)
  26. #define SPI_MCR_XSPI BIT(3)
  27. #define SPI_MCR_DIS_TXF BIT(13)
  28. #define SPI_MCR_DIS_RXF BIT(12)
  29. #define SPI_MCR_HALT BIT(0)
  30. #define SPI_TCR 0x08
  31. #define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
  32. #define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
  33. #define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
  34. #define SPI_CTAR_CPOL BIT(26)
  35. #define SPI_CTAR_CPHA BIT(25)
  36. #define SPI_CTAR_LSBFE BIT(24)
  37. #define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))
  38. #define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))
  39. #define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))
  40. #define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))
  41. #define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))
  42. #define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))
  43. #define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))
  44. #define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))
  45. #define SPI_CTAR_SCALE_BITS 0xf
  46. #define SPI_CTAR0_SLAVE 0x0c
  47. #define SPI_SR 0x2c
  48. #define SPI_SR_TCFQF BIT(31)
  49. #define SPI_SR_TFUF BIT(27)
  50. #define SPI_SR_TFFF BIT(25)
  51. #define SPI_SR_CMDTCF BIT(23)
  52. #define SPI_SR_SPEF BIT(21)
  53. #define SPI_SR_RFOF BIT(19)
  54. #define SPI_SR_TFIWF BIT(18)
  55. #define SPI_SR_RFDF BIT(17)
  56. #define SPI_SR_CMDFFF BIT(16)
  57. #define SPI_SR_CLEAR (SPI_SR_TCFQF | \
  58. SPI_SR_TFUF | SPI_SR_TFFF | \
  59. SPI_SR_CMDTCF | SPI_SR_SPEF | \
  60. SPI_SR_RFOF | SPI_SR_TFIWF | \
  61. SPI_SR_RFDF | SPI_SR_CMDFFF)
  62. #define SPI_RSER_TFFFE BIT(25)
  63. #define SPI_RSER_TFFFD BIT(24)
  64. #define SPI_RSER_RFDFE BIT(17)
  65. #define SPI_RSER_RFDFD BIT(16)
  66. #define SPI_RSER 0x30
  67. #define SPI_RSER_TCFQE BIT(31)
  68. #define SPI_RSER_CMDTCFE BIT(23)
  69. #define SPI_PUSHR 0x34
  70. #define SPI_PUSHR_CMD_CONT BIT(15)
  71. #define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))
  72. #define SPI_PUSHR_CMD_EOQ BIT(11)
  73. #define SPI_PUSHR_CMD_CTCNT BIT(10)
  74. #define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))
  75. #define SPI_PUSHR_SLAVE 0x34
  76. #define SPI_POPR 0x38
  77. #define SPI_TXFR0 0x3c
  78. #define SPI_TXFR1 0x40
  79. #define SPI_TXFR2 0x44
  80. #define SPI_TXFR3 0x48
  81. #define SPI_RXFR0 0x7c
  82. #define SPI_RXFR1 0x80
  83. #define SPI_RXFR2 0x84
  84. #define SPI_RXFR3 0x88
  85. #define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
  86. #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
  87. #define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
  88. #define SPI_SREX 0x13c
  89. #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
  90. #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
  91. #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
  92. struct chip_data {
  93. u32 ctar_val;
  94. };
  95. enum dspi_trans_mode {
  96. DSPI_XSPI_MODE,
  97. DSPI_DMA_MODE,
  98. };
  99. struct fsl_dspi_devtype_data {
  100. enum dspi_trans_mode trans_mode;
  101. u8 max_clock_factor;
  102. int fifo_size;
  103. };
  104. enum {
  105. LS1021A,
  106. LS1012A,
  107. LS1028A,
  108. LS1043A,
  109. LS1046A,
  110. LS2080A,
  111. LS2085A,
  112. LX2160A,
  113. MCF5441X,
  114. VF610,
  115. };
  116. static const struct fsl_dspi_devtype_data devtype_data[] = {
  117. [VF610] = {
  118. .trans_mode = DSPI_DMA_MODE,
  119. .max_clock_factor = 2,
  120. .fifo_size = 4,
  121. },
  122. [LS1021A] = {
  123. /* Has A-011218 DMA erratum */
  124. .trans_mode = DSPI_XSPI_MODE,
  125. .max_clock_factor = 8,
  126. .fifo_size = 4,
  127. },
  128. [LS1012A] = {
  129. /* Has A-011218 DMA erratum */
  130. .trans_mode = DSPI_XSPI_MODE,
  131. .max_clock_factor = 8,
  132. .fifo_size = 16,
  133. },
  134. [LS1028A] = {
  135. .trans_mode = DSPI_XSPI_MODE,
  136. .max_clock_factor = 8,
  137. .fifo_size = 4,
  138. },
  139. [LS1043A] = {
  140. /* Has A-011218 DMA erratum */
  141. .trans_mode = DSPI_XSPI_MODE,
  142. .max_clock_factor = 8,
  143. .fifo_size = 16,
  144. },
  145. [LS1046A] = {
  146. /* Has A-011218 DMA erratum */
  147. .trans_mode = DSPI_XSPI_MODE,
  148. .max_clock_factor = 8,
  149. .fifo_size = 16,
  150. },
  151. [LS2080A] = {
  152. .trans_mode = DSPI_XSPI_MODE,
  153. .max_clock_factor = 8,
  154. .fifo_size = 4,
  155. },
  156. [LS2085A] = {
  157. .trans_mode = DSPI_XSPI_MODE,
  158. .max_clock_factor = 8,
  159. .fifo_size = 4,
  160. },
  161. [LX2160A] = {
  162. .trans_mode = DSPI_XSPI_MODE,
  163. .max_clock_factor = 8,
  164. .fifo_size = 4,
  165. },
  166. [MCF5441X] = {
  167. .trans_mode = DSPI_DMA_MODE,
  168. .max_clock_factor = 8,
  169. .fifo_size = 16,
  170. },
  171. };
  172. struct fsl_dspi_dma {
  173. u32 *tx_dma_buf;
  174. struct dma_chan *chan_tx;
  175. dma_addr_t tx_dma_phys;
  176. struct completion cmd_tx_complete;
  177. struct dma_async_tx_descriptor *tx_desc;
  178. u32 *rx_dma_buf;
  179. struct dma_chan *chan_rx;
  180. dma_addr_t rx_dma_phys;
  181. struct completion cmd_rx_complete;
  182. struct dma_async_tx_descriptor *rx_desc;
  183. };
  184. struct fsl_dspi {
  185. struct spi_controller *ctlr;
  186. struct platform_device *pdev;
  187. struct regmap *regmap;
  188. struct regmap *regmap_pushr;
  189. int irq;
  190. struct clk *clk;
  191. struct spi_transfer *cur_transfer;
  192. struct spi_message *cur_msg;
  193. struct chip_data *cur_chip;
  194. size_t progress;
  195. size_t len;
  196. const void *tx;
  197. void *rx;
  198. u16 tx_cmd;
  199. const struct fsl_dspi_devtype_data *devtype_data;
  200. struct completion xfer_done;
  201. struct fsl_dspi_dma *dma;
  202. int oper_word_size;
  203. int oper_bits_per_word;
  204. int words_in_flight;
  205. /*
  206. * Offsets for CMD and TXDATA within SPI_PUSHR when accessed
  207. * individually (in XSPI mode)
  208. */
  209. int pushr_cmd;
  210. int pushr_tx;
  211. void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
  212. void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
  213. };
  214. static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
  215. {
  216. switch (dspi->oper_word_size) {
  217. case 1:
  218. *txdata = *(u8 *)dspi->tx;
  219. break;
  220. case 2:
  221. *txdata = *(u16 *)dspi->tx;
  222. break;
  223. case 4:
  224. *txdata = *(u32 *)dspi->tx;
  225. break;
  226. }
  227. dspi->tx += dspi->oper_word_size;
  228. }
  229. static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
  230. {
  231. switch (dspi->oper_word_size) {
  232. case 1:
  233. *(u8 *)dspi->rx = rxdata;
  234. break;
  235. case 2:
  236. *(u16 *)dspi->rx = rxdata;
  237. break;
  238. case 4:
  239. *(u32 *)dspi->rx = rxdata;
  240. break;
  241. }
  242. dspi->rx += dspi->oper_word_size;
  243. }
  244. static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
  245. {
  246. *txdata = cpu_to_be32(*(u32 *)dspi->tx);
  247. dspi->tx += sizeof(u32);
  248. }
  249. static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
  250. {
  251. *(u32 *)dspi->rx = be32_to_cpu(rxdata);
  252. dspi->rx += sizeof(u32);
  253. }
  254. static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
  255. {
  256. *txdata = cpu_to_be16(*(u16 *)dspi->tx);
  257. dspi->tx += sizeof(u16);
  258. }
  259. static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
  260. {
  261. *(u16 *)dspi->rx = be16_to_cpu(rxdata);
  262. dspi->rx += sizeof(u16);
  263. }
  264. static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
  265. {
  266. u16 hi = *(u16 *)dspi->tx;
  267. u16 lo = *(u16 *)(dspi->tx + 2);
  268. *txdata = (u32)hi << 16 | lo;
  269. dspi->tx += sizeof(u32);
  270. }
  271. static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
  272. {
  273. u16 hi = rxdata & 0xffff;
  274. u16 lo = rxdata >> 16;
  275. *(u16 *)dspi->rx = lo;
  276. *(u16 *)(dspi->rx + 2) = hi;
  277. dspi->rx += sizeof(u32);
  278. }
  279. /*
  280. * Pop one word from the TX buffer for pushing into the
  281. * PUSHR register (TX FIFO)
  282. */
  283. static u32 dspi_pop_tx(struct fsl_dspi *dspi)
  284. {
  285. u32 txdata = 0;
  286. if (dspi->tx)
  287. dspi->host_to_dev(dspi, &txdata);
  288. dspi->len -= dspi->oper_word_size;
  289. return txdata;
  290. }
  291. /* Prepare one TX FIFO entry (txdata plus cmd) */
  292. static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
  293. {
  294. u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
  295. if (spi_controller_is_slave(dspi->ctlr))
  296. return data;
  297. if (dspi->len > 0)
  298. cmd |= SPI_PUSHR_CMD_CONT;
  299. return cmd << 16 | data;
  300. }
  301. /* Push one word to the RX buffer from the POPR register (RX FIFO) */
  302. static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
  303. {
  304. if (!dspi->rx)
  305. return;
  306. dspi->dev_to_host(dspi, rxdata);
  307. }
  308. static void dspi_tx_dma_callback(void *arg)
  309. {
  310. struct fsl_dspi *dspi = arg;
  311. struct fsl_dspi_dma *dma = dspi->dma;
  312. complete(&dma->cmd_tx_complete);
  313. }
  314. static void dspi_rx_dma_callback(void *arg)
  315. {
  316. struct fsl_dspi *dspi = arg;
  317. struct fsl_dspi_dma *dma = dspi->dma;
  318. int i;
  319. if (dspi->rx) {
  320. for (i = 0; i < dspi->words_in_flight; i++)
  321. dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
  322. }
  323. complete(&dma->cmd_rx_complete);
  324. }
  325. static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
  326. {
  327. struct device *dev = &dspi->pdev->dev;
  328. struct fsl_dspi_dma *dma = dspi->dma;
  329. int time_left;
  330. int i;
  331. for (i = 0; i < dspi->words_in_flight; i++)
  332. dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
  333. dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
  334. dma->tx_dma_phys,
  335. dspi->words_in_flight *
  336. DMA_SLAVE_BUSWIDTH_4_BYTES,
  337. DMA_MEM_TO_DEV,
  338. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  339. if (!dma->tx_desc) {
  340. dev_err(dev, "Not able to get desc for DMA xfer\n");
  341. return -EIO;
  342. }
  343. dma->tx_desc->callback = dspi_tx_dma_callback;
  344. dma->tx_desc->callback_param = dspi;
  345. if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
  346. dev_err(dev, "DMA submit failed\n");
  347. return -EINVAL;
  348. }
  349. dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
  350. dma->rx_dma_phys,
  351. dspi->words_in_flight *
  352. DMA_SLAVE_BUSWIDTH_4_BYTES,
  353. DMA_DEV_TO_MEM,
  354. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  355. if (!dma->rx_desc) {
  356. dev_err(dev, "Not able to get desc for DMA xfer\n");
  357. return -EIO;
  358. }
  359. dma->rx_desc->callback = dspi_rx_dma_callback;
  360. dma->rx_desc->callback_param = dspi;
  361. if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
  362. dev_err(dev, "DMA submit failed\n");
  363. return -EINVAL;
  364. }
  365. reinit_completion(&dspi->dma->cmd_rx_complete);
  366. reinit_completion(&dspi->dma->cmd_tx_complete);
  367. dma_async_issue_pending(dma->chan_rx);
  368. dma_async_issue_pending(dma->chan_tx);
  369. if (spi_controller_is_slave(dspi->ctlr)) {
  370. wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
  371. return 0;
  372. }
  373. time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
  374. DMA_COMPLETION_TIMEOUT);
  375. if (time_left == 0) {
  376. dev_err(dev, "DMA tx timeout\n");
  377. dmaengine_terminate_all(dma->chan_tx);
  378. dmaengine_terminate_all(dma->chan_rx);
  379. return -ETIMEDOUT;
  380. }
  381. time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
  382. DMA_COMPLETION_TIMEOUT);
  383. if (time_left == 0) {
  384. dev_err(dev, "DMA rx timeout\n");
  385. dmaengine_terminate_all(dma->chan_tx);
  386. dmaengine_terminate_all(dma->chan_rx);
  387. return -ETIMEDOUT;
  388. }
  389. return 0;
  390. }
  391. static void dspi_setup_accel(struct fsl_dspi *dspi);
  392. static int dspi_dma_xfer(struct fsl_dspi *dspi)
  393. {
  394. struct spi_message *message = dspi->cur_msg;
  395. struct device *dev = &dspi->pdev->dev;
  396. int ret = 0;
  397. /*
  398. * dspi->len gets decremented by dspi_pop_tx_pushr in
  399. * dspi_next_xfer_dma_submit
  400. */
  401. while (dspi->len) {
  402. /* Figure out operational bits-per-word for this chunk */
  403. dspi_setup_accel(dspi);
  404. dspi->words_in_flight = dspi->len / dspi->oper_word_size;
  405. if (dspi->words_in_flight > dspi->devtype_data->fifo_size)
  406. dspi->words_in_flight = dspi->devtype_data->fifo_size;
  407. message->actual_length += dspi->words_in_flight *
  408. dspi->oper_word_size;
  409. ret = dspi_next_xfer_dma_submit(dspi);
  410. if (ret) {
  411. dev_err(dev, "DMA transfer failed\n");
  412. break;
  413. }
  414. }
  415. return ret;
  416. }
  417. static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
  418. {
  419. int dma_bufsize = dspi->devtype_data->fifo_size * 2;
  420. struct device *dev = &dspi->pdev->dev;
  421. struct dma_slave_config cfg;
  422. struct fsl_dspi_dma *dma;
  423. int ret;
  424. dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
  425. if (!dma)
  426. return -ENOMEM;
  427. dma->chan_rx = dma_request_chan(dev, "rx");
  428. if (IS_ERR(dma->chan_rx)) {
  429. dev_err(dev, "rx dma channel not available\n");
  430. ret = PTR_ERR(dma->chan_rx);
  431. return ret;
  432. }
  433. dma->chan_tx = dma_request_chan(dev, "tx");
  434. if (IS_ERR(dma->chan_tx)) {
  435. dev_err(dev, "tx dma channel not available\n");
  436. ret = PTR_ERR(dma->chan_tx);
  437. goto err_tx_channel;
  438. }
  439. dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev,
  440. dma_bufsize, &dma->tx_dma_phys,
  441. GFP_KERNEL);
  442. if (!dma->tx_dma_buf) {
  443. ret = -ENOMEM;
  444. goto err_tx_dma_buf;
  445. }
  446. dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev,
  447. dma_bufsize, &dma->rx_dma_phys,
  448. GFP_KERNEL);
  449. if (!dma->rx_dma_buf) {
  450. ret = -ENOMEM;
  451. goto err_rx_dma_buf;
  452. }
  453. memset(&cfg, 0, sizeof(cfg));
  454. cfg.src_addr = phy_addr + SPI_POPR;
  455. cfg.dst_addr = phy_addr + SPI_PUSHR;
  456. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  457. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  458. cfg.src_maxburst = 1;
  459. cfg.dst_maxburst = 1;
  460. cfg.direction = DMA_DEV_TO_MEM;
  461. ret = dmaengine_slave_config(dma->chan_rx, &cfg);
  462. if (ret) {
  463. dev_err(dev, "can't configure rx dma channel\n");
  464. ret = -EINVAL;
  465. goto err_slave_config;
  466. }
  467. cfg.direction = DMA_MEM_TO_DEV;
  468. ret = dmaengine_slave_config(dma->chan_tx, &cfg);
  469. if (ret) {
  470. dev_err(dev, "can't configure tx dma channel\n");
  471. ret = -EINVAL;
  472. goto err_slave_config;
  473. }
  474. dspi->dma = dma;
  475. init_completion(&dma->cmd_tx_complete);
  476. init_completion(&dma->cmd_rx_complete);
  477. return 0;
  478. err_slave_config:
  479. dma_free_coherent(dma->chan_rx->device->dev,
  480. dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys);
  481. err_rx_dma_buf:
  482. dma_free_coherent(dma->chan_tx->device->dev,
  483. dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys);
  484. err_tx_dma_buf:
  485. dma_release_channel(dma->chan_tx);
  486. err_tx_channel:
  487. dma_release_channel(dma->chan_rx);
  488. devm_kfree(dev, dma);
  489. dspi->dma = NULL;
  490. return ret;
  491. }
  492. static void dspi_release_dma(struct fsl_dspi *dspi)
  493. {
  494. int dma_bufsize = dspi->devtype_data->fifo_size * 2;
  495. struct fsl_dspi_dma *dma = dspi->dma;
  496. if (!dma)
  497. return;
  498. if (dma->chan_tx) {
  499. dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
  500. dma->tx_dma_buf, dma->tx_dma_phys);
  501. dma_release_channel(dma->chan_tx);
  502. }
  503. if (dma->chan_rx) {
  504. dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
  505. dma->rx_dma_buf, dma->rx_dma_phys);
  506. dma_release_channel(dma->chan_rx);
  507. }
  508. }
  509. static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
  510. unsigned long clkrate)
  511. {
  512. /* Valid baud rate pre-scaler values */
  513. int pbr_tbl[4] = {2, 3, 5, 7};
  514. int brs[16] = { 2, 4, 6, 8,
  515. 16, 32, 64, 128,
  516. 256, 512, 1024, 2048,
  517. 4096, 8192, 16384, 32768 };
  518. int scale_needed, scale, minscale = INT_MAX;
  519. int i, j;
  520. scale_needed = clkrate / speed_hz;
  521. if (clkrate % speed_hz)
  522. scale_needed++;
  523. for (i = 0; i < ARRAY_SIZE(brs); i++)
  524. for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
  525. scale = brs[i] * pbr_tbl[j];
  526. if (scale >= scale_needed) {
  527. if (scale < minscale) {
  528. minscale = scale;
  529. *br = i;
  530. *pbr = j;
  531. }
  532. break;
  533. }
  534. }
  535. if (minscale == INT_MAX) {
  536. pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
  537. speed_hz, clkrate);
  538. *pbr = ARRAY_SIZE(pbr_tbl) - 1;
  539. *br = ARRAY_SIZE(brs) - 1;
  540. }
  541. }
  542. static void ns_delay_scale(char *psc, char *sc, int delay_ns,
  543. unsigned long clkrate)
  544. {
  545. int scale_needed, scale, minscale = INT_MAX;
  546. int pscale_tbl[4] = {1, 3, 5, 7};
  547. u32 remainder;
  548. int i, j;
  549. scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
  550. &remainder);
  551. if (remainder)
  552. scale_needed++;
  553. for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
  554. for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
  555. scale = pscale_tbl[i] * (2 << j);
  556. if (scale >= scale_needed) {
  557. if (scale < minscale) {
  558. minscale = scale;
  559. *psc = i;
  560. *sc = j;
  561. }
  562. break;
  563. }
  564. }
  565. if (minscale == INT_MAX) {
  566. pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
  567. delay_ns, clkrate);
  568. *psc = ARRAY_SIZE(pscale_tbl) - 1;
  569. *sc = SPI_CTAR_SCALE_BITS;
  570. }
  571. }
  572. static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)
  573. {
  574. /*
  575. * The only time when the PCS doesn't need continuation after this word
  576. * is when it's last. We need to look ahead, because we actually call
  577. * dspi_pop_tx (the function that decrements dspi->len) _after_
  578. * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One
  579. * word is enough. If there's more to transmit than that,
  580. * dspi_xspi_write will know to split the FIFO writes in 2, and
  581. * generate a new PUSHR command with the final word that will have PCS
  582. * deasserted (not continued) here.
  583. */
  584. if (dspi->len > dspi->oper_word_size)
  585. cmd |= SPI_PUSHR_CMD_CONT;
  586. regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd);
  587. }
  588. static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata)
  589. {
  590. regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata);
  591. }
  592. static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)
  593. {
  594. int num_bytes = num_words * dspi->oper_word_size;
  595. u16 tx_cmd = dspi->tx_cmd;
  596. /*
  597. * If the PCS needs to de-assert (i.e. we're at the end of the buffer
  598. * and cs_change does not want the PCS to stay on), then we need a new
  599. * PUSHR command, since this one (for the body of the buffer)
  600. * necessarily has the CONT bit set.
  601. * So send one word less during this go, to force a split and a command
  602. * with a single word next time, when CONT will be unset.
  603. */
  604. if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len)
  605. tx_cmd |= SPI_PUSHR_CMD_EOQ;
  606. /* Update CTARE */
  607. regmap_write(dspi->regmap, SPI_CTARE(0),
  608. SPI_FRAME_EBITS(dspi->oper_bits_per_word) |
  609. SPI_CTARE_DTCP(num_words));
  610. /*
  611. * Write the CMD FIFO entry first, and then the two
  612. * corresponding TX FIFO entries (or one...).
  613. */
  614. dspi_pushr_cmd_write(dspi, tx_cmd);
  615. /* Fill TX FIFO with as many transfers as possible */
  616. while (num_words--) {
  617. u32 data = dspi_pop_tx(dspi);
  618. dspi_pushr_txdata_write(dspi, data & 0xFFFF);
  619. if (dspi->oper_bits_per_word > 16)
  620. dspi_pushr_txdata_write(dspi, data >> 16);
  621. }
  622. }
  623. static u32 dspi_popr_read(struct fsl_dspi *dspi)
  624. {
  625. u32 rxdata = 0;
  626. regmap_read(dspi->regmap, SPI_POPR, &rxdata);
  627. return rxdata;
  628. }
  629. static void dspi_fifo_read(struct fsl_dspi *dspi)
  630. {
  631. int num_fifo_entries = dspi->words_in_flight;
  632. /* Read one FIFO entry and push to rx buffer */
  633. while (num_fifo_entries--)
  634. dspi_push_rx(dspi, dspi_popr_read(dspi));
  635. }
  636. static void dspi_setup_accel(struct fsl_dspi *dspi)
  637. {
  638. struct spi_transfer *xfer = dspi->cur_transfer;
  639. bool odd = !!(dspi->len & 1);
  640. /* No accel for frames not multiple of 8 bits at the moment */
  641. if (xfer->bits_per_word % 8)
  642. goto no_accel;
  643. if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
  644. dspi->oper_bits_per_word = 16;
  645. } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) {
  646. dspi->oper_bits_per_word = 8;
  647. } else {
  648. /* Start off with maximum supported by hardware */
  649. if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
  650. dspi->oper_bits_per_word = 32;
  651. else
  652. dspi->oper_bits_per_word = 16;
  653. /*
  654. * And go down only if the buffer can't be sent with
  655. * words this big
  656. */
  657. do {
  658. if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8))
  659. break;
  660. dspi->oper_bits_per_word /= 2;
  661. } while (dspi->oper_bits_per_word > 8);
  662. }
  663. if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) {
  664. dspi->dev_to_host = dspi_8on32_dev_to_host;
  665. dspi->host_to_dev = dspi_8on32_host_to_dev;
  666. } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) {
  667. dspi->dev_to_host = dspi_8on16_dev_to_host;
  668. dspi->host_to_dev = dspi_8on16_host_to_dev;
  669. } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) {
  670. dspi->dev_to_host = dspi_16on32_dev_to_host;
  671. dspi->host_to_dev = dspi_16on32_host_to_dev;
  672. } else {
  673. no_accel:
  674. dspi->dev_to_host = dspi_native_dev_to_host;
  675. dspi->host_to_dev = dspi_native_host_to_dev;
  676. dspi->oper_bits_per_word = xfer->bits_per_word;
  677. }
  678. dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8);
  679. /*
  680. * Update CTAR here (code is common for XSPI and DMA modes).
  681. * We will update CTARE in the portion specific to XSPI, when we
  682. * also know the preload value (DTCP).
  683. */
  684. regmap_write(dspi->regmap, SPI_CTAR(0),
  685. dspi->cur_chip->ctar_val |
  686. SPI_FRAME_BITS(dspi->oper_bits_per_word));
  687. }
  688. static void dspi_fifo_write(struct fsl_dspi *dspi)
  689. {
  690. int num_fifo_entries = dspi->devtype_data->fifo_size;
  691. struct spi_transfer *xfer = dspi->cur_transfer;
  692. struct spi_message *msg = dspi->cur_msg;
  693. int num_words, num_bytes;
  694. dspi_setup_accel(dspi);
  695. /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */
  696. if (dspi->oper_word_size == 4)
  697. num_fifo_entries /= 2;
  698. /*
  699. * Integer division intentionally trims off odd (or non-multiple of 4)
  700. * numbers of bytes at the end of the buffer, which will be sent next
  701. * time using a smaller oper_word_size.
  702. */
  703. num_words = dspi->len / dspi->oper_word_size;
  704. if (num_words > num_fifo_entries)
  705. num_words = num_fifo_entries;
  706. /* Update total number of bytes that were transferred */
  707. num_bytes = num_words * dspi->oper_word_size;
  708. msg->actual_length += num_bytes;
  709. dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8);
  710. /*
  711. * Update shared variable for use in the next interrupt (both in
  712. * dspi_fifo_read and in dspi_fifo_write).
  713. */
  714. dspi->words_in_flight = num_words;
  715. spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq);
  716. dspi_xspi_fifo_write(dspi, num_words);
  717. /*
  718. * Everything after this point is in a potential race with the next
  719. * interrupt, so we must never use dspi->words_in_flight again since it
  720. * might already be modified by the next dspi_fifo_write.
  721. */
  722. spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
  723. dspi->progress, !dspi->irq);
  724. }
  725. static int dspi_rxtx(struct fsl_dspi *dspi)
  726. {
  727. dspi_fifo_read(dspi);
  728. if (!dspi->len)
  729. /* Success! */
  730. return 0;
  731. dspi_fifo_write(dspi);
  732. return -EINPROGRESS;
  733. }
  734. static int dspi_poll(struct fsl_dspi *dspi)
  735. {
  736. int tries = 1000;
  737. u32 spi_sr;
  738. do {
  739. regmap_read(dspi->regmap, SPI_SR, &spi_sr);
  740. regmap_write(dspi->regmap, SPI_SR, spi_sr);
  741. if (spi_sr & SPI_SR_CMDTCF)
  742. break;
  743. } while (--tries);
  744. if (!tries)
  745. return -ETIMEDOUT;
  746. return dspi_rxtx(dspi);
  747. }
  748. static irqreturn_t dspi_interrupt(int irq, void *dev_id)
  749. {
  750. struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
  751. u32 spi_sr;
  752. regmap_read(dspi->regmap, SPI_SR, &spi_sr);
  753. regmap_write(dspi->regmap, SPI_SR, spi_sr);
  754. if (!(spi_sr & SPI_SR_CMDTCF))
  755. return IRQ_NONE;
  756. if (dspi_rxtx(dspi) == 0)
  757. complete(&dspi->xfer_done);
  758. return IRQ_HANDLED;
  759. }
  760. static int dspi_transfer_one_message(struct spi_controller *ctlr,
  761. struct spi_message *message)
  762. {
  763. struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
  764. struct spi_device *spi = message->spi;
  765. struct spi_transfer *transfer;
  766. int status = 0;
  767. message->actual_length = 0;
  768. list_for_each_entry(transfer, &message->transfers, transfer_list) {
  769. dspi->cur_transfer = transfer;
  770. dspi->cur_msg = message;
  771. dspi->cur_chip = spi_get_ctldata(spi);
  772. /* Prepare command word for CMD FIFO */
  773. dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
  774. SPI_PUSHR_CMD_PCS(spi->chip_select);
  775. if (list_is_last(&dspi->cur_transfer->transfer_list,
  776. &dspi->cur_msg->transfers)) {
  777. /* Leave PCS activated after last transfer when
  778. * cs_change is set.
  779. */
  780. if (transfer->cs_change)
  781. dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
  782. } else {
  783. /* Keep PCS active between transfers in same message
  784. * when cs_change is not set, and de-activate PCS
  785. * between transfers in the same message when
  786. * cs_change is set.
  787. */
  788. if (!transfer->cs_change)
  789. dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
  790. }
  791. dspi->tx = transfer->tx_buf;
  792. dspi->rx = transfer->rx_buf;
  793. dspi->len = transfer->len;
  794. dspi->progress = 0;
  795. regmap_update_bits(dspi->regmap, SPI_MCR,
  796. SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
  797. SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
  798. spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
  799. dspi->progress, !dspi->irq);
  800. if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
  801. status = dspi_dma_xfer(dspi);
  802. } else {
  803. dspi_fifo_write(dspi);
  804. if (dspi->irq) {
  805. wait_for_completion(&dspi->xfer_done);
  806. reinit_completion(&dspi->xfer_done);
  807. } else {
  808. do {
  809. status = dspi_poll(dspi);
  810. } while (status == -EINPROGRESS);
  811. }
  812. }
  813. if (status)
  814. break;
  815. spi_transfer_delay_exec(transfer);
  816. }
  817. message->status = status;
  818. spi_finalize_current_message(ctlr);
  819. return status;
  820. }
  821. static int dspi_setup(struct spi_device *spi)
  822. {
  823. struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
  824. unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
  825. u32 cs_sck_delay = 0, sck_cs_delay = 0;
  826. struct fsl_dspi_platform_data *pdata;
  827. unsigned char pasc = 0, asc = 0;
  828. struct chip_data *chip;
  829. unsigned long clkrate;
  830. /* Only alloc on first setup */
  831. chip = spi_get_ctldata(spi);
  832. if (chip == NULL) {
  833. chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
  834. if (!chip)
  835. return -ENOMEM;
  836. }
  837. pdata = dev_get_platdata(&dspi->pdev->dev);
  838. if (!pdata) {
  839. of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
  840. &cs_sck_delay);
  841. of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
  842. &sck_cs_delay);
  843. } else {
  844. cs_sck_delay = pdata->cs_sck_delay;
  845. sck_cs_delay = pdata->sck_cs_delay;
  846. }
  847. clkrate = clk_get_rate(dspi->clk);
  848. hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
  849. /* Set PCS to SCK delay scale values */
  850. ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
  851. /* Set After SCK delay scale values */
  852. ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
  853. chip->ctar_val = 0;
  854. if (spi->mode & SPI_CPOL)
  855. chip->ctar_val |= SPI_CTAR_CPOL;
  856. if (spi->mode & SPI_CPHA)
  857. chip->ctar_val |= SPI_CTAR_CPHA;
  858. if (!spi_controller_is_slave(dspi->ctlr)) {
  859. chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
  860. SPI_CTAR_CSSCK(cssck) |
  861. SPI_CTAR_PASC(pasc) |
  862. SPI_CTAR_ASC(asc) |
  863. SPI_CTAR_PBR(pbr) |
  864. SPI_CTAR_BR(br);
  865. if (spi->mode & SPI_LSB_FIRST)
  866. chip->ctar_val |= SPI_CTAR_LSBFE;
  867. }
  868. spi_set_ctldata(spi, chip);
  869. return 0;
  870. }
  871. static void dspi_cleanup(struct spi_device *spi)
  872. {
  873. struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
  874. dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
  875. spi->controller->bus_num, spi->chip_select);
  876. kfree(chip);
  877. }
  878. static const struct of_device_id fsl_dspi_dt_ids[] = {
  879. {
  880. .compatible = "fsl,vf610-dspi",
  881. .data = &devtype_data[VF610],
  882. }, {
  883. .compatible = "fsl,ls1021a-v1.0-dspi",
  884. .data = &devtype_data[LS1021A],
  885. }, {
  886. .compatible = "fsl,ls1012a-dspi",
  887. .data = &devtype_data[LS1012A],
  888. }, {
  889. .compatible = "fsl,ls1028a-dspi",
  890. .data = &devtype_data[LS1028A],
  891. }, {
  892. .compatible = "fsl,ls1043a-dspi",
  893. .data = &devtype_data[LS1043A],
  894. }, {
  895. .compatible = "fsl,ls1046a-dspi",
  896. .data = &devtype_data[LS1046A],
  897. }, {
  898. .compatible = "fsl,ls2080a-dspi",
  899. .data = &devtype_data[LS2080A],
  900. }, {
  901. .compatible = "fsl,ls2085a-dspi",
  902. .data = &devtype_data[LS2085A],
  903. }, {
  904. .compatible = "fsl,lx2160a-dspi",
  905. .data = &devtype_data[LX2160A],
  906. },
  907. { /* sentinel */ }
  908. };
  909. MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
  910. #ifdef CONFIG_PM_SLEEP
  911. static int dspi_suspend(struct device *dev)
  912. {
  913. struct fsl_dspi *dspi = dev_get_drvdata(dev);
  914. if (dspi->irq)
  915. disable_irq(dspi->irq);
  916. spi_controller_suspend(dspi->ctlr);
  917. clk_disable_unprepare(dspi->clk);
  918. pinctrl_pm_select_sleep_state(dev);
  919. return 0;
  920. }
  921. static int dspi_resume(struct device *dev)
  922. {
  923. struct fsl_dspi *dspi = dev_get_drvdata(dev);
  924. int ret;
  925. pinctrl_pm_select_default_state(dev);
  926. ret = clk_prepare_enable(dspi->clk);
  927. if (ret)
  928. return ret;
  929. spi_controller_resume(dspi->ctlr);
  930. if (dspi->irq)
  931. enable_irq(dspi->irq);
  932. return 0;
  933. }
  934. #endif /* CONFIG_PM_SLEEP */
  935. static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
  936. static const struct regmap_range dspi_volatile_ranges[] = {
  937. regmap_reg_range(SPI_MCR, SPI_TCR),
  938. regmap_reg_range(SPI_SR, SPI_SR),
  939. regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
  940. };
  941. static const struct regmap_access_table dspi_volatile_table = {
  942. .yes_ranges = dspi_volatile_ranges,
  943. .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
  944. };
  945. static const struct regmap_config dspi_regmap_config = {
  946. .reg_bits = 32,
  947. .val_bits = 32,
  948. .reg_stride = 4,
  949. .max_register = 0x88,
  950. .volatile_table = &dspi_volatile_table,
  951. };
  952. static const struct regmap_range dspi_xspi_volatile_ranges[] = {
  953. regmap_reg_range(SPI_MCR, SPI_TCR),
  954. regmap_reg_range(SPI_SR, SPI_SR),
  955. regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
  956. regmap_reg_range(SPI_SREX, SPI_SREX),
  957. };
  958. static const struct regmap_access_table dspi_xspi_volatile_table = {
  959. .yes_ranges = dspi_xspi_volatile_ranges,
  960. .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
  961. };
  962. static const struct regmap_config dspi_xspi_regmap_config[] = {
  963. {
  964. .reg_bits = 32,
  965. .val_bits = 32,
  966. .reg_stride = 4,
  967. .max_register = 0x13c,
  968. .volatile_table = &dspi_xspi_volatile_table,
  969. },
  970. {
  971. .name = "pushr",
  972. .reg_bits = 16,
  973. .val_bits = 16,
  974. .reg_stride = 2,
  975. .max_register = 0x2,
  976. },
  977. };
  978. static int dspi_init(struct fsl_dspi *dspi)
  979. {
  980. unsigned int mcr;
  981. /* Set idle states for all chip select signals to high */
  982. mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0));
  983. if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
  984. mcr |= SPI_MCR_XSPI;
  985. if (!spi_controller_is_slave(dspi->ctlr))
  986. mcr |= SPI_MCR_MASTER;
  987. regmap_write(dspi->regmap, SPI_MCR, mcr);
  988. regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
  989. switch (dspi->devtype_data->trans_mode) {
  990. case DSPI_XSPI_MODE:
  991. regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE);
  992. break;
  993. case DSPI_DMA_MODE:
  994. regmap_write(dspi->regmap, SPI_RSER,
  995. SPI_RSER_TFFFE | SPI_RSER_TFFFD |
  996. SPI_RSER_RFDFE | SPI_RSER_RFDFD);
  997. break;
  998. default:
  999. dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
  1000. dspi->devtype_data->trans_mode);
  1001. return -EINVAL;
  1002. }
  1003. return 0;
  1004. }
  1005. static int dspi_slave_abort(struct spi_master *master)
  1006. {
  1007. struct fsl_dspi *dspi = spi_master_get_devdata(master);
  1008. /*
  1009. * Terminate all pending DMA transactions for the SPI working
  1010. * in SLAVE mode.
  1011. */
  1012. if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
  1013. dmaengine_terminate_sync(dspi->dma->chan_rx);
  1014. dmaengine_terminate_sync(dspi->dma->chan_tx);
  1015. }
  1016. /* Clear the internal DSPI RX and TX FIFO buffers */
  1017. regmap_update_bits(dspi->regmap, SPI_MCR,
  1018. SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
  1019. SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
  1020. return 0;
  1021. }
  1022. static int dspi_probe(struct platform_device *pdev)
  1023. {
  1024. struct device_node *np = pdev->dev.of_node;
  1025. const struct regmap_config *regmap_config;
  1026. struct fsl_dspi_platform_data *pdata;
  1027. struct spi_controller *ctlr;
  1028. int ret, cs_num, bus_num = -1;
  1029. struct fsl_dspi *dspi;
  1030. struct resource *res;
  1031. void __iomem *base;
  1032. bool big_endian;
  1033. dspi = devm_kzalloc(&pdev->dev, sizeof(*dspi), GFP_KERNEL);
  1034. if (!dspi)
  1035. return -ENOMEM;
  1036. ctlr = spi_alloc_master(&pdev->dev, 0);
  1037. if (!ctlr)
  1038. return -ENOMEM;
  1039. spi_controller_set_devdata(ctlr, dspi);
  1040. platform_set_drvdata(pdev, dspi);
  1041. dspi->pdev = pdev;
  1042. dspi->ctlr = ctlr;
  1043. ctlr->setup = dspi_setup;
  1044. ctlr->transfer_one_message = dspi_transfer_one_message;
  1045. ctlr->dev.of_node = pdev->dev.of_node;
  1046. ctlr->cleanup = dspi_cleanup;
  1047. ctlr->slave_abort = dspi_slave_abort;
  1048. ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
  1049. pdata = dev_get_platdata(&pdev->dev);
  1050. if (pdata) {
  1051. ctlr->num_chipselect = ctlr->max_native_cs = pdata->cs_num;
  1052. ctlr->bus_num = pdata->bus_num;
  1053. /* Only Coldfire uses platform data */
  1054. dspi->devtype_data = &devtype_data[MCF5441X];
  1055. big_endian = true;
  1056. } else {
  1057. ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
  1058. if (ret < 0) {
  1059. dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
  1060. goto out_ctlr_put;
  1061. }
  1062. ctlr->num_chipselect = ctlr->max_native_cs = cs_num;
  1063. of_property_read_u32(np, "bus-num", &bus_num);
  1064. ctlr->bus_num = bus_num;
  1065. if (of_property_read_bool(np, "spi-slave"))
  1066. ctlr->slave = true;
  1067. dspi->devtype_data = of_device_get_match_data(&pdev->dev);
  1068. if (!dspi->devtype_data) {
  1069. dev_err(&pdev->dev, "can't get devtype_data\n");
  1070. ret = -EFAULT;
  1071. goto out_ctlr_put;
  1072. }
  1073. big_endian = of_device_is_big_endian(np);
  1074. }
  1075. if (big_endian) {
  1076. dspi->pushr_cmd = 0;
  1077. dspi->pushr_tx = 2;
  1078. } else {
  1079. dspi->pushr_cmd = 2;
  1080. dspi->pushr_tx = 0;
  1081. }
  1082. if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
  1083. ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
  1084. else
  1085. ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
  1086. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1087. base = devm_ioremap_resource(&pdev->dev, res);
  1088. if (IS_ERR(base)) {
  1089. ret = PTR_ERR(base);
  1090. goto out_ctlr_put;
  1091. }
  1092. if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
  1093. regmap_config = &dspi_xspi_regmap_config[0];
  1094. else
  1095. regmap_config = &dspi_regmap_config;
  1096. dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
  1097. if (IS_ERR(dspi->regmap)) {
  1098. dev_err(&pdev->dev, "failed to init regmap: %ld\n",
  1099. PTR_ERR(dspi->regmap));
  1100. ret = PTR_ERR(dspi->regmap);
  1101. goto out_ctlr_put;
  1102. }
  1103. if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
  1104. dspi->regmap_pushr = devm_regmap_init_mmio(
  1105. &pdev->dev, base + SPI_PUSHR,
  1106. &dspi_xspi_regmap_config[1]);
  1107. if (IS_ERR(dspi->regmap_pushr)) {
  1108. dev_err(&pdev->dev,
  1109. "failed to init pushr regmap: %ld\n",
  1110. PTR_ERR(dspi->regmap_pushr));
  1111. ret = PTR_ERR(dspi->regmap_pushr);
  1112. goto out_ctlr_put;
  1113. }
  1114. }
  1115. dspi->clk = devm_clk_get(&pdev->dev, "dspi");
  1116. if (IS_ERR(dspi->clk)) {
  1117. ret = PTR_ERR(dspi->clk);
  1118. dev_err(&pdev->dev, "unable to get clock\n");
  1119. goto out_ctlr_put;
  1120. }
  1121. ret = clk_prepare_enable(dspi->clk);
  1122. if (ret)
  1123. goto out_ctlr_put;
  1124. ret = dspi_init(dspi);
  1125. if (ret)
  1126. goto out_clk_put;
  1127. dspi->irq = platform_get_irq(pdev, 0);
  1128. if (dspi->irq <= 0) {
  1129. dev_info(&pdev->dev,
  1130. "can't get platform irq, using poll mode\n");
  1131. dspi->irq = 0;
  1132. goto poll_mode;
  1133. }
  1134. init_completion(&dspi->xfer_done);
  1135. ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
  1136. IRQF_SHARED, pdev->name, dspi);
  1137. if (ret < 0) {
  1138. dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
  1139. goto out_clk_put;
  1140. }
  1141. poll_mode:
  1142. if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
  1143. ret = dspi_request_dma(dspi, res->start);
  1144. if (ret < 0) {
  1145. dev_err(&pdev->dev, "can't get dma channels\n");
  1146. goto out_free_irq;
  1147. }
  1148. }
  1149. ctlr->max_speed_hz =
  1150. clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
  1151. if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE)
  1152. ctlr->ptp_sts_supported = true;
  1153. ret = spi_register_controller(ctlr);
  1154. if (ret != 0) {
  1155. dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
  1156. goto out_release_dma;
  1157. }
  1158. return ret;
  1159. out_release_dma:
  1160. dspi_release_dma(dspi);
  1161. out_free_irq:
  1162. if (dspi->irq)
  1163. free_irq(dspi->irq, dspi);
  1164. out_clk_put:
  1165. clk_disable_unprepare(dspi->clk);
  1166. out_ctlr_put:
  1167. spi_controller_put(ctlr);
  1168. return ret;
  1169. }
  1170. static int dspi_remove(struct platform_device *pdev)
  1171. {
  1172. struct fsl_dspi *dspi = platform_get_drvdata(pdev);
  1173. /* Disconnect from the SPI framework */
  1174. spi_unregister_controller(dspi->ctlr);
  1175. /* Disable RX and TX */
  1176. regmap_update_bits(dspi->regmap, SPI_MCR,
  1177. SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
  1178. SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
  1179. /* Stop Running */
  1180. regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
  1181. dspi_release_dma(dspi);
  1182. if (dspi->irq)
  1183. free_irq(dspi->irq, dspi);
  1184. clk_disable_unprepare(dspi->clk);
  1185. return 0;
  1186. }
  1187. static void dspi_shutdown(struct platform_device *pdev)
  1188. {
  1189. dspi_remove(pdev);
  1190. }
  1191. static struct platform_driver fsl_dspi_driver = {
  1192. .driver.name = DRIVER_NAME,
  1193. .driver.of_match_table = fsl_dspi_dt_ids,
  1194. .driver.owner = THIS_MODULE,
  1195. .driver.pm = &dspi_pm,
  1196. .probe = dspi_probe,
  1197. .remove = dspi_remove,
  1198. .shutdown = dspi_shutdown,
  1199. };
  1200. module_platform_driver(fsl_dspi_driver);
  1201. MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
  1202. MODULE_LICENSE("GPL");
  1203. MODULE_ALIAS("platform:" DRIVER_NAME);