spi-fsi.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. // Copyright (C) IBM Corporation 2020
  3. #include <linux/bitfield.h>
  4. #include <linux/bits.h>
  5. #include <linux/fsi.h>
  6. #include <linux/jiffies.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/of.h>
  10. #include <linux/spi/spi.h>
  11. #define FSI_ENGID_SPI 0x23
  12. #define FSI_MBOX_ROOT_CTRL_8 0x2860
  13. #define FSI_MBOX_ROOT_CTRL_8_SPI_MUX 0xf0000000
  14. #define FSI2SPI_DATA0 0x00
  15. #define FSI2SPI_DATA1 0x04
  16. #define FSI2SPI_CMD 0x08
  17. #define FSI2SPI_CMD_WRITE BIT(31)
  18. #define FSI2SPI_RESET 0x18
  19. #define FSI2SPI_STATUS 0x1c
  20. #define FSI2SPI_STATUS_ANY_ERROR BIT(31)
  21. #define FSI2SPI_IRQ 0x20
  22. #define SPI_FSI_BASE 0x70000
  23. #define SPI_FSI_INIT_TIMEOUT_MS 1000
  24. #define SPI_FSI_MAX_XFR_SIZE 2048
  25. #define SPI_FSI_MAX_XFR_SIZE_RESTRICTED 32
  26. #define SPI_FSI_ERROR 0x0
  27. #define SPI_FSI_COUNTER_CFG 0x1
  28. #define SPI_FSI_COUNTER_CFG_LOOPS(x) (((u64)(x) & 0xffULL) << 32)
  29. #define SPI_FSI_COUNTER_CFG_N2_RX BIT_ULL(8)
  30. #define SPI_FSI_COUNTER_CFG_N2_TX BIT_ULL(9)
  31. #define SPI_FSI_COUNTER_CFG_N2_IMPLICIT BIT_ULL(10)
  32. #define SPI_FSI_COUNTER_CFG_N2_RELOAD BIT_ULL(11)
  33. #define SPI_FSI_CFG1 0x2
  34. #define SPI_FSI_CLOCK_CFG 0x3
  35. #define SPI_FSI_CLOCK_CFG_MM_ENABLE BIT_ULL(32)
  36. #define SPI_FSI_CLOCK_CFG_ECC_DISABLE (BIT_ULL(35) | BIT_ULL(33))
  37. #define SPI_FSI_CLOCK_CFG_RESET1 (BIT_ULL(36) | BIT_ULL(38))
  38. #define SPI_FSI_CLOCK_CFG_RESET2 (BIT_ULL(37) | BIT_ULL(39))
  39. #define SPI_FSI_CLOCK_CFG_MODE (BIT_ULL(41) | BIT_ULL(42))
  40. #define SPI_FSI_CLOCK_CFG_SCK_RECV_DEL GENMASK_ULL(51, 44)
  41. #define SPI_FSI_CLOCK_CFG_SCK_NO_DEL BIT_ULL(51)
  42. #define SPI_FSI_CLOCK_CFG_SCK_DIV GENMASK_ULL(63, 52)
  43. #define SPI_FSI_MMAP 0x4
  44. #define SPI_FSI_DATA_TX 0x5
  45. #define SPI_FSI_DATA_RX 0x6
  46. #define SPI_FSI_SEQUENCE 0x7
  47. #define SPI_FSI_SEQUENCE_STOP 0x00
  48. #define SPI_FSI_SEQUENCE_SEL_SLAVE(x) (0x10 | ((x) & 0xf))
  49. #define SPI_FSI_SEQUENCE_SHIFT_OUT(x) (0x30 | ((x) & 0xf))
  50. #define SPI_FSI_SEQUENCE_SHIFT_IN(x) (0x40 | ((x) & 0xf))
  51. #define SPI_FSI_SEQUENCE_COPY_DATA_TX 0xc0
  52. #define SPI_FSI_SEQUENCE_BRANCH(x) (0xe0 | ((x) & 0xf))
  53. #define SPI_FSI_STATUS 0x8
  54. #define SPI_FSI_STATUS_ERROR \
  55. (GENMASK_ULL(31, 21) | GENMASK_ULL(15, 12))
  56. #define SPI_FSI_STATUS_SEQ_STATE GENMASK_ULL(55, 48)
  57. #define SPI_FSI_STATUS_SEQ_STATE_IDLE BIT_ULL(48)
  58. #define SPI_FSI_STATUS_TDR_UNDERRUN BIT_ULL(57)
  59. #define SPI_FSI_STATUS_TDR_OVERRUN BIT_ULL(58)
  60. #define SPI_FSI_STATUS_TDR_FULL BIT_ULL(59)
  61. #define SPI_FSI_STATUS_RDR_UNDERRUN BIT_ULL(61)
  62. #define SPI_FSI_STATUS_RDR_OVERRUN BIT_ULL(62)
  63. #define SPI_FSI_STATUS_RDR_FULL BIT_ULL(63)
  64. #define SPI_FSI_STATUS_ANY_ERROR \
  65. (SPI_FSI_STATUS_ERROR | \
  66. SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \
  67. SPI_FSI_STATUS_RDR_OVERRUN)
  68. #define SPI_FSI_PORT_CTRL 0x9
  69. struct fsi_spi {
  70. struct device *dev; /* SPI controller device */
  71. struct fsi_device *fsi; /* FSI2SPI CFAM engine device */
  72. u32 base;
  73. size_t max_xfr_size;
  74. bool restricted;
  75. };
  76. struct fsi_spi_sequence {
  77. int bit;
  78. u64 data;
  79. };
  80. static int fsi_spi_check_mux(struct fsi_device *fsi, struct device *dev)
  81. {
  82. int rc;
  83. u32 root_ctrl_8;
  84. __be32 root_ctrl_8_be;
  85. rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8_be,
  86. sizeof(root_ctrl_8_be));
  87. if (rc)
  88. return rc;
  89. root_ctrl_8 = be32_to_cpu(root_ctrl_8_be);
  90. dev_dbg(dev, "Root control register 8: %08x\n", root_ctrl_8);
  91. if ((root_ctrl_8 & FSI_MBOX_ROOT_CTRL_8_SPI_MUX) ==
  92. FSI_MBOX_ROOT_CTRL_8_SPI_MUX)
  93. return 0;
  94. return -ENOLINK;
  95. }
  96. static int fsi_spi_check_status(struct fsi_spi *ctx)
  97. {
  98. int rc;
  99. u32 sts;
  100. __be32 sts_be;
  101. rc = fsi_device_read(ctx->fsi, FSI2SPI_STATUS, &sts_be,
  102. sizeof(sts_be));
  103. if (rc)
  104. return rc;
  105. sts = be32_to_cpu(sts_be);
  106. if (sts & FSI2SPI_STATUS_ANY_ERROR) {
  107. dev_err(ctx->dev, "Error with FSI2SPI interface: %08x.\n", sts);
  108. return -EIO;
  109. }
  110. return 0;
  111. }
  112. static int fsi_spi_read_reg(struct fsi_spi *ctx, u32 offset, u64 *value)
  113. {
  114. int rc;
  115. __be32 cmd_be;
  116. __be32 data_be;
  117. u32 cmd = offset + ctx->base;
  118. *value = 0ULL;
  119. if (cmd & FSI2SPI_CMD_WRITE)
  120. return -EINVAL;
  121. cmd_be = cpu_to_be32(cmd);
  122. rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be));
  123. if (rc)
  124. return rc;
  125. rc = fsi_spi_check_status(ctx);
  126. if (rc)
  127. return rc;
  128. rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA0, &data_be,
  129. sizeof(data_be));
  130. if (rc)
  131. return rc;
  132. *value |= (u64)be32_to_cpu(data_be) << 32;
  133. rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA1, &data_be,
  134. sizeof(data_be));
  135. if (rc)
  136. return rc;
  137. *value |= (u64)be32_to_cpu(data_be);
  138. dev_dbg(ctx->dev, "Read %02x[%016llx].\n", offset, *value);
  139. return 0;
  140. }
  141. static int fsi_spi_write_reg(struct fsi_spi *ctx, u32 offset, u64 value)
  142. {
  143. int rc;
  144. __be32 cmd_be;
  145. __be32 data_be;
  146. u32 cmd = offset + ctx->base;
  147. if (cmd & FSI2SPI_CMD_WRITE)
  148. return -EINVAL;
  149. dev_dbg(ctx->dev, "Write %02x[%016llx].\n", offset, value);
  150. data_be = cpu_to_be32(upper_32_bits(value));
  151. rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA0, &data_be,
  152. sizeof(data_be));
  153. if (rc)
  154. return rc;
  155. data_be = cpu_to_be32(lower_32_bits(value));
  156. rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA1, &data_be,
  157. sizeof(data_be));
  158. if (rc)
  159. return rc;
  160. cmd_be = cpu_to_be32(cmd | FSI2SPI_CMD_WRITE);
  161. rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be));
  162. if (rc)
  163. return rc;
  164. return fsi_spi_check_status(ctx);
  165. }
  166. static int fsi_spi_data_in(u64 in, u8 *rx, int len)
  167. {
  168. int i;
  169. int num_bytes = min(len, 8);
  170. for (i = 0; i < num_bytes; ++i)
  171. rx[i] = (u8)(in >> (8 * ((num_bytes - 1) - i)));
  172. return num_bytes;
  173. }
  174. static int fsi_spi_data_out(u64 *out, const u8 *tx, int len)
  175. {
  176. int i;
  177. int num_bytes = min(len, 8);
  178. u8 *out_bytes = (u8 *)out;
  179. /* Unused bytes of the tx data should be 0. */
  180. *out = 0ULL;
  181. for (i = 0; i < num_bytes; ++i)
  182. out_bytes[8 - (i + 1)] = tx[i];
  183. return num_bytes;
  184. }
  185. static int fsi_spi_reset(struct fsi_spi *ctx)
  186. {
  187. int rc;
  188. dev_dbg(ctx->dev, "Resetting SPI controller.\n");
  189. rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
  190. SPI_FSI_CLOCK_CFG_RESET1);
  191. if (rc)
  192. return rc;
  193. rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
  194. SPI_FSI_CLOCK_CFG_RESET2);
  195. if (rc)
  196. return rc;
  197. return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL);
  198. }
  199. static int fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val)
  200. {
  201. /*
  202. * Add the next byte of instruction to the 8-byte sequence register.
  203. * Then decrement the counter so that the next instruction will go in
  204. * the right place. Return the index of the slot we just filled in the
  205. * sequence register.
  206. */
  207. seq->data |= (u64)val << seq->bit;
  208. seq->bit -= 8;
  209. return ((64 - seq->bit) / 8) - 2;
  210. }
  211. static void fsi_spi_sequence_init(struct fsi_spi_sequence *seq)
  212. {
  213. seq->bit = 56;
  214. seq->data = 0ULL;
  215. }
  216. static int fsi_spi_sequence_transfer(struct fsi_spi *ctx,
  217. struct fsi_spi_sequence *seq,
  218. struct spi_transfer *transfer)
  219. {
  220. bool docfg = false;
  221. int loops;
  222. int idx;
  223. int rc;
  224. u8 val = 0;
  225. u8 len = min(transfer->len, 8U);
  226. u8 rem = transfer->len % len;
  227. u64 cfg = 0ULL;
  228. loops = transfer->len / len;
  229. if (transfer->tx_buf) {
  230. val = SPI_FSI_SEQUENCE_SHIFT_OUT(len);
  231. idx = fsi_spi_sequence_add(seq, val);
  232. if (rem)
  233. rem = SPI_FSI_SEQUENCE_SHIFT_OUT(rem);
  234. } else if (transfer->rx_buf) {
  235. val = SPI_FSI_SEQUENCE_SHIFT_IN(len);
  236. idx = fsi_spi_sequence_add(seq, val);
  237. if (rem)
  238. rem = SPI_FSI_SEQUENCE_SHIFT_IN(rem);
  239. } else {
  240. return -EINVAL;
  241. }
  242. if (ctx->restricted) {
  243. const int eidx = rem ? 5 : 6;
  244. while (loops > 1 && idx <= eidx) {
  245. idx = fsi_spi_sequence_add(seq, val);
  246. loops--;
  247. docfg = true;
  248. }
  249. if (loops > 1) {
  250. dev_warn(ctx->dev, "No sequencer slots; aborting.\n");
  251. return -EINVAL;
  252. }
  253. }
  254. if (loops > 1) {
  255. fsi_spi_sequence_add(seq, SPI_FSI_SEQUENCE_BRANCH(idx));
  256. docfg = true;
  257. }
  258. if (docfg) {
  259. cfg = SPI_FSI_COUNTER_CFG_LOOPS(loops - 1);
  260. if (transfer->rx_buf)
  261. cfg |= SPI_FSI_COUNTER_CFG_N2_RX |
  262. SPI_FSI_COUNTER_CFG_N2_TX |
  263. SPI_FSI_COUNTER_CFG_N2_IMPLICIT |
  264. SPI_FSI_COUNTER_CFG_N2_RELOAD;
  265. rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, cfg);
  266. if (rc)
  267. return rc;
  268. } else {
  269. fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);
  270. }
  271. if (rem)
  272. fsi_spi_sequence_add(seq, rem);
  273. return 0;
  274. }
  275. static int fsi_spi_transfer_data(struct fsi_spi *ctx,
  276. struct spi_transfer *transfer)
  277. {
  278. int rc = 0;
  279. u64 status = 0ULL;
  280. u64 cfg = 0ULL;
  281. if (transfer->tx_buf) {
  282. int nb;
  283. int sent = 0;
  284. u64 out = 0ULL;
  285. const u8 *tx = transfer->tx_buf;
  286. while (transfer->len > sent) {
  287. nb = fsi_spi_data_out(&out, &tx[sent],
  288. (int)transfer->len - sent);
  289. rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out);
  290. if (rc)
  291. return rc;
  292. do {
  293. rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS,
  294. &status);
  295. if (rc)
  296. return rc;
  297. if (status & SPI_FSI_STATUS_ANY_ERROR) {
  298. rc = fsi_spi_reset(ctx);
  299. if (rc)
  300. return rc;
  301. return -EREMOTEIO;
  302. }
  303. } while (status & SPI_FSI_STATUS_TDR_FULL);
  304. sent += nb;
  305. }
  306. } else if (transfer->rx_buf) {
  307. int recv = 0;
  308. u64 in = 0ULL;
  309. u8 *rx = transfer->rx_buf;
  310. rc = fsi_spi_read_reg(ctx, SPI_FSI_COUNTER_CFG, &cfg);
  311. if (rc)
  312. return rc;
  313. if (cfg & SPI_FSI_COUNTER_CFG_N2_IMPLICIT) {
  314. rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, 0);
  315. if (rc)
  316. return rc;
  317. }
  318. while (transfer->len > recv) {
  319. do {
  320. rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS,
  321. &status);
  322. if (rc)
  323. return rc;
  324. if (status & SPI_FSI_STATUS_ANY_ERROR) {
  325. rc = fsi_spi_reset(ctx);
  326. if (rc)
  327. return rc;
  328. return -EREMOTEIO;
  329. }
  330. } while (!(status & SPI_FSI_STATUS_RDR_FULL));
  331. rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in);
  332. if (rc)
  333. return rc;
  334. recv += fsi_spi_data_in(in, &rx[recv],
  335. (int)transfer->len - recv);
  336. }
  337. }
  338. return 0;
  339. }
  340. static int fsi_spi_transfer_init(struct fsi_spi *ctx)
  341. {
  342. int rc;
  343. bool reset = false;
  344. unsigned long end;
  345. u64 seq_state;
  346. u64 clock_cfg = 0ULL;
  347. u64 status = 0ULL;
  348. u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE |
  349. SPI_FSI_CLOCK_CFG_SCK_NO_DEL |
  350. FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19);
  351. end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS);
  352. do {
  353. if (time_after(jiffies, end))
  354. return -ETIMEDOUT;
  355. rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status);
  356. if (rc)
  357. return rc;
  358. seq_state = status & SPI_FSI_STATUS_SEQ_STATE;
  359. if (status & (SPI_FSI_STATUS_ANY_ERROR |
  360. SPI_FSI_STATUS_TDR_FULL |
  361. SPI_FSI_STATUS_RDR_FULL)) {
  362. if (reset)
  363. return -EIO;
  364. rc = fsi_spi_reset(ctx);
  365. if (rc)
  366. return rc;
  367. reset = true;
  368. continue;
  369. }
  370. } while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE));
  371. rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg);
  372. if (rc)
  373. return rc;
  374. if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE |
  375. SPI_FSI_CLOCK_CFG_ECC_DISABLE |
  376. SPI_FSI_CLOCK_CFG_MODE |
  377. SPI_FSI_CLOCK_CFG_SCK_RECV_DEL |
  378. SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg)
  379. rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
  380. wanted_clock_cfg);
  381. return rc;
  382. }
  383. static int fsi_spi_transfer_one_message(struct spi_controller *ctlr,
  384. struct spi_message *mesg)
  385. {
  386. int rc;
  387. u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1);
  388. struct spi_transfer *transfer;
  389. struct fsi_spi *ctx = spi_controller_get_devdata(ctlr);
  390. rc = fsi_spi_check_mux(ctx->fsi, ctx->dev);
  391. if (rc)
  392. goto error;
  393. list_for_each_entry(transfer, &mesg->transfers, transfer_list) {
  394. struct fsi_spi_sequence seq;
  395. struct spi_transfer *next = NULL;
  396. /* Sequencer must do shift out (tx) first. */
  397. if (!transfer->tx_buf ||
  398. transfer->len > (ctx->max_xfr_size + 8)) {
  399. rc = -EINVAL;
  400. goto error;
  401. }
  402. dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len);
  403. rc = fsi_spi_transfer_init(ctx);
  404. if (rc < 0)
  405. goto error;
  406. fsi_spi_sequence_init(&seq);
  407. fsi_spi_sequence_add(&seq, seq_slave);
  408. rc = fsi_spi_sequence_transfer(ctx, &seq, transfer);
  409. if (rc)
  410. goto error;
  411. if (!list_is_last(&transfer->transfer_list,
  412. &mesg->transfers)) {
  413. next = list_next_entry(transfer, transfer_list);
  414. /* Sequencer can only do shift in (rx) after tx. */
  415. if (next->rx_buf) {
  416. if (next->len > ctx->max_xfr_size) {
  417. rc = -EINVAL;
  418. goto error;
  419. }
  420. dev_dbg(ctx->dev, "Sequence rx of %d bytes.\n",
  421. next->len);
  422. rc = fsi_spi_sequence_transfer(ctx, &seq,
  423. next);
  424. if (rc)
  425. goto error;
  426. } else {
  427. next = NULL;
  428. }
  429. }
  430. fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SEL_SLAVE(0));
  431. rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data);
  432. if (rc)
  433. goto error;
  434. rc = fsi_spi_transfer_data(ctx, transfer);
  435. if (rc)
  436. goto error;
  437. if (next) {
  438. rc = fsi_spi_transfer_data(ctx, next);
  439. if (rc)
  440. goto error;
  441. transfer = next;
  442. }
  443. }
  444. error:
  445. mesg->status = rc;
  446. spi_finalize_current_message(ctlr);
  447. return rc;
  448. }
  449. static size_t fsi_spi_max_transfer_size(struct spi_device *spi)
  450. {
  451. struct fsi_spi *ctx = spi_controller_get_devdata(spi->controller);
  452. return ctx->max_xfr_size;
  453. }
  454. static int fsi_spi_probe(struct device *dev)
  455. {
  456. int rc;
  457. struct device_node *np;
  458. int num_controllers_registered = 0;
  459. struct fsi_device *fsi = to_fsi_dev(dev);
  460. rc = fsi_spi_check_mux(fsi, dev);
  461. if (rc)
  462. return -ENODEV;
  463. for_each_available_child_of_node(dev->of_node, np) {
  464. u32 base;
  465. struct fsi_spi *ctx;
  466. struct spi_controller *ctlr;
  467. if (of_property_read_u32(np, "reg", &base))
  468. continue;
  469. ctlr = spi_alloc_master(dev, sizeof(*ctx));
  470. if (!ctlr)
  471. break;
  472. ctlr->dev.of_node = np;
  473. ctlr->num_chipselect = of_get_available_child_count(np) ?: 1;
  474. ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
  475. ctlr->max_transfer_size = fsi_spi_max_transfer_size;
  476. ctlr->transfer_one_message = fsi_spi_transfer_one_message;
  477. ctx = spi_controller_get_devdata(ctlr);
  478. ctx->dev = &ctlr->dev;
  479. ctx->fsi = fsi;
  480. ctx->base = base + SPI_FSI_BASE;
  481. if (of_device_is_compatible(np, "ibm,fsi2spi-restricted")) {
  482. ctx->restricted = true;
  483. ctx->max_xfr_size = SPI_FSI_MAX_XFR_SIZE_RESTRICTED;
  484. } else {
  485. ctx->restricted = false;
  486. ctx->max_xfr_size = SPI_FSI_MAX_XFR_SIZE;
  487. }
  488. rc = devm_spi_register_controller(dev, ctlr);
  489. if (rc)
  490. spi_controller_put(ctlr);
  491. else
  492. num_controllers_registered++;
  493. }
  494. if (!num_controllers_registered)
  495. return -ENODEV;
  496. return 0;
  497. }
  498. static const struct fsi_device_id fsi_spi_ids[] = {
  499. { FSI_ENGID_SPI, FSI_VERSION_ANY },
  500. { }
  501. };
  502. MODULE_DEVICE_TABLE(fsi, fsi_spi_ids);
  503. static struct fsi_driver fsi_spi_driver = {
  504. .id_table = fsi_spi_ids,
  505. .drv = {
  506. .name = "spi-fsi",
  507. .bus = &fsi_bus_type,
  508. .probe = fsi_spi_probe,
  509. },
  510. };
  511. module_fsi_driver(fsi_spi_driver);
  512. MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>");
  513. MODULE_DESCRIPTION("FSI attached SPI controller");
  514. MODULE_LICENSE("GPL");