spi-dw.h 7.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef DW_SPI_HEADER_H
  3. #define DW_SPI_HEADER_H
  4. #include <linux/bits.h>
  5. #include <linux/completion.h>
  6. #include <linux/debugfs.h>
  7. #include <linux/irqreturn.h>
  8. #include <linux/io.h>
  9. #include <linux/scatterlist.h>
  10. #include <linux/spi/spi-mem.h>
  11. /* Register offsets */
  12. #define DW_SPI_CTRLR0 0x00
  13. #define DW_SPI_CTRLR1 0x04
  14. #define DW_SPI_SSIENR 0x08
  15. #define DW_SPI_MWCR 0x0c
  16. #define DW_SPI_SER 0x10
  17. #define DW_SPI_BAUDR 0x14
  18. #define DW_SPI_TXFTLR 0x18
  19. #define DW_SPI_RXFTLR 0x1c
  20. #define DW_SPI_TXFLR 0x20
  21. #define DW_SPI_RXFLR 0x24
  22. #define DW_SPI_SR 0x28
  23. #define DW_SPI_IMR 0x2c
  24. #define DW_SPI_ISR 0x30
  25. #define DW_SPI_RISR 0x34
  26. #define DW_SPI_TXOICR 0x38
  27. #define DW_SPI_RXOICR 0x3c
  28. #define DW_SPI_RXUICR 0x40
  29. #define DW_SPI_MSTICR 0x44
  30. #define DW_SPI_ICR 0x48
  31. #define DW_SPI_DMACR 0x4c
  32. #define DW_SPI_DMATDLR 0x50
  33. #define DW_SPI_DMARDLR 0x54
  34. #define DW_SPI_IDR 0x58
  35. #define DW_SPI_VERSION 0x5c
  36. #define DW_SPI_DR 0x60
  37. #define DW_SPI_RX_SAMPLE_DLY 0xf0
  38. #define DW_SPI_CS_OVERRIDE 0xf4
  39. /* Bit fields in CTRLR0 */
  40. #define SPI_DFS_OFFSET 0
  41. #define SPI_FRF_OFFSET 4
  42. #define SPI_FRF_SPI 0x0
  43. #define SPI_FRF_SSP 0x1
  44. #define SPI_FRF_MICROWIRE 0x2
  45. #define SPI_FRF_RESV 0x3
  46. #define SPI_MODE_OFFSET 6
  47. #define SPI_SCPH_OFFSET 6
  48. #define SPI_SCOL_OFFSET 7
  49. #define SPI_TMOD_OFFSET 8
  50. #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
  51. #define SPI_TMOD_TR 0x0 /* xmit & recv */
  52. #define SPI_TMOD_TO 0x1 /* xmit only */
  53. #define SPI_TMOD_RO 0x2 /* recv only */
  54. #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
  55. #define SPI_SLVOE_OFFSET 10
  56. #define SPI_SRL_OFFSET 11
  57. #define SPI_CFS_OFFSET 12
  58. /* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
  59. #define DWC_SSI_CTRLR0_SRL_OFFSET 13
  60. #define DWC_SSI_CTRLR0_TMOD_OFFSET 10
  61. #define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
  62. #define DWC_SSI_CTRLR0_SCPOL_OFFSET 9
  63. #define DWC_SSI_CTRLR0_SCPH_OFFSET 8
  64. #define DWC_SSI_CTRLR0_FRF_OFFSET 6
  65. #define DWC_SSI_CTRLR0_DFS_OFFSET 0
  66. /*
  67. * For Keem Bay, CTRLR0[31] is used to select controller mode.
  68. * 0: SSI is slave
  69. * 1: SSI is master
  70. */
  71. #define DWC_SSI_CTRLR0_KEEMBAY_MST BIT(31)
  72. /* Bit fields in CTRLR1 */
  73. #define SPI_NDF_MASK GENMASK(15, 0)
  74. /* Bit fields in SR, 7 bits */
  75. #define SR_MASK 0x7f /* cover 7 bits */
  76. #define SR_BUSY (1 << 0)
  77. #define SR_TF_NOT_FULL (1 << 1)
  78. #define SR_TF_EMPT (1 << 2)
  79. #define SR_RF_NOT_EMPT (1 << 3)
  80. #define SR_RF_FULL (1 << 4)
  81. #define SR_TX_ERR (1 << 5)
  82. #define SR_DCOL (1 << 6)
  83. /* Bit fields in ISR, IMR, RISR, 7 bits */
  84. #define SPI_INT_TXEI (1 << 0)
  85. #define SPI_INT_TXOI (1 << 1)
  86. #define SPI_INT_RXUI (1 << 2)
  87. #define SPI_INT_RXOI (1 << 3)
  88. #define SPI_INT_RXFI (1 << 4)
  89. #define SPI_INT_MSTI (1 << 5)
  90. /* Bit fields in DMACR */
  91. #define SPI_DMA_RDMAE (1 << 0)
  92. #define SPI_DMA_TDMAE (1 << 1)
  93. #define SPI_WAIT_RETRIES 5
  94. #define SPI_BUF_SIZE \
  95. (sizeof_field(struct spi_mem_op, cmd.opcode) + \
  96. sizeof_field(struct spi_mem_op, addr.val) + 256)
  97. #define SPI_GET_BYTE(_val, _idx) \
  98. ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
  99. enum dw_ssi_type {
  100. SSI_MOTO_SPI = 0,
  101. SSI_TI_SSP,
  102. SSI_NS_MICROWIRE,
  103. };
  104. /* DW SPI capabilities */
  105. #define DW_SPI_CAP_CS_OVERRIDE BIT(0)
  106. #define DW_SPI_CAP_KEEMBAY_MST BIT(1)
  107. #define DW_SPI_CAP_DWC_SSI BIT(2)
  108. /* Slave spi_transfer/spi_mem_op related */
  109. struct dw_spi_cfg {
  110. u8 tmode;
  111. u8 dfs;
  112. u32 ndf;
  113. u32 freq;
  114. };
  115. struct dw_spi;
  116. struct dw_spi_dma_ops {
  117. int (*dma_init)(struct device *dev, struct dw_spi *dws);
  118. void (*dma_exit)(struct dw_spi *dws);
  119. int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
  120. bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
  121. struct spi_transfer *xfer);
  122. int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
  123. void (*dma_stop)(struct dw_spi *dws);
  124. };
  125. struct dw_spi {
  126. struct spi_controller *master;
  127. void __iomem *regs;
  128. unsigned long paddr;
  129. int irq;
  130. u32 fifo_len; /* depth of the FIFO buffer */
  131. u32 max_mem_freq; /* max mem-ops bus freq */
  132. u32 max_freq; /* max bus freq supported */
  133. u32 caps; /* DW SPI capabilities */
  134. u32 reg_io_width; /* DR I/O width in bytes */
  135. u16 bus_num;
  136. u16 num_cs; /* supported slave numbers */
  137. void (*set_cs)(struct spi_device *spi, bool enable);
  138. /* Current message transfer state info */
  139. void *tx;
  140. unsigned int tx_len;
  141. void *rx;
  142. unsigned int rx_len;
  143. u8 buf[SPI_BUF_SIZE];
  144. int dma_mapped;
  145. u8 n_bytes; /* current is a 1/2 bytes op */
  146. irqreturn_t (*transfer_handler)(struct dw_spi *dws);
  147. u32 current_freq; /* frequency in hz */
  148. u32 cur_rx_sample_dly;
  149. u32 def_rx_sample_dly_ns;
  150. /* Custom memory operations */
  151. struct spi_controller_mem_ops mem_ops;
  152. /* DMA info */
  153. struct dma_chan *txchan;
  154. u32 txburst;
  155. struct dma_chan *rxchan;
  156. u32 rxburst;
  157. u32 dma_sg_burst;
  158. unsigned long dma_chan_busy;
  159. dma_addr_t dma_addr; /* phy address of the Data register */
  160. const struct dw_spi_dma_ops *dma_ops;
  161. struct completion dma_completion;
  162. #ifdef CONFIG_DEBUG_FS
  163. struct dentry *debugfs;
  164. struct debugfs_regset32 regset;
  165. #endif
  166. };
  167. static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
  168. {
  169. return __raw_readl(dws->regs + offset);
  170. }
  171. static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
  172. {
  173. __raw_writel(val, dws->regs + offset);
  174. }
  175. static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
  176. {
  177. switch (dws->reg_io_width) {
  178. case 2:
  179. return readw_relaxed(dws->regs + offset);
  180. case 4:
  181. default:
  182. return readl_relaxed(dws->regs + offset);
  183. }
  184. }
  185. static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
  186. {
  187. switch (dws->reg_io_width) {
  188. case 2:
  189. writew_relaxed(val, dws->regs + offset);
  190. break;
  191. case 4:
  192. default:
  193. writel_relaxed(val, dws->regs + offset);
  194. break;
  195. }
  196. }
  197. static inline void spi_enable_chip(struct dw_spi *dws, int enable)
  198. {
  199. dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
  200. }
  201. static inline void spi_set_clk(struct dw_spi *dws, u16 div)
  202. {
  203. dw_writel(dws, DW_SPI_BAUDR, div);
  204. }
  205. /* Disable IRQ bits */
  206. static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
  207. {
  208. u32 new_mask;
  209. new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
  210. dw_writel(dws, DW_SPI_IMR, new_mask);
  211. }
  212. /* Enable IRQ bits */
  213. static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
  214. {
  215. u32 new_mask;
  216. new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
  217. dw_writel(dws, DW_SPI_IMR, new_mask);
  218. }
  219. /*
  220. * This disables the SPI controller, interrupts, clears the interrupts status
  221. * and CS, then re-enables the controller back. Transmit and receive FIFO
  222. * buffers are cleared when the device is disabled.
  223. */
  224. static inline void spi_reset_chip(struct dw_spi *dws)
  225. {
  226. spi_enable_chip(dws, 0);
  227. spi_mask_intr(dws, 0xff);
  228. dw_readl(dws, DW_SPI_ICR);
  229. dw_writel(dws, DW_SPI_SER, 0);
  230. spi_enable_chip(dws, 1);
  231. }
  232. static inline void spi_shutdown_chip(struct dw_spi *dws)
  233. {
  234. spi_enable_chip(dws, 0);
  235. spi_set_clk(dws, 0);
  236. }
  237. extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
  238. extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
  239. struct dw_spi_cfg *cfg);
  240. extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
  241. extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
  242. extern void dw_spi_remove_host(struct dw_spi *dws);
  243. extern int dw_spi_suspend_host(struct dw_spi *dws);
  244. extern int dw_spi_resume_host(struct dw_spi *dws);
  245. #ifdef CONFIG_SPI_DW_DMA
  246. extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
  247. extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
  248. #else
  249. static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
  250. static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
  251. #endif /* !CONFIG_SPI_DW_DMA */
  252. #endif /* DW_SPI_HEADER_H */