spi-dw-quad.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Designware ehance-spi core controller driver
  4. *
  5. * Copyright (c) 2021, alibaba-inc Corporation.
  6. *
  7. * base on design-ware spi-core driver(spi-dw-xxx.c)
  8. */
  9. #include <linux/dma-mapping.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/module.h>
  12. #include <linux/highmem.h>
  13. #include <linux/err.h>
  14. #include <linux/errno.h>
  15. #include <linux/iopoll.h>
  16. #include <linux/delay.h>
  17. #include <linux/slab.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/sizes.h>
  20. #include <linux/spi/spi-mem.h>
  21. #include "spi-dw-quad.h"
  22. #include <linux/of_gpio.h>
  23. #include <linux/gpio/consumer.h>
  24. #ifdef CONFIG_DEBUG_FS
  25. #include <linux/debugfs.h>
  26. #endif
  27. /* Slave spi_dev related */
  28. struct chip_data {
  29. u8 tmode; /* TR/TO/RO/EEPROM */
  30. u8 type; /* SPI/SSP/MicroWire */
  31. u8 poll_mode; /* 1 means use poll mode */
  32. u16 clk_div; /* baud rate divider */
  33. u32 speed_hz; /* baud rate of spi io clk */
  34. void (*cs_control)(u32 command);
  35. };
  36. #ifdef CONFIG_DEBUG_FS
  37. #define SPI_REGS_BUFSIZE 1024
  38. static ssize_t dw_qspi_show_regs(struct file *file, char __user *user_buf,
  39. size_t count, loff_t *ppos)
  40. {
  41. struct dw_spi *dws = file->private_data;
  42. char *buf;
  43. u32 len = 0;
  44. ssize_t ret;
  45. buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  46. if (!buf)
  47. return 0;
  48. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  49. "%s registers:\n", dev_name(&dws->master->dev));
  50. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  51. "=================================\n");
  52. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  53. "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  54. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  55. "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  56. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  57. "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  58. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  59. "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  60. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  61. "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  62. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  63. "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  64. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  65. "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  66. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  67. "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  68. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  69. "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
  70. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  71. "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
  72. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  73. "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
  74. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  75. "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
  76. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  77. "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
  78. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  79. "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
  80. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  81. "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
  82. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  83. "RX_SAMPLE_DELAY: \t0x%08x\n", dw_readl(dws, DW_SPI_RX_SMP_DLY));
  84. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  85. "SPI_CTRL0: \t0x%08x\n", dw_readl(dws, DW_SPI_SPI_CTRLR0));
  86. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  87. "TXD_DRIVE_EDGE: \t0x%08x\n", dw_readl(dws, DW_SPI_TXD_DRV_EDGE));
  88. len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  89. "=================================\n");
  90. ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  91. kfree(buf);
  92. return ret;
  93. }
  94. static const struct file_operations dw_qspi_regs_ops = {
  95. .owner = THIS_MODULE,
  96. .open = simple_open,
  97. .read = dw_qspi_show_regs,
  98. .llseek = default_llseek,
  99. };
  100. static int dw_qspi_debugfs_init(struct dw_spi *dws)
  101. {
  102. char name[32];
  103. snprintf(name, 32, "dw_qspi%d", dws->master->bus_num);
  104. dws->debugfs = debugfs_create_dir(name, NULL);
  105. if (!dws->debugfs)
  106. return -ENOMEM;
  107. debugfs_create_file("registers", S_IFREG | S_IRUGO,
  108. dws->debugfs, (void *)dws, &dw_qspi_regs_ops);
  109. return 0;
  110. }
  111. static void dw_qspi_debugfs_remove(struct dw_spi *dws)
  112. {
  113. debugfs_remove_recursive(dws->debugfs);
  114. }
  115. #else
  116. static inline int dw_qspi_debugfs_init(struct dw_spi *dws)
  117. {
  118. return 0;
  119. }
  120. static inline void dw_qspi_debugfs_remove(struct dw_spi *dws)
  121. {
  122. }
  123. #endif /* CONFIG_DEBUG_FS */
  124. void dw_qspi_set_cs(struct spi_device *spi,struct dw_spi *dws, bool enable)
  125. {
  126. bool enable1 = !enable;
  127. if (dws->slave_cs) {
  128. /*
  129. * Honour the SPI_NO_CS flag and invert the enable line, as
  130. * active low is default for SPI. Execution paths that handle
  131. * polarity inversion in gpiolib (such as device tree) will
  132. * enforce active high using the SPI_CS_HIGH resulting in a
  133. * double inversion through the code above.
  134. */
  135. if (!(spi->mode & SPI_NO_CS)) {
  136. if (dws->slave_cs)
  137. gpiod_set_value_cansleep(dws->slave_cs, enable);
  138. else
  139. gpiod_set_value_cansleep(dws->slave_cs, enable1);
  140. }
  141. /* Some SPI masters need both GPIO CS & slave_select */
  142. if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
  143. spi->controller->set_cs)
  144. spi->controller->set_cs(spi, !enable);
  145. } else if (spi->controller->set_cs) {
  146. spi->controller->set_cs(spi, !enable);
  147. }
  148. }
  149. static void __maybe_unused set_cs(struct spi_device *spi, bool enable)
  150. {
  151. struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
  152. struct chip_data *chip = spi_get_ctldata(spi);
  153. /* Chip select logic is inverted from spi_set_cs() */
  154. if (chip && chip->cs_control)
  155. chip->cs_control(!enable);
  156. if (!enable)
  157. dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
  158. else if (dws->cs_override)
  159. dw_writel(dws, DW_SPI_SER, 0);
  160. }
  161. /* Return the max entries we can fill into tx fifo */
  162. static inline u32 tx_max(struct dw_spi *dws)
  163. {
  164. u32 tx_left, tx_room, rxtx_gap;
  165. tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
  166. tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
  167. /*
  168. * Another concern is about the tx/rx mismatch, we
  169. * though to use (dws->fifo_len - rxflr - txflr) as
  170. * one maximum value for tx, but it doesn't cover the
  171. * data which is out of tx/rx fifo and inside the
  172. * shift registers. So a control from sw point of
  173. * view is taken.
  174. */
  175. rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
  176. / dws->n_bytes;
  177. return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
  178. }
  179. /* Return the max entries we should read out of rx fifo */
  180. static inline u32 rx_max(struct dw_spi *dws)
  181. {
  182. u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
  183. return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
  184. }
  185. static void dw_writer(struct dw_spi *dws)
  186. {
  187. u32 max;
  188. u32 txw = 0;
  189. spin_lock(&dws->buf_lock);
  190. max = tx_max(dws);
  191. while (max--) {
  192. /* Set the tx word if the transfer's original "tx" is not null */
  193. if (dws->tx_end - dws->len) {
  194. if (dws->n_bytes == 1)
  195. txw = *(u8 *)(dws->tx);
  196. else if(dws->n_bytes == 2)
  197. txw = *(u16 *)(dws->tx);
  198. else
  199. txw = *(u32 *)(dws->tx);
  200. }
  201. dw_write_io_reg(dws, DW_SPI_DR, txw);
  202. dws->tx += dws->n_bytes;
  203. }
  204. spin_unlock(&dws->buf_lock);
  205. }
  206. static void dw_reader(struct dw_spi *dws)
  207. {
  208. u32 max;
  209. u32 rxw;
  210. spin_lock(&dws->buf_lock);
  211. max = rx_max(dws);
  212. while (max--) {
  213. rxw = dw_read_io_reg(dws, DW_SPI_DR);
  214. /* Care rx only if the transfer's original "rx" is not null */
  215. if (dws->rx_end - dws->len) {
  216. if (dws->n_bytes == 1)
  217. *(u8 *)(dws->rx) = rxw;
  218. else if(dws->n_bytes ==2)
  219. *(u16 *)(dws->rx) = rxw;
  220. else
  221. *(u32 *)(dws->rx) = rxw;
  222. }
  223. dws->rx += dws->n_bytes;
  224. }
  225. spin_unlock(&dws->buf_lock);
  226. }
  227. static irqreturn_t dw_qspi_irq(int irq, void *dev_id)
  228. {
  229. struct spi_controller *master = dev_id;
  230. struct dw_spi *dws = spi_controller_get_devdata(master);
  231. u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
  232. if (!irq_status)
  233. return IRQ_NONE;
  234. if (!master->cur_msg) {
  235. spi_mask_intr(dws, SPI_INT_TXEI);
  236. return IRQ_HANDLED;
  237. }
  238. return dws->transfer_handler(dws);
  239. }
  240. static void dw_qspi_handle_err(struct spi_controller *master,
  241. struct spi_message *msg)
  242. {
  243. struct dw_spi *dws = spi_controller_get_devdata(master);
  244. if (dws->dma_mapped)
  245. dws->dma_ops->dma_stop(dws);
  246. spi_reset_chip(dws);
  247. }
  248. /* This may be called twice for each spi dev */
  249. static int dw_qspi_setup(struct spi_device *spi)
  250. {
  251. struct dw_spi_chip *chip_info = NULL;
  252. struct chip_data *chip;
  253. /* Only alloc on first setup */
  254. chip = spi_get_ctldata(spi);
  255. if (!chip) {
  256. chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
  257. if (!chip)
  258. return -ENOMEM;
  259. spi_set_ctldata(spi, chip);
  260. }
  261. /*
  262. * Protocol drivers may change the chip settings, so...
  263. * if chip_info exists, use it
  264. */
  265. chip_info = spi->controller_data;
  266. /* chip_info doesn't always exist */
  267. if (chip_info) {
  268. if (chip_info->cs_control)
  269. chip->cs_control = chip_info->cs_control;
  270. chip->poll_mode = chip_info->poll_mode;
  271. chip->type = chip_info->type;
  272. }
  273. /* use both transmit and receive mode by default */
  274. chip->tmode = SPI_TMOD_TR;
  275. return 0;
  276. }
  277. static void dw_qspi_cleanup(struct spi_device *spi)
  278. {
  279. struct chip_data *chip = spi_get_ctldata(spi);
  280. kfree(chip);
  281. spi_set_ctldata(spi, NULL);
  282. }
  283. /* Restart the controller, disable all interrupts, clean rx fifo */
  284. static void qspi_hw_init(struct device *dev, struct dw_spi *dws)
  285. {
  286. spi_reset_chip(dws);
  287. /*
  288. * Try to detect the FIFO depth if not set by interface driver,
  289. * the depth could be from 2 to 256 from HW spec
  290. */
  291. if (!dws->fifo_len) {
  292. u32 fifo;
  293. for (fifo = 1; fifo < 256; fifo++) {
  294. dw_writel(dws, DW_SPI_TXFLTR, fifo);
  295. if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
  296. break;
  297. }
  298. dw_writel(dws, DW_SPI_TXFLTR, 0);
  299. dw_writel(dws,DW_SPI_SER,0x3);
  300. dws->fifo_len = (fifo == 1) ? 0 : fifo;
  301. dev_dbg(dev, "Detected FIFO size: %u uint32 \n", dws->fifo_len);
  302. }
  303. spi_enable_chip(dws,0);
  304. dw_writel(dws, DW_SPI_RX_SMP_DLY, dws->rx_sample_delay);
  305. spi_enable_chip(dws,1);
  306. }
  307. static int dw_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
  308. {
  309. struct dw_spi *dws = spi_controller_get_devdata(mem->spi->master);
  310. /* dw spi's rx and tx have the same fifo depth */
  311. if (op->data.dir == SPI_MEM_DATA_OUT && op->data.nbytes >= ((dws->fifo_len -2)<<2) ) {
  312. op->data.nbytes = ((dws->fifo_len -2)<<2);
  313. }
  314. if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes >= (dws->fifo_len<<2) ) {
  315. op->data.nbytes = (dws->fifo_len<<2);
  316. }
  317. return 0;
  318. }
  319. static int dw_qspi_check_buswidth(struct dw_spi *dws, u8 width)
  320. {
  321. switch (width) {
  322. case 1:
  323. case 2:
  324. case 4:
  325. return 0;
  326. }
  327. return -ENOTSUPP;
  328. }
  329. static bool dw_qspi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
  330. {
  331. struct dw_spi *dws = spi_controller_get_devdata(mem->spi->master);
  332. int ret=0;
  333. u32 temp_len;
  334. /* check buswidth */
  335. if(op->cmd.buswidth!=1 || \
  336. (op->addr.nbytes && op->addr.buswidth !=1) || \
  337. ( op->dummy.nbytes && op->dummy.buswidth !=1))
  338. {
  339. return false;
  340. }
  341. if (op->data.nbytes)
  342. ret |= dw_qspi_check_buswidth(dws, op->data.buswidth);
  343. if (ret){
  344. return false;
  345. }
  346. /* check addr bits length */
  347. temp_len = op->addr.nbytes << 3;
  348. if(op->data.nbytes && op->data.buswidth > 4 && temp_len > 60 ){
  349. return false;
  350. }
  351. return true;
  352. }
  353. static int dw_qspi_readl_poll_time_out(struct dw_spi *dws,u32 delay_us, u32 timeout_us)
  354. {
  355. u32 val;
  356. void __iomem *reg = dws->regs + DW_SPI_SR;
  357. return readl_poll_timeout(reg,val,!(val & SR_BUSY),delay_us,timeout_us);
  358. }
  359. static void dw_qspi_build_xfer_pre_portion(struct dw_spi *dws,const struct spi_mem_op *op)
  360. {
  361. u32 i = 0,j=0;
  362. /* operation code */
  363. dws->xfer_data_pre.xfer_pre[i++]= op->cmd.opcode;
  364. /* addr */
  365. if(op->addr.nbytes){
  366. for(j=0; j < op->addr.nbytes; j++)
  367. {
  368. dws->xfer_data_pre.xfer_pre[i++] = (op->addr.val >> (8 *(op->addr.nbytes -j -1))) & 0xFF;
  369. }
  370. }
  371. /* dummy */
  372. if(op->dummy.nbytes){
  373. memset(&dws->xfer_data_pre.xfer_pre[i],0xFF,op->dummy.nbytes);
  374. i += op->dummy.nbytes;
  375. }
  376. dws->xfer_data_pre.xfer_pre_len = i;
  377. return;
  378. }
  379. static bool dw_qspi_can_xfer_32bits_frame(const struct spi_mem_op *op)
  380. {
  381. bool ret = false;
  382. if(op->data.buswidth > 1 && op->data.nbytes && !(op->data.nbytes & 0x3) && !(op->data.nbytes & 0x3)){
  383. if(op->data.dir == SPI_MEM_DATA_OUT && !((unsigned long)(op->data.buf.out) & 0x03) )
  384. {
  385. ret = true;
  386. }
  387. else if(op->data.dir == SPI_MEM_DATA_IN && !((unsigned long)(op->data.buf.in) & 0x03) ){
  388. ret = true;
  389. }
  390. }
  391. return ret;
  392. }
  393. static int dw_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
  394. {
  395. struct dw_spi *dws = spi_controller_get_devdata(mem->spi->master);
  396. struct spi_device *spi = mem->spi;
  397. struct chip_data *chip = spi_get_ctldata(mem->spi);
  398. int ret=0;
  399. u32 cr0=0,spi_cr0=0;
  400. u32 rx_len;
  401. u32 addr_bits_len, dummy_bits_len;
  402. /* wait for the controller being ready */
  403. ret = dw_qspi_readl_poll_time_out(dws,10,1000*1000);
  404. if(ret){
  405. dev_err(&dws->master->dev, "time out during waiting for spi-core idle\n");
  406. return ret;
  407. }
  408. /*disable spi core */
  409. spi_enable_chip(dws,0);
  410. if(op->data.dir == SPI_MEM_DATA_OUT) {
  411. spi_disable_slave(dws,0);
  412. }else {
  413. spi_enable_slave(dws,0);
  414. }
  415. /* config clk rate, div = 8 */
  416. //printk("dws->max_freq = %d spi->max_speed_hz %d \n",dws->max_freq,spi->max_speed_hz);
  417. chip->clk_div = (DIV_ROUND_UP(dws->max_freq,spi->max_speed_hz)+1) & 0xfffe;
  418. chip->speed_hz = dws->current_freq = spi->max_speed_hz;
  419. spi_set_clk(dws,chip->clk_div);
  420. /* build pre-xfer data portion*/
  421. dw_qspi_build_xfer_pre_portion(dws,op);
  422. /*
  423. * default cr0 register setting
  424. * SSI_TYPE-----> SPI_FRF_SPI
  425. * CPOL&CPHA----> SPI_CPOL=SPI_CPHA = 0
  426. * FRAME_SIZE---> 8bits
  427. * SPI_TMOD_OFFSET SPI_TMOD_TO
  428. */
  429. cr0 = (chip->type << SPI_FRF_OFFSET) | \
  430. (((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) | \
  431. (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) | \
  432. (chip->tmode << SPI_TMOD_OFFSET) | \
  433. ((8-1) << SPI_DFS32_OFFSET) ;
  434. chip->tmode = SPI_TMOD_TO;
  435. if(op->data.dir == SPI_MEM_NO_DATA || op->data.dir == SPI_MEM_DATA_OUT){
  436. chip->tmode = SPI_TMOD_TO;
  437. }
  438. else if(op->data.dir == SPI_MEM_DATA_IN && op->data.buswidth > 1){
  439. chip->tmode = SPI_TMOD_RO;
  440. rx_len = op->data.nbytes;
  441. if(dw_qspi_can_xfer_32bits_frame(op)){
  442. rx_len >>=2;
  443. }
  444. dw_writel(dws,DW_SPI_CTRL1,rx_len -1);
  445. }
  446. cr0 &=~SPI_TMOD_MASK;
  447. cr0 |=(chip->tmode << SPI_TMOD_OFFSET);
  448. /* init config spi_cr0 if use non-standard spi mode */
  449. if(op->data.buswidth > 1){
  450. /*
  451. * trans_type = both instruction and address are sent in standard mode
  452. * instruction bits length is 8bits
  453. *
  454. */
  455. spi_cr0 = (SPI_CTRLR0_TRANS_ISTD_ASTD << SPI_CTRLR0_TRNAS_OFFET) | \
  456. (SPI_CTRLR0_INST_L_8 << SPI_CTRLR0_INST_L_OFFSET);
  457. addr_bits_len = (op->addr.nbytes << 3)>>2;
  458. dummy_bits_len = op->dummy.nbytes << 3;
  459. spi_cr0 |= (addr_bits_len << SPI_CTRLR0_ADDR_L_OFFSET);
  460. spi_cr0 |= (dummy_bits_len << SPI_CTRLR0_WAIT_CYCLES_OFFSET);
  461. dw_writel(dws,DW_SPI_SPI_CTRLR0,spi_cr0);
  462. /* update SPI_SPI_FRF */
  463. cr0 &=~ SPI_SPI_FRF_MASK;
  464. switch(op->data.buswidth){
  465. case 2:
  466. cr0 |= (SPI_SPI_FRF_DUAL << SPI_SPI_FRF_OFFSET);
  467. break;
  468. case 4:
  469. cr0 |= (SPI_SPI_FRF_QUAD << SPI_SPI_FRF_OFFSET);
  470. default:
  471. break;
  472. }
  473. }
  474. /*check whether can xfer through 32bit-frame size, then update cr0 */
  475. if(dw_qspi_can_xfer_32bits_frame(op)){
  476. cr0 &=~SPI_DFS32_MASK;
  477. cr0 |= ((32-1) << SPI_DFS32_OFFSET );
  478. }
  479. dw_writel(dws,DW_SPI_CTRL0,cr0);
  480. /* for poll mode just disable all interrupts */
  481. spi_mask_intr(dws,0xff);
  482. /* dma mode */
  483. #if 0
  484. if (dws->dma_mapped) {
  485. ret = dws->dma_setup(dws, &dws->xfer_data_pre,op);
  486. if (ret < 0) {
  487. spi_enable_chip(dws, 1);
  488. return ret;
  489. }
  490. }
  491. #endif
  492. /* transfer data_pre portion(cmd+addr+dummy) */
  493. dw_qspi_set_cs(mem->spi,dws,true);
  494. spi_enable_chip(dws,1);
  495. /* pre portion is sent with spi-standard mode and data-frame size is 8bit frame */
  496. dws->n_bytes = 1;
  497. if(op->data.nbytes && op->data.buswidth > 1)
  498. {
  499. /*!!!note: in quad mode, dw-ssi can't be interrupt during sending pre portion and data portion
  500. * otherwise, the timing won't be expected
  501. */
  502. dw_writel(dws,DW_SPI_DR,op->cmd.opcode);
  503. if(op->addr.nbytes){
  504. dw_writel(dws,DW_SPI_DR,op->addr.val);
  505. }
  506. }
  507. else
  508. {
  509. dws->tx = (void *)dws->xfer_data_pre.xfer_pre;
  510. dws->tx_end = dws->tx + dws->xfer_data_pre.xfer_pre_len;
  511. dws->len = dws->xfer_data_pre.xfer_pre_len;
  512. do{
  513. dw_writer(dws);
  514. }while(dws->tx_end > dws->tx);
  515. }
  516. /* transfer data portion if needs */
  517. if(op->data.dir == SPI_MEM_DATA_OUT){
  518. dws->tx =(void*) op->data.buf.out;
  519. dws->tx_end = dws->tx + op->data.nbytes;
  520. dws->len = op->data.nbytes;
  521. if(dw_qspi_can_xfer_32bits_frame(op)){
  522. dws->n_bytes = 4;
  523. }
  524. do{
  525. dw_writer(dws);
  526. }while(dws->tx_end > dws->tx);
  527. if(op->data.nbytes && op->data.buswidth > 1){
  528. //local_irq_restore(flag);
  529. }
  530. spi_enable_slave(dws,0);
  531. }
  532. else if (op->data.dir == SPI_MEM_DATA_IN)
  533. {
  534. /* if data portion use standard mode,pre transfer mode is tx, need set rx mode */
  535. if(op->data.buswidth == 1){
  536. while(dw_readl(dws,DW_SPI_SR) & SR_BUSY){
  537. cpu_relax();
  538. }
  539. spi_enable_chip(dws,0);
  540. cr0 = dw_readl(dws,DW_SPI_CTRL0);
  541. cr0 &=~SPI_TMOD_MASK;
  542. cr0 |= (SPI_TMOD_RO << SPI_TMOD_OFFSET);
  543. dw_writel(dws,DW_SPI_CTRL0,cr0);
  544. dw_writel(dws,DW_SPI_CTRL1,op->data.nbytes -1);
  545. spi_enable_chip(dws,1);
  546. dw_write_io_reg(dws,DW_SPI_DR,0);
  547. dws->rx = op->data.buf.in;
  548. dws->rx_end = dws->rx + op->data.nbytes;
  549. dws->len = op->data.nbytes;
  550. do{
  551. dw_reader(dws);
  552. //cpu_relax();
  553. }while(dws->rx_end > dws->rx);
  554. }
  555. /* non-standard mode */
  556. else {
  557. dws->rx = op->data.buf.in;
  558. dws->rx_end = dws->rx + op->data.nbytes;
  559. dws->len = op->data.nbytes;
  560. if(dw_qspi_can_xfer_32bits_frame(op)) {
  561. dws->n_bytes = 4;
  562. }
  563. do {
  564. dw_reader(dws);
  565. }while(dws->rx_end > dws->rx);
  566. if(op->data.nbytes && op->data.buswidth > 1) {
  567. //local_irq_restore(flag);
  568. }
  569. }
  570. }
  571. while(dw_readl(dws,DW_SPI_SR) & SR_BUSY) {
  572. cpu_relax();
  573. }
  574. if(dw_readl(dws,DW_SPI_RISR) &(SPI_INT_RXOI|SPI_INT_RXUI) ) {
  575. printk("###rx err %02x \n",dw_readl(dws,DW_SPI_RISR));
  576. }
  577. dw_qspi_set_cs(mem->spi,dws,false);
  578. return 0;
  579. }
  580. static const struct spi_controller_mem_ops dw_qspi_mem_ops = {
  581. .adjust_op_size = dw_qspi_adjust_op_size,
  582. .supports_op = dw_qspi_supports_op,
  583. .exec_op = dw_qspi_exec_op,
  584. .get_name = NULL,/*dw_qspi_get_name,*/
  585. };
  586. int dw_qspi_add_host(struct device *dev, struct dw_spi *dws)
  587. {
  588. struct spi_controller *master;
  589. int ret;
  590. BUG_ON(dws == NULL);
  591. /* allocate master */
  592. master = spi_alloc_master(dev, 0);
  593. if (!master)
  594. return -ENOMEM;
  595. dws->master = master;
  596. dws->type = SSI_MOTO_SPI;
  597. dws->dma_inited = 0;
  598. dws->reg_io_width = 4;
  599. dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
  600. spin_lock_init(&dws->buf_lock);
  601. /* save device data */
  602. spi_controller_set_devdata(master, dws);
  603. /* register interrupt call-back */
  604. ret = request_irq(dws->irq, dw_qspi_irq, IRQF_SHARED, dev_name(dev),
  605. master);
  606. if (ret < 0) {
  607. dev_err(dev, "can not get IRQ\n");
  608. goto err_free_master;
  609. }
  610. master->mode_bits = SPI_CPOL |\
  611. SPI_CPHA |\
  612. SPI_RX_DUAL |\
  613. SPI_RX_QUAD | \
  614. SPI_TX_DUAL| \
  615. SPI_TX_QUAD;
  616. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
  617. master->bus_num = dws->bus_num;
  618. master->num_chipselect = dws->num_cs;
  619. master->setup = dw_qspi_setup;
  620. master->cleanup = dw_qspi_cleanup;
  621. master->handle_err = dw_qspi_handle_err;
  622. master->max_speed_hz = dws->max_freq;
  623. master->dev.of_node = dev->of_node;
  624. master->dev.fwnode = dev->fwnode;
  625. if (dws->set_cs)
  626. master->set_cs = dws->set_cs;
  627. /* Basic HW init */
  628. qspi_hw_init(dev, dws);
  629. if (dws->dma_ops && dws->dma_ops->dma_init) {
  630. ret = dws->dma_ops->dma_init(dws);
  631. if (ret) {
  632. dev_warn(dev, "DMA init failed\n");
  633. dws->dma_inited = 0;
  634. } else {
  635. master->can_dma = dws->dma_ops->can_dma;
  636. }
  637. }
  638. /* set qspi-mem ops table */
  639. master->mem_ops = &dw_qspi_mem_ops;
  640. /* regist master controler */
  641. ret = devm_spi_register_controller(dev, master);
  642. if (ret) {
  643. dev_err(&master->dev, "problem registering spi master\n");
  644. goto err_dma_exit;
  645. }
  646. /* init debugfs feature */
  647. dw_qspi_debugfs_init(dws);
  648. return 0;
  649. err_dma_exit:
  650. if (dws->dma_ops && dws->dma_ops->dma_exit)
  651. dws->dma_ops->dma_exit(dws);
  652. spi_enable_chip(dws, 0);
  653. free_irq(dws->irq, master);
  654. err_free_master:
  655. spi_controller_put(master);
  656. return ret;
  657. }
  658. EXPORT_SYMBOL_GPL(dw_qspi_add_host);
  659. void dw_qspi_remove_host(struct dw_spi *dws)
  660. {
  661. dw_qspi_debugfs_remove(dws);
  662. if (dws->dma_ops && dws->dma_ops->dma_exit)
  663. dws->dma_ops->dma_exit(dws);
  664. spi_shutdown_chip(dws);
  665. free_irq(dws->irq, dws->master);
  666. }
  667. EXPORT_SYMBOL_GPL(dw_qspi_remove_host);
  668. int dw_qspi_suspend_host(struct dw_spi *dws)
  669. {
  670. int ret;
  671. ret = spi_controller_suspend(dws->master);
  672. if (ret)
  673. return ret;
  674. spi_shutdown_chip(dws);
  675. return 0;
  676. }
  677. EXPORT_SYMBOL_GPL(dw_qspi_suspend_host);
  678. int dw_qspi_resume_host(struct dw_spi *dws)
  679. {
  680. qspi_hw_init(&dws->master->dev, dws);
  681. return spi_controller_resume(dws->master);
  682. }
  683. EXPORT_SYMBOL_GPL(dw_qspi_resume_host);
  684. MODULE_AUTHOR("linghui zeng<linghui.zlh@linux.alibaba.com>");
  685. MODULE_DESCRIPTION("Driver for DesignWare ehance-spi controller core");
  686. MODULE_LICENSE("GPL v2");