spi-dw-dma.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Special handling for DW DMA core
  4. *
  5. * Copyright (c) 2009, 2014 Intel Corporation.
  6. */
  7. #include <linux/completion.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/dmaengine.h>
  10. #include <linux/irqreturn.h>
  11. #include <linux/jiffies.h>
  12. #include <linux/pci.h>
  13. #include <linux/platform_data/dma-dw.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/types.h>
  16. #include "spi-dw.h"
  17. #define RX_BUSY 0
  18. #define RX_BURST_LEVEL 16
  19. #define TX_BUSY 1
  20. #define TX_BURST_LEVEL 16
  21. static bool dw_spi_dma_chan_filter(struct dma_chan *chan, void *param)
  22. {
  23. struct dw_dma_slave *s = param;
  24. if (s->dma_dev != chan->device->dev)
  25. return false;
  26. chan->private = s;
  27. return true;
  28. }
  29. static void dw_spi_dma_maxburst_init(struct dw_spi *dws)
  30. {
  31. struct dma_slave_caps caps;
  32. u32 max_burst, def_burst;
  33. int ret;
  34. def_burst = dws->fifo_len / 2;
  35. ret = dma_get_slave_caps(dws->rxchan, &caps);
  36. if (!ret && caps.max_burst)
  37. max_burst = caps.max_burst;
  38. else
  39. max_burst = RX_BURST_LEVEL;
  40. dws->rxburst = min(max_burst, def_burst);
  41. dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
  42. ret = dma_get_slave_caps(dws->txchan, &caps);
  43. if (!ret && caps.max_burst)
  44. max_burst = caps.max_burst;
  45. else
  46. max_burst = TX_BURST_LEVEL;
  47. /*
  48. * Having a Rx DMA channel serviced with higher priority than a Tx DMA
  49. * channel might not be enough to provide a well balanced DMA-based
  50. * SPI transfer interface. There might still be moments when the Tx DMA
  51. * channel is occasionally handled faster than the Rx DMA channel.
  52. * That in its turn will eventually cause the SPI Rx FIFO overflow if
  53. * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's
  54. * cleared by the Rx DMA channel. In order to fix the problem the Tx
  55. * DMA activity is intentionally slowed down by limiting the SPI Tx
  56. * FIFO depth with a value twice bigger than the Tx burst length.
  57. */
  58. dws->txburst = min(max_burst, def_burst);
  59. dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);
  60. }
  61. static void dw_spi_dma_sg_burst_init(struct dw_spi *dws)
  62. {
  63. struct dma_slave_caps tx = {0}, rx = {0};
  64. dma_get_slave_caps(dws->txchan, &tx);
  65. dma_get_slave_caps(dws->rxchan, &rx);
  66. if (tx.max_sg_burst > 0 && rx.max_sg_burst > 0)
  67. dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst);
  68. else if (tx.max_sg_burst > 0)
  69. dws->dma_sg_burst = tx.max_sg_burst;
  70. else if (rx.max_sg_burst > 0)
  71. dws->dma_sg_burst = rx.max_sg_burst;
  72. else
  73. dws->dma_sg_burst = 0;
  74. }
  75. static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
  76. {
  77. struct dw_dma_slave dma_tx = { .dst_id = 1 }, *tx = &dma_tx;
  78. struct dw_dma_slave dma_rx = { .src_id = 0 }, *rx = &dma_rx;
  79. struct pci_dev *dma_dev;
  80. dma_cap_mask_t mask;
  81. /*
  82. * Get pci device for DMA controller, currently it could only
  83. * be the DMA controller of Medfield
  84. */
  85. dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
  86. if (!dma_dev)
  87. return -ENODEV;
  88. dma_cap_zero(mask);
  89. dma_cap_set(DMA_SLAVE, mask);
  90. /* 1. Init rx channel */
  91. rx->dma_dev = &dma_dev->dev;
  92. dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx);
  93. if (!dws->rxchan)
  94. goto err_exit;
  95. /* 2. Init tx channel */
  96. tx->dma_dev = &dma_dev->dev;
  97. dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx);
  98. if (!dws->txchan)
  99. goto free_rxchan;
  100. dws->master->dma_rx = dws->rxchan;
  101. dws->master->dma_tx = dws->txchan;
  102. init_completion(&dws->dma_completion);
  103. dw_spi_dma_maxburst_init(dws);
  104. dw_spi_dma_sg_burst_init(dws);
  105. return 0;
  106. free_rxchan:
  107. dma_release_channel(dws->rxchan);
  108. dws->rxchan = NULL;
  109. err_exit:
  110. return -EBUSY;
  111. }
  112. static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
  113. {
  114. dws->rxchan = dma_request_slave_channel(dev, "rx");
  115. if (!dws->rxchan)
  116. return -ENODEV;
  117. dws->txchan = dma_request_slave_channel(dev, "tx");
  118. if (!dws->txchan) {
  119. dma_release_channel(dws->rxchan);
  120. dws->rxchan = NULL;
  121. return -ENODEV;
  122. }
  123. dws->master->dma_rx = dws->rxchan;
  124. dws->master->dma_tx = dws->txchan;
  125. init_completion(&dws->dma_completion);
  126. dw_spi_dma_maxburst_init(dws);
  127. dw_spi_dma_sg_burst_init(dws);
  128. return 0;
  129. }
  130. static void dw_spi_dma_exit(struct dw_spi *dws)
  131. {
  132. if (dws->txchan) {
  133. dmaengine_terminate_sync(dws->txchan);
  134. dma_release_channel(dws->txchan);
  135. }
  136. if (dws->rxchan) {
  137. dmaengine_terminate_sync(dws->rxchan);
  138. dma_release_channel(dws->rxchan);
  139. }
  140. }
  141. static irqreturn_t dw_spi_dma_transfer_handler(struct dw_spi *dws)
  142. {
  143. dw_spi_check_status(dws, false);
  144. complete(&dws->dma_completion);
  145. return IRQ_HANDLED;
  146. }
  147. static bool dw_spi_can_dma(struct spi_controller *master,
  148. struct spi_device *spi, struct spi_transfer *xfer)
  149. {
  150. struct dw_spi *dws = spi_controller_get_devdata(master);
  151. return xfer->len > dws->fifo_len;
  152. }
  153. static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
  154. {
  155. if (n_bytes == 1)
  156. return DMA_SLAVE_BUSWIDTH_1_BYTE;
  157. else if (n_bytes == 2)
  158. return DMA_SLAVE_BUSWIDTH_2_BYTES;
  159. return DMA_SLAVE_BUSWIDTH_UNDEFINED;
  160. }
  161. static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed)
  162. {
  163. unsigned long long ms;
  164. ms = len * MSEC_PER_SEC * BITS_PER_BYTE;
  165. do_div(ms, speed);
  166. ms += ms + 200;
  167. if (ms > UINT_MAX)
  168. ms = UINT_MAX;
  169. ms = wait_for_completion_timeout(&dws->dma_completion,
  170. msecs_to_jiffies(ms));
  171. if (ms == 0) {
  172. dev_err(&dws->master->cur_msg->spi->dev,
  173. "DMA transaction timed out\n");
  174. return -ETIMEDOUT;
  175. }
  176. return 0;
  177. }
  178. static inline bool dw_spi_dma_tx_busy(struct dw_spi *dws)
  179. {
  180. return !(dw_readl(dws, DW_SPI_SR) & SR_TF_EMPT);
  181. }
  182. static int dw_spi_dma_wait_tx_done(struct dw_spi *dws,
  183. struct spi_transfer *xfer)
  184. {
  185. int retry = SPI_WAIT_RETRIES;
  186. struct spi_delay delay;
  187. u32 nents;
  188. nents = dw_readl(dws, DW_SPI_TXFLR);
  189. delay.unit = SPI_DELAY_UNIT_SCK;
  190. delay.value = nents * dws->n_bytes * BITS_PER_BYTE;
  191. while (dw_spi_dma_tx_busy(dws) && retry--)
  192. spi_delay_exec(&delay, xfer);
  193. if (retry < 0) {
  194. dev_err(&dws->master->dev, "Tx hanged up\n");
  195. return -EIO;
  196. }
  197. return 0;
  198. }
  199. /*
  200. * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
  201. * channel will clear a corresponding bit.
  202. */
  203. static void dw_spi_dma_tx_done(void *arg)
  204. {
  205. struct dw_spi *dws = arg;
  206. clear_bit(TX_BUSY, &dws->dma_chan_busy);
  207. if (test_bit(RX_BUSY, &dws->dma_chan_busy))
  208. return;
  209. complete(&dws->dma_completion);
  210. }
  211. static int dw_spi_dma_config_tx(struct dw_spi *dws)
  212. {
  213. struct dma_slave_config txconf;
  214. memset(&txconf, 0, sizeof(txconf));
  215. txconf.direction = DMA_MEM_TO_DEV;
  216. txconf.dst_addr = dws->dma_addr;
  217. txconf.dst_maxburst = dws->txburst;
  218. txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  219. txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
  220. txconf.device_fc = false;
  221. return dmaengine_slave_config(dws->txchan, &txconf);
  222. }
  223. static int dw_spi_dma_submit_tx(struct dw_spi *dws, struct scatterlist *sgl,
  224. unsigned int nents)
  225. {
  226. struct dma_async_tx_descriptor *txdesc;
  227. dma_cookie_t cookie;
  228. int ret;
  229. txdesc = dmaengine_prep_slave_sg(dws->txchan, sgl, nents,
  230. DMA_MEM_TO_DEV,
  231. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  232. if (!txdesc)
  233. return -ENOMEM;
  234. txdesc->callback = dw_spi_dma_tx_done;
  235. txdesc->callback_param = dws;
  236. cookie = dmaengine_submit(txdesc);
  237. ret = dma_submit_error(cookie);
  238. if (ret) {
  239. dmaengine_terminate_sync(dws->txchan);
  240. return ret;
  241. }
  242. set_bit(TX_BUSY, &dws->dma_chan_busy);
  243. return 0;
  244. }
  245. static inline bool dw_spi_dma_rx_busy(struct dw_spi *dws)
  246. {
  247. return !!(dw_readl(dws, DW_SPI_SR) & SR_RF_NOT_EMPT);
  248. }
  249. static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
  250. {
  251. int retry = SPI_WAIT_RETRIES;
  252. struct spi_delay delay;
  253. unsigned long ns, us;
  254. u32 nents;
  255. /*
  256. * It's unlikely that DMA engine is still doing the data fetching, but
  257. * if it's let's give it some reasonable time. The timeout calculation
  258. * is based on the synchronous APB/SSI reference clock rate, on a
  259. * number of data entries left in the Rx FIFO, times a number of clock
  260. * periods normally needed for a single APB read/write transaction
  261. * without PREADY signal utilized (which is true for the DW APB SSI
  262. * controller).
  263. */
  264. nents = dw_readl(dws, DW_SPI_RXFLR);
  265. ns = 4U * NSEC_PER_SEC / dws->max_freq * nents;
  266. if (ns <= NSEC_PER_USEC) {
  267. delay.unit = SPI_DELAY_UNIT_NSECS;
  268. delay.value = ns;
  269. } else {
  270. us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
  271. delay.unit = SPI_DELAY_UNIT_USECS;
  272. delay.value = clamp_val(us, 0, USHRT_MAX);
  273. }
  274. while (dw_spi_dma_rx_busy(dws) && retry--)
  275. spi_delay_exec(&delay, NULL);
  276. if (retry < 0) {
  277. dev_err(&dws->master->dev, "Rx hanged up\n");
  278. return -EIO;
  279. }
  280. return 0;
  281. }
  282. /*
  283. * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
  284. * channel will clear a corresponding bit.
  285. */
  286. static void dw_spi_dma_rx_done(void *arg)
  287. {
  288. struct dw_spi *dws = arg;
  289. clear_bit(RX_BUSY, &dws->dma_chan_busy);
  290. if (test_bit(TX_BUSY, &dws->dma_chan_busy))
  291. return;
  292. complete(&dws->dma_completion);
  293. }
  294. static int dw_spi_dma_config_rx(struct dw_spi *dws)
  295. {
  296. struct dma_slave_config rxconf;
  297. memset(&rxconf, 0, sizeof(rxconf));
  298. rxconf.direction = DMA_DEV_TO_MEM;
  299. rxconf.src_addr = dws->dma_addr;
  300. rxconf.src_maxburst = dws->rxburst;
  301. rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  302. rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
  303. rxconf.device_fc = false;
  304. return dmaengine_slave_config(dws->rxchan, &rxconf);
  305. }
  306. static int dw_spi_dma_submit_rx(struct dw_spi *dws, struct scatterlist *sgl,
  307. unsigned int nents)
  308. {
  309. struct dma_async_tx_descriptor *rxdesc;
  310. dma_cookie_t cookie;
  311. int ret;
  312. rxdesc = dmaengine_prep_slave_sg(dws->rxchan, sgl, nents,
  313. DMA_DEV_TO_MEM,
  314. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  315. if (!rxdesc)
  316. return -ENOMEM;
  317. rxdesc->callback = dw_spi_dma_rx_done;
  318. rxdesc->callback_param = dws;
  319. cookie = dmaengine_submit(rxdesc);
  320. ret = dma_submit_error(cookie);
  321. if (ret) {
  322. dmaengine_terminate_sync(dws->rxchan);
  323. return ret;
  324. }
  325. set_bit(RX_BUSY, &dws->dma_chan_busy);
  326. return 0;
  327. }
  328. static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
  329. {
  330. u16 imr, dma_ctrl;
  331. int ret;
  332. if (!xfer->tx_buf)
  333. return -EINVAL;
  334. /* Setup DMA channels */
  335. ret = dw_spi_dma_config_tx(dws);
  336. if (ret)
  337. return ret;
  338. if (xfer->rx_buf) {
  339. ret = dw_spi_dma_config_rx(dws);
  340. if (ret)
  341. return ret;
  342. }
  343. /* Set the DMA handshaking interface */
  344. dma_ctrl = SPI_DMA_TDMAE;
  345. if (xfer->rx_buf)
  346. dma_ctrl |= SPI_DMA_RDMAE;
  347. dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
  348. /* Set the interrupt mask */
  349. imr = SPI_INT_TXOI;
  350. if (xfer->rx_buf)
  351. imr |= SPI_INT_RXUI | SPI_INT_RXOI;
  352. spi_umask_intr(dws, imr);
  353. reinit_completion(&dws->dma_completion);
  354. dws->transfer_handler = dw_spi_dma_transfer_handler;
  355. return 0;
  356. }
  357. static int dw_spi_dma_transfer_all(struct dw_spi *dws,
  358. struct spi_transfer *xfer)
  359. {
  360. int ret;
  361. /* Submit the DMA Tx transfer */
  362. ret = dw_spi_dma_submit_tx(dws, xfer->tx_sg.sgl, xfer->tx_sg.nents);
  363. if (ret)
  364. goto err_clear_dmac;
  365. /* Submit the DMA Rx transfer if required */
  366. if (xfer->rx_buf) {
  367. ret = dw_spi_dma_submit_rx(dws, xfer->rx_sg.sgl,
  368. xfer->rx_sg.nents);
  369. if (ret)
  370. goto err_clear_dmac;
  371. /* rx must be started before tx due to spi instinct */
  372. dma_async_issue_pending(dws->rxchan);
  373. }
  374. dma_async_issue_pending(dws->txchan);
  375. ret = dw_spi_dma_wait(dws, xfer->len, xfer->effective_speed_hz);
  376. err_clear_dmac:
  377. dw_writel(dws, DW_SPI_DMACR, 0);
  378. return ret;
  379. }
  380. /*
  381. * In case if at least one of the requested DMA channels doesn't support the
  382. * hardware accelerated SG list entries traverse, the DMA driver will most
  383. * likely work that around by performing the IRQ-based SG list entries
  384. * resubmission. That might and will cause a problem if the DMA Tx channel is
  385. * recharged and re-executed before the Rx DMA channel. Due to
  386. * non-deterministic IRQ-handler execution latency the DMA Tx channel will
  387. * start pushing data to the SPI bus before the Rx DMA channel is even
  388. * reinitialized with the next inbound SG list entry. By doing so the DMA Tx
  389. * channel will implicitly start filling the DW APB SSI Rx FIFO up, which while
  390. * the DMA Rx channel being recharged and re-executed will eventually be
  391. * overflown.
  392. *
  393. * In order to solve the problem we have to feed the DMA engine with SG list
  394. * entries one-by-one. It shall keep the DW APB SSI Tx and Rx FIFOs
  395. * synchronized and prevent the Rx FIFO overflow. Since in general the tx_sg
  396. * and rx_sg lists may have different number of entries of different lengths
  397. * (though total length should match) let's virtually split the SG-lists to the
  398. * set of DMA transfers, which length is a minimum of the ordered SG-entries
  399. * lengths. An ASCII-sketch of the implemented algo is following:
  400. * xfer->len
  401. * |___________|
  402. * tx_sg list: |___|____|__|
  403. * rx_sg list: |_|____|____|
  404. * DMA transfers: |_|_|__|_|__|
  405. *
  406. * Note in order to have this workaround solving the denoted problem the DMA
  407. * engine driver should properly initialize the max_sg_burst capability and set
  408. * the DMA device max segment size parameter with maximum data block size the
  409. * DMA engine supports.
  410. */
  411. static int dw_spi_dma_transfer_one(struct dw_spi *dws,
  412. struct spi_transfer *xfer)
  413. {
  414. struct scatterlist *tx_sg = NULL, *rx_sg = NULL, tx_tmp, rx_tmp;
  415. unsigned int tx_len = 0, rx_len = 0;
  416. unsigned int base, len;
  417. int ret;
  418. sg_init_table(&tx_tmp, 1);
  419. sg_init_table(&rx_tmp, 1);
  420. for (base = 0, len = 0; base < xfer->len; base += len) {
  421. /* Fetch next Tx DMA data chunk */
  422. if (!tx_len) {
  423. tx_sg = !tx_sg ? &xfer->tx_sg.sgl[0] : sg_next(tx_sg);
  424. sg_dma_address(&tx_tmp) = sg_dma_address(tx_sg);
  425. tx_len = sg_dma_len(tx_sg);
  426. }
  427. /* Fetch next Rx DMA data chunk */
  428. if (!rx_len) {
  429. rx_sg = !rx_sg ? &xfer->rx_sg.sgl[0] : sg_next(rx_sg);
  430. sg_dma_address(&rx_tmp) = sg_dma_address(rx_sg);
  431. rx_len = sg_dma_len(rx_sg);
  432. }
  433. len = min(tx_len, rx_len);
  434. sg_dma_len(&tx_tmp) = len;
  435. sg_dma_len(&rx_tmp) = len;
  436. /* Submit DMA Tx transfer */
  437. ret = dw_spi_dma_submit_tx(dws, &tx_tmp, 1);
  438. if (ret)
  439. break;
  440. /* Submit DMA Rx transfer */
  441. ret = dw_spi_dma_submit_rx(dws, &rx_tmp, 1);
  442. if (ret)
  443. break;
  444. /* Rx must be started before Tx due to SPI instinct */
  445. dma_async_issue_pending(dws->rxchan);
  446. dma_async_issue_pending(dws->txchan);
  447. /*
  448. * Here we only need to wait for the DMA transfer to be
  449. * finished since SPI controller is kept enabled during the
  450. * procedure this loop implements and there is no risk to lose
  451. * data left in the Tx/Rx FIFOs.
  452. */
  453. ret = dw_spi_dma_wait(dws, len, xfer->effective_speed_hz);
  454. if (ret)
  455. break;
  456. reinit_completion(&dws->dma_completion);
  457. sg_dma_address(&tx_tmp) += len;
  458. sg_dma_address(&rx_tmp) += len;
  459. tx_len -= len;
  460. rx_len -= len;
  461. }
  462. dw_writel(dws, DW_SPI_DMACR, 0);
  463. return ret;
  464. }
  465. static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
  466. {
  467. unsigned int nents;
  468. int ret;
  469. nents = max(xfer->tx_sg.nents, xfer->rx_sg.nents);
  470. /*
  471. * Execute normal DMA-based transfer (which submits the Rx and Tx SG
  472. * lists directly to the DMA engine at once) if either full hardware
  473. * accelerated SG list traverse is supported by both channels, or the
  474. * Tx-only SPI transfer is requested, or the DMA engine is capable to
  475. * handle both SG lists on hardware accelerated basis.
  476. */
  477. if (!dws->dma_sg_burst || !xfer->rx_buf || nents <= dws->dma_sg_burst)
  478. ret = dw_spi_dma_transfer_all(dws, xfer);
  479. else
  480. ret = dw_spi_dma_transfer_one(dws, xfer);
  481. if (ret)
  482. return ret;
  483. if (dws->master->cur_msg->status == -EINPROGRESS) {
  484. ret = dw_spi_dma_wait_tx_done(dws, xfer);
  485. if (ret)
  486. return ret;
  487. }
  488. if (xfer->rx_buf && dws->master->cur_msg->status == -EINPROGRESS)
  489. ret = dw_spi_dma_wait_rx_done(dws);
  490. return ret;
  491. }
  492. static void dw_spi_dma_stop(struct dw_spi *dws)
  493. {
  494. if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
  495. dmaengine_terminate_sync(dws->txchan);
  496. clear_bit(TX_BUSY, &dws->dma_chan_busy);
  497. }
  498. if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
  499. dmaengine_terminate_sync(dws->rxchan);
  500. clear_bit(RX_BUSY, &dws->dma_chan_busy);
  501. }
  502. }
  503. static const struct dw_spi_dma_ops dw_spi_dma_mfld_ops = {
  504. .dma_init = dw_spi_dma_init_mfld,
  505. .dma_exit = dw_spi_dma_exit,
  506. .dma_setup = dw_spi_dma_setup,
  507. .can_dma = dw_spi_can_dma,
  508. .dma_transfer = dw_spi_dma_transfer,
  509. .dma_stop = dw_spi_dma_stop,
  510. };
  511. void dw_spi_dma_setup_mfld(struct dw_spi *dws)
  512. {
  513. dws->dma_ops = &dw_spi_dma_mfld_ops;
  514. }
  515. EXPORT_SYMBOL_GPL(dw_spi_dma_setup_mfld);
  516. static const struct dw_spi_dma_ops dw_spi_dma_generic_ops = {
  517. .dma_init = dw_spi_dma_init_generic,
  518. .dma_exit = dw_spi_dma_exit,
  519. .dma_setup = dw_spi_dma_setup,
  520. .can_dma = dw_spi_can_dma,
  521. .dma_transfer = dw_spi_dma_transfer,
  522. .dma_stop = dw_spi_dma_stop,
  523. };
  524. void dw_spi_dma_setup_generic(struct dw_spi *dws)
  525. {
  526. dws->dma_ops = &dw_spi_dma_generic_ops;
  527. }
  528. EXPORT_SYMBOL_GPL(dw_spi_dma_setup_generic);