spi-davinci.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2009 Texas Instruments.
  4. * Copyright (C) 2010 EF Johnson Technologies
  5. */
  6. #include <linux/interrupt.h>
  7. #include <linux/io.h>
  8. #include <linux/gpio/consumer.h>
  9. #include <linux/module.h>
  10. #include <linux/delay.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/err.h>
  13. #include <linux/clk.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/spi/spi_bitbang.h>
  20. #include <linux/slab.h>
  21. #include <linux/platform_data/spi-davinci.h>
  22. #define CS_DEFAULT 0xFF
  23. #define SPIFMT_PHASE_MASK BIT(16)
  24. #define SPIFMT_POLARITY_MASK BIT(17)
  25. #define SPIFMT_DISTIMER_MASK BIT(18)
  26. #define SPIFMT_SHIFTDIR_MASK BIT(20)
  27. #define SPIFMT_WAITENA_MASK BIT(21)
  28. #define SPIFMT_PARITYENA_MASK BIT(22)
  29. #define SPIFMT_ODD_PARITY_MASK BIT(23)
  30. #define SPIFMT_WDELAY_MASK 0x3f000000u
  31. #define SPIFMT_WDELAY_SHIFT 24
  32. #define SPIFMT_PRESCALE_SHIFT 8
  33. /* SPIPC0 */
  34. #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
  35. #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
  36. #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
  37. #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
  38. #define SPIINT_MASKALL 0x0101035F
  39. #define SPIINT_MASKINT 0x0000015F
  40. #define SPI_INTLVL_1 0x000001FF
  41. #define SPI_INTLVL_0 0x00000000
  42. /* SPIDAT1 (upper 16 bit defines) */
  43. #define SPIDAT1_CSHOLD_MASK BIT(12)
  44. #define SPIDAT1_WDEL BIT(10)
  45. /* SPIGCR1 */
  46. #define SPIGCR1_CLKMOD_MASK BIT(1)
  47. #define SPIGCR1_MASTER_MASK BIT(0)
  48. #define SPIGCR1_POWERDOWN_MASK BIT(8)
  49. #define SPIGCR1_LOOPBACK_MASK BIT(16)
  50. #define SPIGCR1_SPIENA_MASK BIT(24)
  51. /* SPIBUF */
  52. #define SPIBUF_TXFULL_MASK BIT(29)
  53. #define SPIBUF_RXEMPTY_MASK BIT(31)
  54. /* SPIDELAY */
  55. #define SPIDELAY_C2TDELAY_SHIFT 24
  56. #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
  57. #define SPIDELAY_T2CDELAY_SHIFT 16
  58. #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
  59. #define SPIDELAY_T2EDELAY_SHIFT 8
  60. #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
  61. #define SPIDELAY_C2EDELAY_SHIFT 0
  62. #define SPIDELAY_C2EDELAY_MASK 0xFF
  63. /* Error Masks */
  64. #define SPIFLG_DLEN_ERR_MASK BIT(0)
  65. #define SPIFLG_TIMEOUT_MASK BIT(1)
  66. #define SPIFLG_PARERR_MASK BIT(2)
  67. #define SPIFLG_DESYNC_MASK BIT(3)
  68. #define SPIFLG_BITERR_MASK BIT(4)
  69. #define SPIFLG_OVRRUN_MASK BIT(6)
  70. #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
  71. #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
  72. | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
  73. | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
  74. | SPIFLG_OVRRUN_MASK)
  75. #define SPIINT_DMA_REQ_EN BIT(16)
  76. /* SPI Controller registers */
  77. #define SPIGCR0 0x00
  78. #define SPIGCR1 0x04
  79. #define SPIINT 0x08
  80. #define SPILVL 0x0c
  81. #define SPIFLG 0x10
  82. #define SPIPC0 0x14
  83. #define SPIDAT1 0x3c
  84. #define SPIBUF 0x40
  85. #define SPIDELAY 0x48
  86. #define SPIDEF 0x4c
  87. #define SPIFMT0 0x50
  88. #define DMA_MIN_BYTES 16
  89. /* SPI Controller driver's private data. */
  90. struct davinci_spi {
  91. struct spi_bitbang bitbang;
  92. struct clk *clk;
  93. u8 version;
  94. resource_size_t pbase;
  95. void __iomem *base;
  96. u32 irq;
  97. struct completion done;
  98. const void *tx;
  99. void *rx;
  100. int rcount;
  101. int wcount;
  102. struct dma_chan *dma_rx;
  103. struct dma_chan *dma_tx;
  104. struct davinci_spi_platform_data pdata;
  105. void (*get_rx)(u32 rx_data, struct davinci_spi *);
  106. u32 (*get_tx)(struct davinci_spi *);
  107. u8 *bytes_per_word;
  108. u8 prescaler_limit;
  109. };
  110. static struct davinci_spi_config davinci_spi_default_cfg;
  111. static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
  112. {
  113. if (dspi->rx) {
  114. u8 *rx = dspi->rx;
  115. *rx++ = (u8)data;
  116. dspi->rx = rx;
  117. }
  118. }
  119. static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
  120. {
  121. if (dspi->rx) {
  122. u16 *rx = dspi->rx;
  123. *rx++ = (u16)data;
  124. dspi->rx = rx;
  125. }
  126. }
  127. static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
  128. {
  129. u32 data = 0;
  130. if (dspi->tx) {
  131. const u8 *tx = dspi->tx;
  132. data = *tx++;
  133. dspi->tx = tx;
  134. }
  135. return data;
  136. }
  137. static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
  138. {
  139. u32 data = 0;
  140. if (dspi->tx) {
  141. const u16 *tx = dspi->tx;
  142. data = *tx++;
  143. dspi->tx = tx;
  144. }
  145. return data;
  146. }
  147. static inline void set_io_bits(void __iomem *addr, u32 bits)
  148. {
  149. u32 v = ioread32(addr);
  150. v |= bits;
  151. iowrite32(v, addr);
  152. }
  153. static inline void clear_io_bits(void __iomem *addr, u32 bits)
  154. {
  155. u32 v = ioread32(addr);
  156. v &= ~bits;
  157. iowrite32(v, addr);
  158. }
  159. /*
  160. * Interface to control the chip select signal
  161. */
  162. static void davinci_spi_chipselect(struct spi_device *spi, int value)
  163. {
  164. struct davinci_spi *dspi;
  165. struct davinci_spi_config *spicfg = spi->controller_data;
  166. u8 chip_sel = spi->chip_select;
  167. u16 spidat1 = CS_DEFAULT;
  168. dspi = spi_master_get_devdata(spi->master);
  169. /* program delay transfers if tx_delay is non zero */
  170. if (spicfg && spicfg->wdelay)
  171. spidat1 |= SPIDAT1_WDEL;
  172. /*
  173. * Board specific chip select logic decides the polarity and cs
  174. * line for the controller
  175. */
  176. if (spi->cs_gpiod) {
  177. if (value == BITBANG_CS_ACTIVE)
  178. gpiod_set_value(spi->cs_gpiod, 1);
  179. else
  180. gpiod_set_value(spi->cs_gpiod, 0);
  181. } else {
  182. if (value == BITBANG_CS_ACTIVE) {
  183. if (!(spi->mode & SPI_CS_WORD))
  184. spidat1 |= SPIDAT1_CSHOLD_MASK;
  185. spidat1 &= ~(0x1 << chip_sel);
  186. }
  187. }
  188. iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
  189. }
  190. /**
  191. * davinci_spi_get_prescale - Calculates the correct prescale value
  192. * @dspi: the controller data
  193. * @max_speed_hz: the maximum rate the SPI clock can run at
  194. *
  195. * This function calculates the prescale value that generates a clock rate
  196. * less than or equal to the specified maximum.
  197. *
  198. * Returns: calculated prescale value for easy programming into SPI registers
  199. * or negative error number if valid prescalar cannot be updated.
  200. */
  201. static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
  202. u32 max_speed_hz)
  203. {
  204. int ret;
  205. /* Subtract 1 to match what will be programmed into SPI register. */
  206. ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
  207. if (ret < dspi->prescaler_limit || ret > 255)
  208. return -EINVAL;
  209. return ret;
  210. }
  211. /**
  212. * davinci_spi_setup_transfer - This functions will determine transfer method
  213. * @spi: spi device on which data transfer to be done
  214. * @t: spi transfer in which transfer info is filled
  215. *
  216. * This function determines data transfer method (8/16/32 bit transfer).
  217. * It will also set the SPI Clock Control register according to
  218. * SPI slave device freq.
  219. */
  220. static int davinci_spi_setup_transfer(struct spi_device *spi,
  221. struct spi_transfer *t)
  222. {
  223. struct davinci_spi *dspi;
  224. struct davinci_spi_config *spicfg;
  225. u8 bits_per_word = 0;
  226. u32 hz = 0, spifmt = 0;
  227. int prescale;
  228. dspi = spi_master_get_devdata(spi->master);
  229. spicfg = spi->controller_data;
  230. if (!spicfg)
  231. spicfg = &davinci_spi_default_cfg;
  232. if (t) {
  233. bits_per_word = t->bits_per_word;
  234. hz = t->speed_hz;
  235. }
  236. /* if bits_per_word is not set then set it default */
  237. if (!bits_per_word)
  238. bits_per_word = spi->bits_per_word;
  239. /*
  240. * Assign function pointer to appropriate transfer method
  241. * 8bit, 16bit or 32bit transfer
  242. */
  243. if (bits_per_word <= 8) {
  244. dspi->get_rx = davinci_spi_rx_buf_u8;
  245. dspi->get_tx = davinci_spi_tx_buf_u8;
  246. dspi->bytes_per_word[spi->chip_select] = 1;
  247. } else {
  248. dspi->get_rx = davinci_spi_rx_buf_u16;
  249. dspi->get_tx = davinci_spi_tx_buf_u16;
  250. dspi->bytes_per_word[spi->chip_select] = 2;
  251. }
  252. if (!hz)
  253. hz = spi->max_speed_hz;
  254. /* Set up SPIFMTn register, unique to this chipselect. */
  255. prescale = davinci_spi_get_prescale(dspi, hz);
  256. if (prescale < 0)
  257. return prescale;
  258. spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
  259. if (spi->mode & SPI_LSB_FIRST)
  260. spifmt |= SPIFMT_SHIFTDIR_MASK;
  261. if (spi->mode & SPI_CPOL)
  262. spifmt |= SPIFMT_POLARITY_MASK;
  263. if (!(spi->mode & SPI_CPHA))
  264. spifmt |= SPIFMT_PHASE_MASK;
  265. /*
  266. * Assume wdelay is used only on SPI peripherals that has this field
  267. * in SPIFMTn register and when it's configured from board file or DT.
  268. */
  269. if (spicfg->wdelay)
  270. spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
  271. & SPIFMT_WDELAY_MASK);
  272. /*
  273. * Version 1 hardware supports two basic SPI modes:
  274. * - Standard SPI mode uses 4 pins, with chipselect
  275. * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
  276. * (distinct from SPI_3WIRE, with just one data wire;
  277. * or similar variants without MOSI or without MISO)
  278. *
  279. * Version 2 hardware supports an optional handshaking signal,
  280. * so it can support two more modes:
  281. * - 5 pin SPI variant is standard SPI plus SPI_READY
  282. * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
  283. */
  284. if (dspi->version == SPI_VERSION_2) {
  285. u32 delay = 0;
  286. if (spicfg->odd_parity)
  287. spifmt |= SPIFMT_ODD_PARITY_MASK;
  288. if (spicfg->parity_enable)
  289. spifmt |= SPIFMT_PARITYENA_MASK;
  290. if (spicfg->timer_disable) {
  291. spifmt |= SPIFMT_DISTIMER_MASK;
  292. } else {
  293. delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
  294. & SPIDELAY_C2TDELAY_MASK;
  295. delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
  296. & SPIDELAY_T2CDELAY_MASK;
  297. }
  298. if (spi->mode & SPI_READY) {
  299. spifmt |= SPIFMT_WAITENA_MASK;
  300. delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
  301. & SPIDELAY_T2EDELAY_MASK;
  302. delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
  303. & SPIDELAY_C2EDELAY_MASK;
  304. }
  305. iowrite32(delay, dspi->base + SPIDELAY);
  306. }
  307. iowrite32(spifmt, dspi->base + SPIFMT0);
  308. return 0;
  309. }
  310. static int davinci_spi_of_setup(struct spi_device *spi)
  311. {
  312. struct davinci_spi_config *spicfg = spi->controller_data;
  313. struct device_node *np = spi->dev.of_node;
  314. struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
  315. u32 prop;
  316. if (spicfg == NULL && np) {
  317. spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
  318. if (!spicfg)
  319. return -ENOMEM;
  320. *spicfg = davinci_spi_default_cfg;
  321. /* override with dt configured values */
  322. if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
  323. spicfg->wdelay = (u8)prop;
  324. spi->controller_data = spicfg;
  325. if (dspi->dma_rx && dspi->dma_tx)
  326. spicfg->io_type = SPI_IO_TYPE_DMA;
  327. }
  328. return 0;
  329. }
  330. /**
  331. * davinci_spi_setup - This functions will set default transfer method
  332. * @spi: spi device on which data transfer to be done
  333. *
  334. * This functions sets the default transfer method.
  335. */
  336. static int davinci_spi_setup(struct spi_device *spi)
  337. {
  338. struct davinci_spi *dspi;
  339. struct device_node *np = spi->dev.of_node;
  340. bool internal_cs = true;
  341. dspi = spi_master_get_devdata(spi->master);
  342. if (!(spi->mode & SPI_NO_CS)) {
  343. if (np && spi->cs_gpiod)
  344. internal_cs = false;
  345. if (internal_cs)
  346. set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
  347. }
  348. if (spi->mode & SPI_READY)
  349. set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
  350. if (spi->mode & SPI_LOOP)
  351. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
  352. else
  353. clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
  354. return davinci_spi_of_setup(spi);
  355. }
  356. static void davinci_spi_cleanup(struct spi_device *spi)
  357. {
  358. struct davinci_spi_config *spicfg = spi->controller_data;
  359. spi->controller_data = NULL;
  360. if (spi->dev.of_node)
  361. kfree(spicfg);
  362. }
  363. static bool davinci_spi_can_dma(struct spi_master *master,
  364. struct spi_device *spi,
  365. struct spi_transfer *xfer)
  366. {
  367. struct davinci_spi_config *spicfg = spi->controller_data;
  368. bool can_dma = false;
  369. if (spicfg)
  370. can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) &&
  371. (xfer->len >= DMA_MIN_BYTES) &&
  372. !is_vmalloc_addr(xfer->rx_buf) &&
  373. !is_vmalloc_addr(xfer->tx_buf);
  374. return can_dma;
  375. }
  376. static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
  377. {
  378. struct device *sdev = dspi->bitbang.master->dev.parent;
  379. if (int_status & SPIFLG_TIMEOUT_MASK) {
  380. dev_err(sdev, "SPI Time-out Error\n");
  381. return -ETIMEDOUT;
  382. }
  383. if (int_status & SPIFLG_DESYNC_MASK) {
  384. dev_err(sdev, "SPI Desynchronization Error\n");
  385. return -EIO;
  386. }
  387. if (int_status & SPIFLG_BITERR_MASK) {
  388. dev_err(sdev, "SPI Bit error\n");
  389. return -EIO;
  390. }
  391. if (dspi->version == SPI_VERSION_2) {
  392. if (int_status & SPIFLG_DLEN_ERR_MASK) {
  393. dev_err(sdev, "SPI Data Length Error\n");
  394. return -EIO;
  395. }
  396. if (int_status & SPIFLG_PARERR_MASK) {
  397. dev_err(sdev, "SPI Parity Error\n");
  398. return -EIO;
  399. }
  400. if (int_status & SPIFLG_OVRRUN_MASK) {
  401. dev_err(sdev, "SPI Data Overrun error\n");
  402. return -EIO;
  403. }
  404. if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
  405. dev_err(sdev, "SPI Buffer Init Active\n");
  406. return -EBUSY;
  407. }
  408. }
  409. return 0;
  410. }
  411. /**
  412. * davinci_spi_process_events - check for and handle any SPI controller events
  413. * @dspi: the controller data
  414. *
  415. * This function will check the SPIFLG register and handle any events that are
  416. * detected there
  417. */
  418. static int davinci_spi_process_events(struct davinci_spi *dspi)
  419. {
  420. u32 buf, status, errors = 0, spidat1;
  421. buf = ioread32(dspi->base + SPIBUF);
  422. if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
  423. dspi->get_rx(buf & 0xFFFF, dspi);
  424. dspi->rcount--;
  425. }
  426. status = ioread32(dspi->base + SPIFLG);
  427. if (unlikely(status & SPIFLG_ERROR_MASK)) {
  428. errors = status & SPIFLG_ERROR_MASK;
  429. goto out;
  430. }
  431. if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
  432. spidat1 = ioread32(dspi->base + SPIDAT1);
  433. dspi->wcount--;
  434. spidat1 &= ~0xFFFF;
  435. spidat1 |= 0xFFFF & dspi->get_tx(dspi);
  436. iowrite32(spidat1, dspi->base + SPIDAT1);
  437. }
  438. out:
  439. return errors;
  440. }
  441. static void davinci_spi_dma_rx_callback(void *data)
  442. {
  443. struct davinci_spi *dspi = (struct davinci_spi *)data;
  444. dspi->rcount = 0;
  445. if (!dspi->wcount && !dspi->rcount)
  446. complete(&dspi->done);
  447. }
  448. static void davinci_spi_dma_tx_callback(void *data)
  449. {
  450. struct davinci_spi *dspi = (struct davinci_spi *)data;
  451. dspi->wcount = 0;
  452. if (!dspi->wcount && !dspi->rcount)
  453. complete(&dspi->done);
  454. }
  455. /**
  456. * davinci_spi_bufs - functions which will handle transfer data
  457. * @spi: spi device on which data transfer to be done
  458. * @t: spi transfer in which transfer info is filled
  459. *
  460. * This function will put data to be transferred into data register
  461. * of SPI controller and then wait until the completion will be marked
  462. * by the IRQ Handler.
  463. */
  464. static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
  465. {
  466. struct davinci_spi *dspi;
  467. int data_type, ret = -ENOMEM;
  468. u32 tx_data, spidat1;
  469. u32 errors = 0;
  470. struct davinci_spi_config *spicfg;
  471. struct davinci_spi_platform_data *pdata;
  472. dspi = spi_master_get_devdata(spi->master);
  473. pdata = &dspi->pdata;
  474. spicfg = (struct davinci_spi_config *)spi->controller_data;
  475. if (!spicfg)
  476. spicfg = &davinci_spi_default_cfg;
  477. /* convert len to words based on bits_per_word */
  478. data_type = dspi->bytes_per_word[spi->chip_select];
  479. dspi->tx = t->tx_buf;
  480. dspi->rx = t->rx_buf;
  481. dspi->wcount = t->len / data_type;
  482. dspi->rcount = dspi->wcount;
  483. spidat1 = ioread32(dspi->base + SPIDAT1);
  484. clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
  485. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
  486. reinit_completion(&dspi->done);
  487. if (!davinci_spi_can_dma(spi->master, spi, t)) {
  488. if (spicfg->io_type != SPI_IO_TYPE_POLL)
  489. set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
  490. /* start the transfer */
  491. dspi->wcount--;
  492. tx_data = dspi->get_tx(dspi);
  493. spidat1 &= 0xFFFF0000;
  494. spidat1 |= tx_data & 0xFFFF;
  495. iowrite32(spidat1, dspi->base + SPIDAT1);
  496. } else {
  497. struct dma_slave_config dma_rx_conf = {
  498. .direction = DMA_DEV_TO_MEM,
  499. .src_addr = (unsigned long)dspi->pbase + SPIBUF,
  500. .src_addr_width = data_type,
  501. .src_maxburst = 1,
  502. };
  503. struct dma_slave_config dma_tx_conf = {
  504. .direction = DMA_MEM_TO_DEV,
  505. .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
  506. .dst_addr_width = data_type,
  507. .dst_maxburst = 1,
  508. };
  509. struct dma_async_tx_descriptor *rxdesc;
  510. struct dma_async_tx_descriptor *txdesc;
  511. dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
  512. dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
  513. rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
  514. t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM,
  515. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  516. if (!rxdesc)
  517. goto err_desc;
  518. if (!t->tx_buf) {
  519. /* To avoid errors when doing rx-only transfers with
  520. * many SG entries (> 20), use the rx buffer as the
  521. * dummy tx buffer so that dma reloads are done at the
  522. * same time for rx and tx.
  523. */
  524. t->tx_sg.sgl = t->rx_sg.sgl;
  525. t->tx_sg.nents = t->rx_sg.nents;
  526. }
  527. txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
  528. t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV,
  529. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  530. if (!txdesc)
  531. goto err_desc;
  532. rxdesc->callback = davinci_spi_dma_rx_callback;
  533. rxdesc->callback_param = (void *)dspi;
  534. txdesc->callback = davinci_spi_dma_tx_callback;
  535. txdesc->callback_param = (void *)dspi;
  536. if (pdata->cshold_bug)
  537. iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
  538. dmaengine_submit(rxdesc);
  539. dmaengine_submit(txdesc);
  540. dma_async_issue_pending(dspi->dma_rx);
  541. dma_async_issue_pending(dspi->dma_tx);
  542. set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
  543. }
  544. /* Wait for the transfer to complete */
  545. if (spicfg->io_type != SPI_IO_TYPE_POLL) {
  546. if (wait_for_completion_timeout(&dspi->done, HZ) == 0)
  547. errors = SPIFLG_TIMEOUT_MASK;
  548. } else {
  549. while (dspi->rcount > 0 || dspi->wcount > 0) {
  550. errors = davinci_spi_process_events(dspi);
  551. if (errors)
  552. break;
  553. cpu_relax();
  554. }
  555. }
  556. clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
  557. if (davinci_spi_can_dma(spi->master, spi, t))
  558. clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
  559. clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
  560. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
  561. /*
  562. * Check for bit error, desync error,parity error,timeout error and
  563. * receive overflow errors
  564. */
  565. if (errors) {
  566. ret = davinci_spi_check_error(dspi, errors);
  567. WARN(!ret, "%s: error reported but no error found!\n",
  568. dev_name(&spi->dev));
  569. return ret;
  570. }
  571. if (dspi->rcount != 0 || dspi->wcount != 0) {
  572. dev_err(&spi->dev, "SPI data transfer error\n");
  573. return -EIO;
  574. }
  575. return t->len;
  576. err_desc:
  577. return ret;
  578. }
  579. /**
  580. * dummy_thread_fn - dummy thread function
  581. * @irq: IRQ number for this SPI Master
  582. * @data: structure for SPI Master controller davinci_spi
  583. *
  584. * This is to satisfy the request_threaded_irq() API so that the irq
  585. * handler is called in interrupt context.
  586. */
  587. static irqreturn_t dummy_thread_fn(s32 irq, void *data)
  588. {
  589. return IRQ_HANDLED;
  590. }
  591. /**
  592. * davinci_spi_irq - Interrupt handler for SPI Master Controller
  593. * @irq: IRQ number for this SPI Master
  594. * @data: structure for SPI Master controller davinci_spi
  595. *
  596. * ISR will determine that interrupt arrives either for READ or WRITE command.
  597. * According to command it will do the appropriate action. It will check
  598. * transfer length and if it is not zero then dispatch transfer command again.
  599. * If transfer length is zero then it will indicate the COMPLETION so that
  600. * davinci_spi_bufs function can go ahead.
  601. */
  602. static irqreturn_t davinci_spi_irq(s32 irq, void *data)
  603. {
  604. struct davinci_spi *dspi = data;
  605. int status;
  606. status = davinci_spi_process_events(dspi);
  607. if (unlikely(status != 0))
  608. clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
  609. if ((!dspi->rcount && !dspi->wcount) || status)
  610. complete(&dspi->done);
  611. return IRQ_HANDLED;
  612. }
  613. static int davinci_spi_request_dma(struct davinci_spi *dspi)
  614. {
  615. struct device *sdev = dspi->bitbang.master->dev.parent;
  616. dspi->dma_rx = dma_request_chan(sdev, "rx");
  617. if (IS_ERR(dspi->dma_rx))
  618. return PTR_ERR(dspi->dma_rx);
  619. dspi->dma_tx = dma_request_chan(sdev, "tx");
  620. if (IS_ERR(dspi->dma_tx)) {
  621. dma_release_channel(dspi->dma_rx);
  622. return PTR_ERR(dspi->dma_tx);
  623. }
  624. return 0;
  625. }
  626. #if defined(CONFIG_OF)
  627. /* OF SPI data structure */
  628. struct davinci_spi_of_data {
  629. u8 version;
  630. u8 prescaler_limit;
  631. };
  632. static const struct davinci_spi_of_data dm6441_spi_data = {
  633. .version = SPI_VERSION_1,
  634. .prescaler_limit = 2,
  635. };
  636. static const struct davinci_spi_of_data da830_spi_data = {
  637. .version = SPI_VERSION_2,
  638. .prescaler_limit = 2,
  639. };
  640. static const struct davinci_spi_of_data keystone_spi_data = {
  641. .version = SPI_VERSION_1,
  642. .prescaler_limit = 0,
  643. };
  644. static const struct of_device_id davinci_spi_of_match[] = {
  645. {
  646. .compatible = "ti,dm6441-spi",
  647. .data = &dm6441_spi_data,
  648. },
  649. {
  650. .compatible = "ti,da830-spi",
  651. .data = &da830_spi_data,
  652. },
  653. {
  654. .compatible = "ti,keystone-spi",
  655. .data = &keystone_spi_data,
  656. },
  657. { },
  658. };
  659. MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
  660. /**
  661. * spi_davinci_get_pdata - Get platform data from DTS binding
  662. * @pdev: ptr to platform data
  663. * @dspi: ptr to driver data
  664. *
  665. * Parses and populates pdata in dspi from device tree bindings.
  666. *
  667. * NOTE: Not all platform data params are supported currently.
  668. */
  669. static int spi_davinci_get_pdata(struct platform_device *pdev,
  670. struct davinci_spi *dspi)
  671. {
  672. struct device_node *node = pdev->dev.of_node;
  673. struct davinci_spi_of_data *spi_data;
  674. struct davinci_spi_platform_data *pdata;
  675. unsigned int num_cs, intr_line = 0;
  676. const struct of_device_id *match;
  677. pdata = &dspi->pdata;
  678. match = of_match_device(davinci_spi_of_match, &pdev->dev);
  679. if (!match)
  680. return -ENODEV;
  681. spi_data = (struct davinci_spi_of_data *)match->data;
  682. pdata->version = spi_data->version;
  683. pdata->prescaler_limit = spi_data->prescaler_limit;
  684. /*
  685. * default num_cs is 1 and all chipsel are internal to the chip
  686. * indicated by chip_sel being NULL or cs_gpios being NULL or
  687. * set to -ENOENT. num-cs includes internal as well as gpios.
  688. * indicated by chip_sel being NULL. GPIO based CS is not
  689. * supported yet in DT bindings.
  690. */
  691. num_cs = 1;
  692. of_property_read_u32(node, "num-cs", &num_cs);
  693. pdata->num_chipselect = num_cs;
  694. of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
  695. pdata->intr_line = intr_line;
  696. return 0;
  697. }
  698. #else
  699. static int spi_davinci_get_pdata(struct platform_device *pdev,
  700. struct davinci_spi *dspi)
  701. {
  702. return -ENODEV;
  703. }
  704. #endif
  705. /**
  706. * davinci_spi_probe - probe function for SPI Master Controller
  707. * @pdev: platform_device structure which contains plateform specific data
  708. *
  709. * According to Linux Device Model this function will be invoked by Linux
  710. * with platform_device struct which contains the device specific info.
  711. * This function will map the SPI controller's memory, register IRQ,
  712. * Reset SPI controller and setting its registers to default value.
  713. * It will invoke spi_bitbang_start to create work queue so that client driver
  714. * can register transfer method to work queue.
  715. */
  716. static int davinci_spi_probe(struct platform_device *pdev)
  717. {
  718. struct spi_master *master;
  719. struct davinci_spi *dspi;
  720. struct davinci_spi_platform_data *pdata;
  721. struct resource *r;
  722. int ret = 0;
  723. u32 spipc0;
  724. master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
  725. if (master == NULL) {
  726. ret = -ENOMEM;
  727. goto err;
  728. }
  729. platform_set_drvdata(pdev, master);
  730. dspi = spi_master_get_devdata(master);
  731. if (dev_get_platdata(&pdev->dev)) {
  732. pdata = dev_get_platdata(&pdev->dev);
  733. dspi->pdata = *pdata;
  734. } else {
  735. /* update dspi pdata with that from the DT */
  736. ret = spi_davinci_get_pdata(pdev, dspi);
  737. if (ret < 0)
  738. goto free_master;
  739. }
  740. /* pdata in dspi is now updated and point pdata to that */
  741. pdata = &dspi->pdata;
  742. dspi->bytes_per_word = devm_kcalloc(&pdev->dev,
  743. pdata->num_chipselect,
  744. sizeof(*dspi->bytes_per_word),
  745. GFP_KERNEL);
  746. if (dspi->bytes_per_word == NULL) {
  747. ret = -ENOMEM;
  748. goto free_master;
  749. }
  750. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  751. if (r == NULL) {
  752. ret = -ENOENT;
  753. goto free_master;
  754. }
  755. dspi->pbase = r->start;
  756. dspi->base = devm_ioremap_resource(&pdev->dev, r);
  757. if (IS_ERR(dspi->base)) {
  758. ret = PTR_ERR(dspi->base);
  759. goto free_master;
  760. }
  761. init_completion(&dspi->done);
  762. ret = platform_get_irq(pdev, 0);
  763. if (ret == 0)
  764. ret = -EINVAL;
  765. if (ret < 0)
  766. goto free_master;
  767. dspi->irq = ret;
  768. ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
  769. dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
  770. if (ret)
  771. goto free_master;
  772. dspi->bitbang.master = master;
  773. dspi->clk = devm_clk_get(&pdev->dev, NULL);
  774. if (IS_ERR(dspi->clk)) {
  775. ret = -ENODEV;
  776. goto free_master;
  777. }
  778. ret = clk_prepare_enable(dspi->clk);
  779. if (ret)
  780. goto free_master;
  781. master->use_gpio_descriptors = true;
  782. master->dev.of_node = pdev->dev.of_node;
  783. master->bus_num = pdev->id;
  784. master->num_chipselect = pdata->num_chipselect;
  785. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
  786. master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_GPIO_SS;
  787. master->setup = davinci_spi_setup;
  788. master->cleanup = davinci_spi_cleanup;
  789. master->can_dma = davinci_spi_can_dma;
  790. dspi->bitbang.chipselect = davinci_spi_chipselect;
  791. dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
  792. dspi->prescaler_limit = pdata->prescaler_limit;
  793. dspi->version = pdata->version;
  794. dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD;
  795. if (dspi->version == SPI_VERSION_2)
  796. dspi->bitbang.flags |= SPI_READY;
  797. dspi->bitbang.txrx_bufs = davinci_spi_bufs;
  798. ret = davinci_spi_request_dma(dspi);
  799. if (ret == -EPROBE_DEFER) {
  800. goto free_clk;
  801. } else if (ret) {
  802. dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret);
  803. dspi->dma_rx = NULL;
  804. dspi->dma_tx = NULL;
  805. }
  806. dspi->get_rx = davinci_spi_rx_buf_u8;
  807. dspi->get_tx = davinci_spi_tx_buf_u8;
  808. /* Reset In/OUT SPI module */
  809. iowrite32(0, dspi->base + SPIGCR0);
  810. udelay(100);
  811. iowrite32(1, dspi->base + SPIGCR0);
  812. /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
  813. spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
  814. iowrite32(spipc0, dspi->base + SPIPC0);
  815. if (pdata->intr_line)
  816. iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
  817. else
  818. iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
  819. iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
  820. /* master mode default */
  821. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
  822. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
  823. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
  824. ret = spi_bitbang_start(&dspi->bitbang);
  825. if (ret)
  826. goto free_dma;
  827. dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
  828. return ret;
  829. free_dma:
  830. if (dspi->dma_rx) {
  831. dma_release_channel(dspi->dma_rx);
  832. dma_release_channel(dspi->dma_tx);
  833. }
  834. free_clk:
  835. clk_disable_unprepare(dspi->clk);
  836. free_master:
  837. spi_master_put(master);
  838. err:
  839. return ret;
  840. }
  841. /**
  842. * davinci_spi_remove - remove function for SPI Master Controller
  843. * @pdev: platform_device structure which contains plateform specific data
  844. *
  845. * This function will do the reverse action of davinci_spi_probe function
  846. * It will free the IRQ and SPI controller's memory region.
  847. * It will also call spi_bitbang_stop to destroy the work queue which was
  848. * created by spi_bitbang_start.
  849. */
  850. static int davinci_spi_remove(struct platform_device *pdev)
  851. {
  852. struct davinci_spi *dspi;
  853. struct spi_master *master;
  854. master = platform_get_drvdata(pdev);
  855. dspi = spi_master_get_devdata(master);
  856. spi_bitbang_stop(&dspi->bitbang);
  857. clk_disable_unprepare(dspi->clk);
  858. if (dspi->dma_rx) {
  859. dma_release_channel(dspi->dma_rx);
  860. dma_release_channel(dspi->dma_tx);
  861. }
  862. spi_master_put(master);
  863. return 0;
  864. }
  865. static struct platform_driver davinci_spi_driver = {
  866. .driver = {
  867. .name = "spi_davinci",
  868. .of_match_table = of_match_ptr(davinci_spi_of_match),
  869. },
  870. .probe = davinci_spi_probe,
  871. .remove = davinci_spi_remove,
  872. };
  873. module_platform_driver(davinci_spi_driver);
  874. MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
  875. MODULE_LICENSE("GPL");