spi-cadence.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Cadence SPI controller driver (master mode only)
  4. *
  5. * Copyright (C) 2008 - 2014 Xilinx, Inc.
  6. *
  7. * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/gpio/consumer.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/of_address.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/spi/spi.h>
  20. /* Name of this driver */
  21. #define CDNS_SPI_NAME "cdns-spi"
  22. /* Register offset definitions */
  23. #define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
  24. #define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
  25. #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
  26. #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
  27. #define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
  28. #define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
  29. #define CDNS_SPI_DR 0x18 /* Delay Register, RW */
  30. #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
  31. #define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
  32. #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
  33. #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
  34. #define SPI_AUTOSUSPEND_TIMEOUT 3000
  35. /*
  36. * SPI Configuration Register bit Masks
  37. *
  38. * This register contains various control bits that affect the operation
  39. * of the SPI controller
  40. */
  41. #define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
  42. #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
  43. #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
  44. #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
  45. #define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
  46. #define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
  47. #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
  48. #define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
  49. #define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
  50. #define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
  51. #define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
  52. CDNS_SPI_CR_SSCTRL | \
  53. CDNS_SPI_CR_SSFORCE | \
  54. CDNS_SPI_CR_BAUD_DIV_4)
  55. /*
  56. * SPI Configuration Register - Baud rate and slave select
  57. *
  58. * These are the values used in the calculation of baud rate divisor and
  59. * setting the slave select.
  60. */
  61. #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
  62. #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
  63. #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
  64. #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
  65. #define CDNS_SPI_SS0 0x1 /* Slave Select zero */
  66. /*
  67. * SPI Interrupt Registers bit Masks
  68. *
  69. * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  70. * bit definitions.
  71. */
  72. #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
  73. #define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
  74. #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
  75. #define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
  76. CDNS_SPI_IXR_MODF)
  77. #define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
  78. #define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
  79. /*
  80. * SPI Enable Register bit Masks
  81. *
  82. * This register is used to enable or disable the SPI controller
  83. */
  84. #define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
  85. #define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
  86. /* SPI FIFO depth in bytes */
  87. #define CDNS_SPI_FIFO_DEPTH 128
  88. /* Default number of chip select lines */
  89. #define CDNS_SPI_DEFAULT_NUM_CS 4
  90. /**
  91. * struct cdns_spi - This definition defines spi driver instance
  92. * @regs: Virtual address of the SPI controller registers
  93. * @ref_clk: Pointer to the peripheral clock
  94. * @pclk: Pointer to the APB clock
  95. * @speed_hz: Current SPI bus clock speed in Hz
  96. * @txbuf: Pointer to the TX buffer
  97. * @rxbuf: Pointer to the RX buffer
  98. * @tx_bytes: Number of bytes left to transfer
  99. * @rx_bytes: Number of bytes requested
  100. * @dev_busy: Device busy flag
  101. * @is_decoded_cs: Flag for decoder property set or not
  102. */
  103. struct cdns_spi {
  104. void __iomem *regs;
  105. struct clk *ref_clk;
  106. struct clk *pclk;
  107. unsigned int clk_rate;
  108. u32 speed_hz;
  109. const u8 *txbuf;
  110. u8 *rxbuf;
  111. int tx_bytes;
  112. int rx_bytes;
  113. u8 dev_busy;
  114. u32 is_decoded_cs;
  115. };
  116. /* Macros for the SPI controller read/write */
  117. static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
  118. {
  119. return readl_relaxed(xspi->regs + offset);
  120. }
  121. static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
  122. {
  123. writel_relaxed(val, xspi->regs + offset);
  124. }
  125. /**
  126. * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
  127. * @xspi: Pointer to the cdns_spi structure
  128. *
  129. * On reset the SPI controller is configured to be in master mode, baud rate
  130. * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
  131. * to 1 and size of the word to be transferred as 8 bit.
  132. * This function initializes the SPI controller to disable and clear all the
  133. * interrupts, enable manual slave select and manual start, deselect all the
  134. * chip select lines, and enable the SPI controller.
  135. */
  136. static void cdns_spi_init_hw(struct cdns_spi *xspi)
  137. {
  138. u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
  139. if (xspi->is_decoded_cs)
  140. ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
  141. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
  142. cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
  143. /* Clear the RX FIFO */
  144. while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
  145. cdns_spi_read(xspi, CDNS_SPI_RXD);
  146. cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
  147. cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
  148. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
  149. }
  150. /**
  151. * cdns_spi_chipselect - Select or deselect the chip select line
  152. * @spi: Pointer to the spi_device structure
  153. * @is_high: Select(0) or deselect (1) the chip select line
  154. */
  155. static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
  156. {
  157. struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
  158. u32 ctrl_reg;
  159. ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
  160. if (is_high) {
  161. /* Deselect the slave */
  162. ctrl_reg |= CDNS_SPI_CR_SSCTRL;
  163. } else {
  164. /* Select the slave */
  165. ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
  166. if (!(xspi->is_decoded_cs))
  167. ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
  168. CDNS_SPI_SS_SHIFT) &
  169. CDNS_SPI_CR_SSCTRL;
  170. else
  171. ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
  172. CDNS_SPI_CR_SSCTRL;
  173. }
  174. cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
  175. }
  176. /**
  177. * cdns_spi_config_clock_mode - Sets clock polarity and phase
  178. * @spi: Pointer to the spi_device structure
  179. *
  180. * Sets the requested clock polarity and phase.
  181. */
  182. static void cdns_spi_config_clock_mode(struct spi_device *spi)
  183. {
  184. struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
  185. u32 ctrl_reg, new_ctrl_reg;
  186. new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
  187. ctrl_reg = new_ctrl_reg;
  188. /* Set the SPI clock phase and clock polarity */
  189. new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
  190. if (spi->mode & SPI_CPHA)
  191. new_ctrl_reg |= CDNS_SPI_CR_CPHA;
  192. if (spi->mode & SPI_CPOL)
  193. new_ctrl_reg |= CDNS_SPI_CR_CPOL;
  194. if (new_ctrl_reg != ctrl_reg) {
  195. /*
  196. * Just writing the CR register does not seem to apply the clock
  197. * setting changes. This is problematic when changing the clock
  198. * polarity as it will cause the SPI slave to see spurious clock
  199. * transitions. To workaround the issue toggle the ER register.
  200. */
  201. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
  202. cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
  203. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
  204. }
  205. }
  206. /**
  207. * cdns_spi_config_clock_freq - Sets clock frequency
  208. * @spi: Pointer to the spi_device structure
  209. * @transfer: Pointer to the spi_transfer structure which provides
  210. * information about next transfer setup parameters
  211. *
  212. * Sets the requested clock frequency.
  213. * Note: If the requested frequency is not an exact match with what can be
  214. * obtained using the prescalar value the driver sets the clock frequency which
  215. * is lower than the requested frequency (maximum lower) for the transfer. If
  216. * the requested frequency is higher or lower than that is supported by the SPI
  217. * controller the driver will set the highest or lowest frequency supported by
  218. * controller.
  219. */
  220. static void cdns_spi_config_clock_freq(struct spi_device *spi,
  221. struct spi_transfer *transfer)
  222. {
  223. struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
  224. u32 ctrl_reg, baud_rate_val;
  225. unsigned long frequency;
  226. frequency = xspi->clk_rate;
  227. ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
  228. /* Set the clock frequency */
  229. if (xspi->speed_hz != transfer->speed_hz) {
  230. /* first valid value is 1 */
  231. baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
  232. while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
  233. (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
  234. baud_rate_val++;
  235. ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
  236. ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
  237. xspi->speed_hz = frequency / (2 << baud_rate_val);
  238. }
  239. cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
  240. }
  241. /**
  242. * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
  243. * @spi: Pointer to the spi_device structure
  244. * @transfer: Pointer to the spi_transfer structure which provides
  245. * information about next transfer setup parameters
  246. *
  247. * Sets the operational mode of SPI controller for the next SPI transfer and
  248. * sets the requested clock frequency.
  249. *
  250. * Return: Always 0
  251. */
  252. static int cdns_spi_setup_transfer(struct spi_device *spi,
  253. struct spi_transfer *transfer)
  254. {
  255. struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
  256. cdns_spi_config_clock_freq(spi, transfer);
  257. dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
  258. __func__, spi->mode, spi->bits_per_word,
  259. xspi->speed_hz);
  260. return 0;
  261. }
  262. /**
  263. * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
  264. * @xspi: Pointer to the cdns_spi structure
  265. */
  266. static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
  267. {
  268. unsigned long trans_cnt = 0;
  269. while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
  270. (xspi->tx_bytes > 0)) {
  271. /* When xspi in busy condition, bytes may send failed,
  272. * then spi control did't work thoroughly, add one byte delay
  273. */
  274. if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
  275. CDNS_SPI_IXR_TXFULL)
  276. udelay(10);
  277. if (xspi->txbuf)
  278. cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
  279. else
  280. cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
  281. xspi->tx_bytes--;
  282. trans_cnt++;
  283. }
  284. }
  285. /**
  286. * cdns_spi_irq - Interrupt service routine of the SPI controller
  287. * @irq: IRQ number
  288. * @dev_id: Pointer to the xspi structure
  289. *
  290. * This function handles TX empty and Mode Fault interrupts only.
  291. * On TX empty interrupt this function reads the received data from RX FIFO and
  292. * fills the TX FIFO if there is any data remaining to be transferred.
  293. * On Mode Fault interrupt this function indicates that transfer is completed,
  294. * the SPI subsystem will identify the error as the remaining bytes to be
  295. * transferred is non-zero.
  296. *
  297. * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
  298. */
  299. static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
  300. {
  301. struct spi_master *master = dev_id;
  302. struct cdns_spi *xspi = spi_master_get_devdata(master);
  303. u32 intr_status, status;
  304. status = IRQ_NONE;
  305. intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
  306. cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
  307. if (intr_status & CDNS_SPI_IXR_MODF) {
  308. /* Indicate that transfer is completed, the SPI subsystem will
  309. * identify the error as the remaining bytes to be
  310. * transferred is non-zero
  311. */
  312. cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
  313. spi_finalize_current_transfer(master);
  314. status = IRQ_HANDLED;
  315. } else if (intr_status & CDNS_SPI_IXR_TXOW) {
  316. unsigned long trans_cnt;
  317. trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
  318. /* Read out the data from the RX FIFO */
  319. while (trans_cnt) {
  320. u8 data;
  321. data = cdns_spi_read(xspi, CDNS_SPI_RXD);
  322. if (xspi->rxbuf)
  323. *xspi->rxbuf++ = data;
  324. xspi->rx_bytes--;
  325. trans_cnt--;
  326. }
  327. if (xspi->tx_bytes) {
  328. /* There is more data to send */
  329. cdns_spi_fill_tx_fifo(xspi);
  330. } else {
  331. /* Transfer is completed */
  332. cdns_spi_write(xspi, CDNS_SPI_IDR,
  333. CDNS_SPI_IXR_DEFAULT);
  334. spi_finalize_current_transfer(master);
  335. }
  336. status = IRQ_HANDLED;
  337. }
  338. return status;
  339. }
  340. static int cdns_prepare_message(struct spi_master *master,
  341. struct spi_message *msg)
  342. {
  343. cdns_spi_config_clock_mode(msg->spi);
  344. return 0;
  345. }
  346. /**
  347. * cdns_transfer_one - Initiates the SPI transfer
  348. * @master: Pointer to spi_master structure
  349. * @spi: Pointer to the spi_device structure
  350. * @transfer: Pointer to the spi_transfer structure which provides
  351. * information about next transfer parameters
  352. *
  353. * This function fills the TX FIFO, starts the SPI transfer and
  354. * returns a positive transfer count so that core will wait for completion.
  355. *
  356. * Return: Number of bytes transferred in the last transfer
  357. */
  358. static int cdns_transfer_one(struct spi_master *master,
  359. struct spi_device *spi,
  360. struct spi_transfer *transfer)
  361. {
  362. struct cdns_spi *xspi = spi_master_get_devdata(master);
  363. xspi->txbuf = transfer->tx_buf;
  364. xspi->rxbuf = transfer->rx_buf;
  365. xspi->tx_bytes = transfer->len;
  366. xspi->rx_bytes = transfer->len;
  367. cdns_spi_setup_transfer(spi, transfer);
  368. cdns_spi_fill_tx_fifo(xspi);
  369. spi_transfer_delay_exec(transfer);
  370. cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
  371. return transfer->len;
  372. }
  373. /**
  374. * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
  375. * @master: Pointer to the spi_master structure which provides
  376. * information about the controller.
  377. *
  378. * This function enables SPI master controller.
  379. *
  380. * Return: 0 always
  381. */
  382. static int cdns_prepare_transfer_hardware(struct spi_master *master)
  383. {
  384. struct cdns_spi *xspi = spi_master_get_devdata(master);
  385. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
  386. return 0;
  387. }
  388. /**
  389. * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
  390. * @master: Pointer to the spi_master structure which provides
  391. * information about the controller.
  392. *
  393. * This function disables the SPI master controller.
  394. *
  395. * Return: 0 always
  396. */
  397. static int cdns_unprepare_transfer_hardware(struct spi_master *master)
  398. {
  399. struct cdns_spi *xspi = spi_master_get_devdata(master);
  400. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
  401. return 0;
  402. }
  403. /**
  404. * cdns_spi_probe - Probe method for the SPI driver
  405. * @pdev: Pointer to the platform_device structure
  406. *
  407. * This function initializes the driver data structures and the hardware.
  408. *
  409. * Return: 0 on success and error value on error
  410. */
  411. static int cdns_spi_probe(struct platform_device *pdev)
  412. {
  413. int ret = 0, irq;
  414. struct spi_master *master;
  415. struct cdns_spi *xspi;
  416. u32 num_cs;
  417. master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
  418. if (!master)
  419. return -ENOMEM;
  420. xspi = spi_master_get_devdata(master);
  421. master->dev.of_node = pdev->dev.of_node;
  422. platform_set_drvdata(pdev, master);
  423. xspi->regs = devm_platform_ioremap_resource(pdev, 0);
  424. if (IS_ERR(xspi->regs)) {
  425. ret = PTR_ERR(xspi->regs);
  426. goto remove_master;
  427. }
  428. xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
  429. if (IS_ERR(xspi->pclk)) {
  430. dev_err(&pdev->dev, "pclk clock not found.\n");
  431. ret = PTR_ERR(xspi->pclk);
  432. goto remove_master;
  433. }
  434. xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
  435. if (IS_ERR(xspi->ref_clk)) {
  436. dev_err(&pdev->dev, "ref_clk clock not found.\n");
  437. ret = PTR_ERR(xspi->ref_clk);
  438. goto remove_master;
  439. }
  440. ret = clk_prepare_enable(xspi->pclk);
  441. if (ret) {
  442. dev_err(&pdev->dev, "Unable to enable APB clock.\n");
  443. goto remove_master;
  444. }
  445. ret = clk_prepare_enable(xspi->ref_clk);
  446. if (ret) {
  447. dev_err(&pdev->dev, "Unable to enable device clock.\n");
  448. goto clk_dis_apb;
  449. }
  450. pm_runtime_use_autosuspend(&pdev->dev);
  451. pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
  452. pm_runtime_get_noresume(&pdev->dev);
  453. pm_runtime_set_active(&pdev->dev);
  454. pm_runtime_enable(&pdev->dev);
  455. ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
  456. if (ret < 0)
  457. master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
  458. else
  459. master->num_chipselect = num_cs;
  460. ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
  461. &xspi->is_decoded_cs);
  462. if (ret < 0)
  463. xspi->is_decoded_cs = 0;
  464. /* SPI controller initializations */
  465. cdns_spi_init_hw(xspi);
  466. irq = platform_get_irq(pdev, 0);
  467. if (irq <= 0) {
  468. ret = -ENXIO;
  469. goto clk_dis_all;
  470. }
  471. ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
  472. 0, pdev->name, master);
  473. if (ret != 0) {
  474. ret = -ENXIO;
  475. dev_err(&pdev->dev, "request_irq failed\n");
  476. goto clk_dis_all;
  477. }
  478. master->use_gpio_descriptors = true;
  479. master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
  480. master->prepare_message = cdns_prepare_message;
  481. master->transfer_one = cdns_transfer_one;
  482. master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
  483. master->set_cs = cdns_spi_chipselect;
  484. master->auto_runtime_pm = true;
  485. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  486. xspi->clk_rate = clk_get_rate(xspi->ref_clk);
  487. /* Set to default valid value */
  488. master->max_speed_hz = xspi->clk_rate / 4;
  489. xspi->speed_hz = master->max_speed_hz;
  490. master->bits_per_word_mask = SPI_BPW_MASK(8);
  491. pm_runtime_mark_last_busy(&pdev->dev);
  492. pm_runtime_put_autosuspend(&pdev->dev);
  493. ret = spi_register_master(master);
  494. if (ret) {
  495. dev_err(&pdev->dev, "spi_register_master failed\n");
  496. goto clk_dis_all;
  497. }
  498. return ret;
  499. clk_dis_all:
  500. pm_runtime_set_suspended(&pdev->dev);
  501. pm_runtime_disable(&pdev->dev);
  502. clk_disable_unprepare(xspi->ref_clk);
  503. clk_dis_apb:
  504. clk_disable_unprepare(xspi->pclk);
  505. remove_master:
  506. spi_master_put(master);
  507. return ret;
  508. }
  509. /**
  510. * cdns_spi_remove - Remove method for the SPI driver
  511. * @pdev: Pointer to the platform_device structure
  512. *
  513. * This function is called if a device is physically removed from the system or
  514. * if the driver module is being unloaded. It frees all resources allocated to
  515. * the device.
  516. *
  517. * Return: 0 on success and error value on error
  518. */
  519. static int cdns_spi_remove(struct platform_device *pdev)
  520. {
  521. struct spi_master *master = platform_get_drvdata(pdev);
  522. struct cdns_spi *xspi = spi_master_get_devdata(master);
  523. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
  524. clk_disable_unprepare(xspi->ref_clk);
  525. clk_disable_unprepare(xspi->pclk);
  526. pm_runtime_set_suspended(&pdev->dev);
  527. pm_runtime_disable(&pdev->dev);
  528. spi_unregister_master(master);
  529. return 0;
  530. }
  531. /**
  532. * cdns_spi_suspend - Suspend method for the SPI driver
  533. * @dev: Address of the platform_device structure
  534. *
  535. * This function disables the SPI controller and
  536. * changes the driver state to "suspend"
  537. *
  538. * Return: 0 on success and error value on error
  539. */
  540. static int __maybe_unused cdns_spi_suspend(struct device *dev)
  541. {
  542. struct spi_master *master = dev_get_drvdata(dev);
  543. return spi_master_suspend(master);
  544. }
  545. /**
  546. * cdns_spi_resume - Resume method for the SPI driver
  547. * @dev: Address of the platform_device structure
  548. *
  549. * This function changes the driver state to "ready"
  550. *
  551. * Return: 0 on success and error value on error
  552. */
  553. static int __maybe_unused cdns_spi_resume(struct device *dev)
  554. {
  555. struct spi_master *master = dev_get_drvdata(dev);
  556. struct cdns_spi *xspi = spi_master_get_devdata(master);
  557. cdns_spi_init_hw(xspi);
  558. return spi_master_resume(master);
  559. }
  560. /**
  561. * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
  562. * @dev: Address of the platform_device structure
  563. *
  564. * This function enables the clocks
  565. *
  566. * Return: 0 on success and error value on error
  567. */
  568. static int __maybe_unused cnds_runtime_resume(struct device *dev)
  569. {
  570. struct spi_master *master = dev_get_drvdata(dev);
  571. struct cdns_spi *xspi = spi_master_get_devdata(master);
  572. int ret;
  573. ret = clk_prepare_enable(xspi->pclk);
  574. if (ret) {
  575. dev_err(dev, "Cannot enable APB clock.\n");
  576. return ret;
  577. }
  578. ret = clk_prepare_enable(xspi->ref_clk);
  579. if (ret) {
  580. dev_err(dev, "Cannot enable device clock.\n");
  581. clk_disable_unprepare(xspi->pclk);
  582. return ret;
  583. }
  584. return 0;
  585. }
  586. /**
  587. * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
  588. * @dev: Address of the platform_device structure
  589. *
  590. * This function disables the clocks
  591. *
  592. * Return: Always 0
  593. */
  594. static int __maybe_unused cnds_runtime_suspend(struct device *dev)
  595. {
  596. struct spi_master *master = dev_get_drvdata(dev);
  597. struct cdns_spi *xspi = spi_master_get_devdata(master);
  598. clk_disable_unprepare(xspi->ref_clk);
  599. clk_disable_unprepare(xspi->pclk);
  600. return 0;
  601. }
  602. static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
  603. SET_RUNTIME_PM_OPS(cnds_runtime_suspend,
  604. cnds_runtime_resume, NULL)
  605. SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
  606. };
  607. static const struct of_device_id cdns_spi_of_match[] = {
  608. { .compatible = "xlnx,zynq-spi-r1p6" },
  609. { .compatible = "cdns,spi-r1p6" },
  610. { /* end of table */ }
  611. };
  612. MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
  613. /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
  614. static struct platform_driver cdns_spi_driver = {
  615. .probe = cdns_spi_probe,
  616. .remove = cdns_spi_remove,
  617. .driver = {
  618. .name = CDNS_SPI_NAME,
  619. .of_match_table = cdns_spi_of_match,
  620. .pm = &cdns_spi_dev_pm_ops,
  621. },
  622. };
  623. module_platform_driver(cdns_spi_driver);
  624. MODULE_AUTHOR("Xilinx, Inc.");
  625. MODULE_DESCRIPTION("Cadence SPI driver");
  626. MODULE_LICENSE("GPL");