spi-cadence-quadspi.c 37 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // Driver for Cadence QSPI Controller
  4. //
  5. // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
  6. // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
  7. // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
  8. #include <linux/clk.h>
  9. #include <linux/completion.h>
  10. #include <linux/delay.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/err.h>
  14. #include <linux/errno.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/iopoll.h>
  18. #include <linux/jiffies.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/of_device.h>
  22. #include <linux/of.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/pm_runtime.h>
  25. #include <linux/reset.h>
  26. #include <linux/sched.h>
  27. #include <linux/spi/spi.h>
  28. #include <linux/spi/spi-mem.h>
  29. #include <linux/timer.h>
  30. #define CQSPI_NAME "cadence-qspi"
  31. #define CQSPI_MAX_CHIPSELECT 16
  32. /* Quirks */
  33. #define CQSPI_NEEDS_WR_DELAY BIT(0)
  34. #define CQSPI_DISABLE_DAC_MODE BIT(1)
  35. /* Capabilities */
  36. #define CQSPI_SUPPORTS_OCTAL BIT(0)
  37. struct cqspi_st;
  38. struct cqspi_flash_pdata {
  39. struct cqspi_st *cqspi;
  40. u32 clk_rate;
  41. u32 read_delay;
  42. u32 tshsl_ns;
  43. u32 tsd2d_ns;
  44. u32 tchsh_ns;
  45. u32 tslch_ns;
  46. u8 inst_width;
  47. u8 addr_width;
  48. u8 data_width;
  49. u8 cs;
  50. };
  51. struct cqspi_st {
  52. struct platform_device *pdev;
  53. struct clk *clk;
  54. unsigned int sclk;
  55. void __iomem *iobase;
  56. void __iomem *ahb_base;
  57. resource_size_t ahb_size;
  58. struct completion transfer_complete;
  59. struct dma_chan *rx_chan;
  60. struct completion rx_dma_complete;
  61. dma_addr_t mmap_phys_base;
  62. int current_cs;
  63. unsigned long master_ref_clk_hz;
  64. bool is_decoded_cs;
  65. u32 fifo_depth;
  66. u32 fifo_width;
  67. bool rclk_en;
  68. u32 trigger_address;
  69. u32 wr_delay;
  70. bool use_direct_mode;
  71. struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  72. };
  73. struct cqspi_driver_platdata {
  74. u32 hwcaps_mask;
  75. u8 quirks;
  76. };
  77. /* Operation timeout value */
  78. #define CQSPI_TIMEOUT_MS 500
  79. #define CQSPI_READ_TIMEOUT_MS 10
  80. /* Instruction type */
  81. #define CQSPI_INST_TYPE_SINGLE 0
  82. #define CQSPI_INST_TYPE_DUAL 1
  83. #define CQSPI_INST_TYPE_QUAD 2
  84. #define CQSPI_INST_TYPE_OCTAL 3
  85. #define CQSPI_DUMMY_CLKS_PER_BYTE 8
  86. #define CQSPI_DUMMY_BYTES_MAX 4
  87. #define CQSPI_DUMMY_CLKS_MAX 31
  88. #define CQSPI_STIG_DATA_LEN_MAX 8
  89. /* Register map */
  90. #define CQSPI_REG_CONFIG 0x00
  91. #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
  92. #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
  93. #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
  94. #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
  95. #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
  96. #define CQSPI_REG_CONFIG_BAUD_LSB 19
  97. #define CQSPI_REG_CONFIG_IDLE_LSB 31
  98. #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
  99. #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
  100. #define CQSPI_REG_RD_INSTR 0x04
  101. #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
  102. #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
  103. #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
  104. #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
  105. #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
  106. #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
  107. #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
  108. #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
  109. #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
  110. #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
  111. #define CQSPI_REG_WR_INSTR 0x08
  112. #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
  113. #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
  114. #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
  115. #define CQSPI_REG_DELAY 0x0C
  116. #define CQSPI_REG_DELAY_TSLCH_LSB 0
  117. #define CQSPI_REG_DELAY_TCHSH_LSB 8
  118. #define CQSPI_REG_DELAY_TSD2D_LSB 16
  119. #define CQSPI_REG_DELAY_TSHSL_LSB 24
  120. #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
  121. #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
  122. #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
  123. #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
  124. #define CQSPI_REG_READCAPTURE 0x10
  125. #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
  126. #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
  127. #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
  128. #define CQSPI_REG_SIZE 0x14
  129. #define CQSPI_REG_SIZE_ADDRESS_LSB 0
  130. #define CQSPI_REG_SIZE_PAGE_LSB 4
  131. #define CQSPI_REG_SIZE_BLOCK_LSB 16
  132. #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
  133. #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
  134. #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
  135. #define CQSPI_REG_SRAMPARTITION 0x18
  136. #define CQSPI_REG_INDIRECTTRIGGER 0x1C
  137. #define CQSPI_REG_DMA 0x20
  138. #define CQSPI_REG_DMA_SINGLE_LSB 0
  139. #define CQSPI_REG_DMA_BURST_LSB 8
  140. #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
  141. #define CQSPI_REG_DMA_BURST_MASK 0xFF
  142. #define CQSPI_REG_REMAP 0x24
  143. #define CQSPI_REG_MODE_BIT 0x28
  144. #define CQSPI_REG_SDRAMLEVEL 0x2C
  145. #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
  146. #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
  147. #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
  148. #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
  149. #define CQSPI_REG_IRQSTATUS 0x40
  150. #define CQSPI_REG_IRQMASK 0x44
  151. #define CQSPI_REG_INDIRECTRD 0x60
  152. #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
  153. #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
  154. #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
  155. #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
  156. #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
  157. #define CQSPI_REG_INDIRECTRDBYTES 0x6C
  158. #define CQSPI_REG_CMDCTRL 0x90
  159. #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
  160. #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
  161. #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
  162. #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
  163. #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
  164. #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
  165. #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
  166. #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
  167. #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
  168. #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
  169. #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
  170. #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
  171. #define CQSPI_REG_INDIRECTWR 0x70
  172. #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
  173. #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
  174. #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
  175. #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
  176. #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
  177. #define CQSPI_REG_INDIRECTWRBYTES 0x7C
  178. #define CQSPI_REG_CMDADDRESS 0x94
  179. #define CQSPI_REG_CMDREADDATALOWER 0xA0
  180. #define CQSPI_REG_CMDREADDATAUPPER 0xA4
  181. #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
  182. #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
  183. /* Interrupt status bits */
  184. #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
  185. #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
  186. #define CQSPI_REG_IRQ_IND_COMP BIT(2)
  187. #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
  188. #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
  189. #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
  190. #define CQSPI_REG_IRQ_WATERMARK BIT(6)
  191. #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
  192. #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
  193. CQSPI_REG_IRQ_IND_SRAM_FULL | \
  194. CQSPI_REG_IRQ_IND_COMP)
  195. #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
  196. CQSPI_REG_IRQ_WATERMARK | \
  197. CQSPI_REG_IRQ_UNDERFLOW)
  198. #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
  199. static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
  200. {
  201. u32 val;
  202. return readl_relaxed_poll_timeout(reg, val,
  203. (((clr ? ~val : val) & mask) == mask),
  204. 10, CQSPI_TIMEOUT_MS * 1000);
  205. }
  206. static bool cqspi_is_idle(struct cqspi_st *cqspi)
  207. {
  208. u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
  209. return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
  210. }
  211. static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
  212. {
  213. u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
  214. reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
  215. return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
  216. }
  217. static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
  218. {
  219. struct cqspi_st *cqspi = dev;
  220. unsigned int irq_status;
  221. /* Read interrupt status */
  222. irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
  223. /* Clear interrupt */
  224. writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
  225. irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
  226. if (irq_status)
  227. complete(&cqspi->transfer_complete);
  228. return IRQ_HANDLED;
  229. }
  230. static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
  231. {
  232. u32 rdreg = 0;
  233. rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
  234. rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
  235. rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
  236. return rdreg;
  237. }
  238. static int cqspi_wait_idle(struct cqspi_st *cqspi)
  239. {
  240. const unsigned int poll_idle_retry = 3;
  241. unsigned int count = 0;
  242. unsigned long timeout;
  243. timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
  244. while (1) {
  245. /*
  246. * Read few times in succession to ensure the controller
  247. * is indeed idle, that is, the bit does not transition
  248. * low again.
  249. */
  250. if (cqspi_is_idle(cqspi))
  251. count++;
  252. else
  253. count = 0;
  254. if (count >= poll_idle_retry)
  255. return 0;
  256. if (time_after(jiffies, timeout)) {
  257. /* Timeout, in busy mode. */
  258. dev_err(&cqspi->pdev->dev,
  259. "QSPI is still busy after %dms timeout.\n",
  260. CQSPI_TIMEOUT_MS);
  261. return -ETIMEDOUT;
  262. }
  263. cpu_relax();
  264. }
  265. }
  266. static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
  267. {
  268. void __iomem *reg_base = cqspi->iobase;
  269. int ret;
  270. /* Write the CMDCTRL without start execution. */
  271. writel(reg, reg_base + CQSPI_REG_CMDCTRL);
  272. /* Start execute */
  273. reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
  274. writel(reg, reg_base + CQSPI_REG_CMDCTRL);
  275. /* Polling for completion. */
  276. ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
  277. CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
  278. if (ret) {
  279. dev_err(&cqspi->pdev->dev,
  280. "Flash command execution timed out.\n");
  281. return ret;
  282. }
  283. /* Polling QSPI idle status. */
  284. return cqspi_wait_idle(cqspi);
  285. }
  286. static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
  287. const struct spi_mem_op *op)
  288. {
  289. struct cqspi_st *cqspi = f_pdata->cqspi;
  290. void __iomem *reg_base = cqspi->iobase;
  291. u8 *rxbuf = op->data.buf.in;
  292. u8 opcode = op->cmd.opcode;
  293. size_t n_rx = op->data.nbytes;
  294. unsigned int rdreg;
  295. unsigned int reg;
  296. size_t read_len;
  297. int status;
  298. if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
  299. dev_err(&cqspi->pdev->dev,
  300. "Invalid input argument, len %zu rxbuf 0x%p\n",
  301. n_rx, rxbuf);
  302. return -EINVAL;
  303. }
  304. reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
  305. rdreg = cqspi_calc_rdreg(f_pdata);
  306. writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
  307. reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
  308. /* 0 means 1 byte. */
  309. reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
  310. << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
  311. status = cqspi_exec_flash_cmd(cqspi, reg);
  312. if (status)
  313. return status;
  314. reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
  315. /* Put the read value into rx_buf */
  316. read_len = (n_rx > 4) ? 4 : n_rx;
  317. memcpy(rxbuf, &reg, read_len);
  318. rxbuf += read_len;
  319. if (n_rx > 4) {
  320. reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
  321. read_len = n_rx - read_len;
  322. memcpy(rxbuf, &reg, read_len);
  323. }
  324. return 0;
  325. }
  326. static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
  327. const struct spi_mem_op *op)
  328. {
  329. struct cqspi_st *cqspi = f_pdata->cqspi;
  330. void __iomem *reg_base = cqspi->iobase;
  331. const u8 opcode = op->cmd.opcode;
  332. const u8 *txbuf = op->data.buf.out;
  333. size_t n_tx = op->data.nbytes;
  334. unsigned int reg;
  335. unsigned int data;
  336. size_t write_len;
  337. if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
  338. dev_err(&cqspi->pdev->dev,
  339. "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
  340. n_tx, txbuf);
  341. return -EINVAL;
  342. }
  343. reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
  344. if (op->addr.nbytes) {
  345. reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
  346. reg |= ((op->addr.nbytes - 1) &
  347. CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
  348. << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
  349. writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
  350. }
  351. if (n_tx) {
  352. reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
  353. reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
  354. << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
  355. data = 0;
  356. write_len = (n_tx > 4) ? 4 : n_tx;
  357. memcpy(&data, txbuf, write_len);
  358. txbuf += write_len;
  359. writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
  360. if (n_tx > 4) {
  361. data = 0;
  362. write_len = n_tx - 4;
  363. memcpy(&data, txbuf, write_len);
  364. writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
  365. }
  366. }
  367. return cqspi_exec_flash_cmd(cqspi, reg);
  368. }
  369. static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
  370. const struct spi_mem_op *op)
  371. {
  372. struct cqspi_st *cqspi = f_pdata->cqspi;
  373. void __iomem *reg_base = cqspi->iobase;
  374. unsigned int dummy_clk = 0;
  375. unsigned int reg;
  376. reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
  377. reg |= cqspi_calc_rdreg(f_pdata);
  378. /* Setup dummy clock cycles */
  379. dummy_clk = op->dummy.nbytes * 8;
  380. if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
  381. return -EOPNOTSUPP;
  382. if (dummy_clk)
  383. reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
  384. << CQSPI_REG_RD_INSTR_DUMMY_LSB;
  385. writel(reg, reg_base + CQSPI_REG_RD_INSTR);
  386. /* Set address width */
  387. reg = readl(reg_base + CQSPI_REG_SIZE);
  388. reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
  389. reg |= (op->addr.nbytes - 1);
  390. writel(reg, reg_base + CQSPI_REG_SIZE);
  391. return 0;
  392. }
  393. static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
  394. u8 *rxbuf, loff_t from_addr,
  395. const size_t n_rx)
  396. {
  397. struct cqspi_st *cqspi = f_pdata->cqspi;
  398. struct device *dev = &cqspi->pdev->dev;
  399. void __iomem *reg_base = cqspi->iobase;
  400. void __iomem *ahb_base = cqspi->ahb_base;
  401. unsigned int remaining = n_rx;
  402. unsigned int mod_bytes = n_rx % 4;
  403. unsigned int bytes_to_read = 0;
  404. u8 *rxbuf_end = rxbuf + n_rx;
  405. int ret = 0;
  406. writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
  407. writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
  408. /* Clear all interrupts. */
  409. writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
  410. writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
  411. reinit_completion(&cqspi->transfer_complete);
  412. writel(CQSPI_REG_INDIRECTRD_START_MASK,
  413. reg_base + CQSPI_REG_INDIRECTRD);
  414. while (remaining > 0) {
  415. if (!wait_for_completion_timeout(&cqspi->transfer_complete,
  416. msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
  417. ret = -ETIMEDOUT;
  418. bytes_to_read = cqspi_get_rd_sram_level(cqspi);
  419. if (ret && bytes_to_read == 0) {
  420. dev_err(dev, "Indirect read timeout, no bytes\n");
  421. goto failrd;
  422. }
  423. while (bytes_to_read != 0) {
  424. unsigned int word_remain = round_down(remaining, 4);
  425. bytes_to_read *= cqspi->fifo_width;
  426. bytes_to_read = bytes_to_read > remaining ?
  427. remaining : bytes_to_read;
  428. bytes_to_read = round_down(bytes_to_read, 4);
  429. /* Read 4 byte word chunks then single bytes */
  430. if (bytes_to_read) {
  431. ioread32_rep(ahb_base, rxbuf,
  432. (bytes_to_read / 4));
  433. } else if (!word_remain && mod_bytes) {
  434. unsigned int temp = ioread32(ahb_base);
  435. bytes_to_read = mod_bytes;
  436. memcpy(rxbuf, &temp, min((unsigned int)
  437. (rxbuf_end - rxbuf),
  438. bytes_to_read));
  439. }
  440. rxbuf += bytes_to_read;
  441. remaining -= bytes_to_read;
  442. bytes_to_read = cqspi_get_rd_sram_level(cqspi);
  443. }
  444. if (remaining > 0)
  445. reinit_completion(&cqspi->transfer_complete);
  446. }
  447. /* Check indirect done status */
  448. ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
  449. CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
  450. if (ret) {
  451. dev_err(dev, "Indirect read completion error (%i)\n", ret);
  452. goto failrd;
  453. }
  454. /* Disable interrupt */
  455. writel(0, reg_base + CQSPI_REG_IRQMASK);
  456. /* Clear indirect completion status */
  457. writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
  458. return 0;
  459. failrd:
  460. /* Disable interrupt */
  461. writel(0, reg_base + CQSPI_REG_IRQMASK);
  462. /* Cancel the indirect read */
  463. writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
  464. reg_base + CQSPI_REG_INDIRECTRD);
  465. return ret;
  466. }
  467. static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
  468. const struct spi_mem_op *op)
  469. {
  470. unsigned int reg;
  471. struct cqspi_st *cqspi = f_pdata->cqspi;
  472. void __iomem *reg_base = cqspi->iobase;
  473. /* Set opcode. */
  474. reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
  475. writel(reg, reg_base + CQSPI_REG_WR_INSTR);
  476. reg = cqspi_calc_rdreg(f_pdata);
  477. writel(reg, reg_base + CQSPI_REG_RD_INSTR);
  478. reg = readl(reg_base + CQSPI_REG_SIZE);
  479. reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
  480. reg |= (op->addr.nbytes - 1);
  481. writel(reg, reg_base + CQSPI_REG_SIZE);
  482. return 0;
  483. }
  484. static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
  485. loff_t to_addr, const u8 *txbuf,
  486. const size_t n_tx)
  487. {
  488. struct cqspi_st *cqspi = f_pdata->cqspi;
  489. struct device *dev = &cqspi->pdev->dev;
  490. void __iomem *reg_base = cqspi->iobase;
  491. unsigned int remaining = n_tx;
  492. unsigned int write_bytes;
  493. int ret;
  494. writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
  495. writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
  496. /* Clear all interrupts. */
  497. writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
  498. writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
  499. reinit_completion(&cqspi->transfer_complete);
  500. writel(CQSPI_REG_INDIRECTWR_START_MASK,
  501. reg_base + CQSPI_REG_INDIRECTWR);
  502. /*
  503. * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
  504. * Controller programming sequence, couple of cycles of
  505. * QSPI_REF_CLK delay is required for the above bit to
  506. * be internally synchronized by the QSPI module. Provide 5
  507. * cycles of delay.
  508. */
  509. if (cqspi->wr_delay)
  510. ndelay(cqspi->wr_delay);
  511. while (remaining > 0) {
  512. size_t write_words, mod_bytes;
  513. write_bytes = remaining;
  514. write_words = write_bytes / 4;
  515. mod_bytes = write_bytes % 4;
  516. /* Write 4 bytes at a time then single bytes. */
  517. if (write_words) {
  518. iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
  519. txbuf += (write_words * 4);
  520. }
  521. if (mod_bytes) {
  522. unsigned int temp = 0xFFFFFFFF;
  523. memcpy(&temp, txbuf, mod_bytes);
  524. iowrite32(temp, cqspi->ahb_base);
  525. txbuf += mod_bytes;
  526. }
  527. if (!wait_for_completion_timeout(&cqspi->transfer_complete,
  528. msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
  529. dev_err(dev, "Indirect write timeout\n");
  530. ret = -ETIMEDOUT;
  531. goto failwr;
  532. }
  533. remaining -= write_bytes;
  534. if (remaining > 0)
  535. reinit_completion(&cqspi->transfer_complete);
  536. }
  537. /* Check indirect done status */
  538. ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
  539. CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
  540. if (ret) {
  541. dev_err(dev, "Indirect write completion error (%i)\n", ret);
  542. goto failwr;
  543. }
  544. /* Disable interrupt. */
  545. writel(0, reg_base + CQSPI_REG_IRQMASK);
  546. /* Clear indirect completion status */
  547. writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
  548. cqspi_wait_idle(cqspi);
  549. return 0;
  550. failwr:
  551. /* Disable interrupt. */
  552. writel(0, reg_base + CQSPI_REG_IRQMASK);
  553. /* Cancel the indirect write */
  554. writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
  555. reg_base + CQSPI_REG_INDIRECTWR);
  556. return ret;
  557. }
  558. static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
  559. {
  560. struct cqspi_st *cqspi = f_pdata->cqspi;
  561. void __iomem *reg_base = cqspi->iobase;
  562. unsigned int chip_select = f_pdata->cs;
  563. unsigned int reg;
  564. reg = readl(reg_base + CQSPI_REG_CONFIG);
  565. if (cqspi->is_decoded_cs) {
  566. reg |= CQSPI_REG_CONFIG_DECODE_MASK;
  567. } else {
  568. reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
  569. /* Convert CS if without decoder.
  570. * CS0 to 4b'1110
  571. * CS1 to 4b'1101
  572. * CS2 to 4b'1011
  573. * CS3 to 4b'0111
  574. */
  575. chip_select = 0xF & ~(1 << chip_select);
  576. }
  577. reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
  578. << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
  579. reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
  580. << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
  581. writel(reg, reg_base + CQSPI_REG_CONFIG);
  582. }
  583. static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
  584. const unsigned int ns_val)
  585. {
  586. unsigned int ticks;
  587. ticks = ref_clk_hz / 1000; /* kHz */
  588. ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
  589. return ticks;
  590. }
  591. static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
  592. {
  593. struct cqspi_st *cqspi = f_pdata->cqspi;
  594. void __iomem *iobase = cqspi->iobase;
  595. const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
  596. unsigned int tshsl, tchsh, tslch, tsd2d;
  597. unsigned int reg;
  598. unsigned int tsclk;
  599. /* calculate the number of ref ticks for one sclk tick */
  600. tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
  601. tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
  602. /* this particular value must be at least one sclk */
  603. if (tshsl < tsclk)
  604. tshsl = tsclk;
  605. tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
  606. tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
  607. tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
  608. reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
  609. << CQSPI_REG_DELAY_TSHSL_LSB;
  610. reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
  611. << CQSPI_REG_DELAY_TCHSH_LSB;
  612. reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
  613. << CQSPI_REG_DELAY_TSLCH_LSB;
  614. reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
  615. << CQSPI_REG_DELAY_TSD2D_LSB;
  616. writel(reg, iobase + CQSPI_REG_DELAY);
  617. }
  618. static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
  619. {
  620. const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
  621. void __iomem *reg_base = cqspi->iobase;
  622. u32 reg, div;
  623. /* Recalculate the baudrate divisor based on QSPI specification. */
  624. div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
  625. reg = readl(reg_base + CQSPI_REG_CONFIG);
  626. reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
  627. reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
  628. writel(reg, reg_base + CQSPI_REG_CONFIG);
  629. }
  630. static void cqspi_readdata_capture(struct cqspi_st *cqspi,
  631. const bool bypass,
  632. const unsigned int delay)
  633. {
  634. void __iomem *reg_base = cqspi->iobase;
  635. unsigned int reg;
  636. reg = readl(reg_base + CQSPI_REG_READCAPTURE);
  637. if (bypass)
  638. reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
  639. else
  640. reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
  641. reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
  642. << CQSPI_REG_READCAPTURE_DELAY_LSB);
  643. reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
  644. << CQSPI_REG_READCAPTURE_DELAY_LSB;
  645. writel(reg, reg_base + CQSPI_REG_READCAPTURE);
  646. }
  647. static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
  648. {
  649. void __iomem *reg_base = cqspi->iobase;
  650. unsigned int reg;
  651. reg = readl(reg_base + CQSPI_REG_CONFIG);
  652. if (enable)
  653. reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
  654. else
  655. reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
  656. writel(reg, reg_base + CQSPI_REG_CONFIG);
  657. }
  658. static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
  659. unsigned long sclk)
  660. {
  661. struct cqspi_st *cqspi = f_pdata->cqspi;
  662. int switch_cs = (cqspi->current_cs != f_pdata->cs);
  663. int switch_ck = (cqspi->sclk != sclk);
  664. if (switch_cs || switch_ck)
  665. cqspi_controller_enable(cqspi, 0);
  666. /* Switch chip select. */
  667. if (switch_cs) {
  668. cqspi->current_cs = f_pdata->cs;
  669. cqspi_chipselect(f_pdata);
  670. }
  671. /* Setup baudrate divisor and delays */
  672. if (switch_ck) {
  673. cqspi->sclk = sclk;
  674. cqspi_config_baudrate_div(cqspi);
  675. cqspi_delay(f_pdata);
  676. cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
  677. f_pdata->read_delay);
  678. }
  679. if (switch_cs || switch_ck)
  680. cqspi_controller_enable(cqspi, 1);
  681. }
  682. static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
  683. const struct spi_mem_op *op)
  684. {
  685. f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
  686. f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
  687. f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
  688. if (op->data.dir == SPI_MEM_DATA_IN) {
  689. switch (op->data.buswidth) {
  690. case 1:
  691. f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
  692. break;
  693. case 2:
  694. f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
  695. break;
  696. case 4:
  697. f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
  698. break;
  699. case 8:
  700. f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
  701. break;
  702. default:
  703. return -EINVAL;
  704. }
  705. }
  706. return 0;
  707. }
  708. static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
  709. const struct spi_mem_op *op)
  710. {
  711. struct cqspi_st *cqspi = f_pdata->cqspi;
  712. loff_t to = op->addr.val;
  713. size_t len = op->data.nbytes;
  714. const u_char *buf = op->data.buf.out;
  715. int ret;
  716. ret = cqspi_set_protocol(f_pdata, op);
  717. if (ret)
  718. return ret;
  719. ret = cqspi_write_setup(f_pdata, op);
  720. if (ret)
  721. return ret;
  722. if (cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) {
  723. memcpy_toio(cqspi->ahb_base + to, buf, len);
  724. return cqspi_wait_idle(cqspi);
  725. }
  726. return cqspi_indirect_write_execute(f_pdata, to, buf, len);
  727. }
  728. static void cqspi_rx_dma_callback(void *param)
  729. {
  730. struct cqspi_st *cqspi = param;
  731. complete(&cqspi->rx_dma_complete);
  732. }
  733. static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
  734. u_char *buf, loff_t from, size_t len)
  735. {
  736. struct cqspi_st *cqspi = f_pdata->cqspi;
  737. struct device *dev = &cqspi->pdev->dev;
  738. enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
  739. dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
  740. int ret = 0;
  741. struct dma_async_tx_descriptor *tx;
  742. dma_cookie_t cookie;
  743. dma_addr_t dma_dst;
  744. struct device *ddev;
  745. if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
  746. memcpy_fromio(buf, cqspi->ahb_base + from, len);
  747. return 0;
  748. }
  749. ddev = cqspi->rx_chan->device->dev;
  750. dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
  751. if (dma_mapping_error(ddev, dma_dst)) {
  752. dev_err(dev, "dma mapping failed\n");
  753. return -ENOMEM;
  754. }
  755. tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
  756. len, flags);
  757. if (!tx) {
  758. dev_err(dev, "device_prep_dma_memcpy error\n");
  759. ret = -EIO;
  760. goto err_unmap;
  761. }
  762. tx->callback = cqspi_rx_dma_callback;
  763. tx->callback_param = cqspi;
  764. cookie = tx->tx_submit(tx);
  765. reinit_completion(&cqspi->rx_dma_complete);
  766. ret = dma_submit_error(cookie);
  767. if (ret) {
  768. dev_err(dev, "dma_submit_error %d\n", cookie);
  769. ret = -EIO;
  770. goto err_unmap;
  771. }
  772. dma_async_issue_pending(cqspi->rx_chan);
  773. if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
  774. msecs_to_jiffies(len))) {
  775. dmaengine_terminate_sync(cqspi->rx_chan);
  776. dev_err(dev, "DMA wait_for_completion_timeout\n");
  777. ret = -ETIMEDOUT;
  778. goto err_unmap;
  779. }
  780. err_unmap:
  781. dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
  782. return ret;
  783. }
  784. static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
  785. const struct spi_mem_op *op)
  786. {
  787. struct cqspi_st *cqspi = f_pdata->cqspi;
  788. loff_t from = op->addr.val;
  789. size_t len = op->data.nbytes;
  790. u_char *buf = op->data.buf.in;
  791. int ret;
  792. ret = cqspi_set_protocol(f_pdata, op);
  793. if (ret)
  794. return ret;
  795. ret = cqspi_read_setup(f_pdata, op);
  796. if (ret)
  797. return ret;
  798. if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
  799. return cqspi_direct_read_execute(f_pdata, buf, from, len);
  800. return cqspi_indirect_read_execute(f_pdata, buf, from, len);
  801. }
  802. static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
  803. {
  804. struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
  805. struct cqspi_flash_pdata *f_pdata;
  806. f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
  807. cqspi_configure(f_pdata, mem->spi->max_speed_hz);
  808. if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
  809. if (!op->addr.nbytes)
  810. return cqspi_command_read(f_pdata, op);
  811. return cqspi_read(f_pdata, op);
  812. }
  813. if (!op->addr.nbytes || !op->data.buf.out)
  814. return cqspi_command_write(f_pdata, op);
  815. return cqspi_write(f_pdata, op);
  816. }
  817. static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
  818. {
  819. int ret;
  820. ret = cqspi_mem_process(mem, op);
  821. if (ret)
  822. dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
  823. return ret;
  824. }
  825. static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
  826. struct cqspi_flash_pdata *f_pdata,
  827. struct device_node *np)
  828. {
  829. if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
  830. dev_err(&pdev->dev, "couldn't determine read-delay\n");
  831. return -ENXIO;
  832. }
  833. if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
  834. dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
  835. return -ENXIO;
  836. }
  837. if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
  838. dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
  839. return -ENXIO;
  840. }
  841. if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
  842. dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
  843. return -ENXIO;
  844. }
  845. if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
  846. dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
  847. return -ENXIO;
  848. }
  849. if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
  850. dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
  851. return -ENXIO;
  852. }
  853. return 0;
  854. }
  855. static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
  856. {
  857. struct device *dev = &cqspi->pdev->dev;
  858. struct device_node *np = dev->of_node;
  859. cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
  860. if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
  861. dev_err(dev, "couldn't determine fifo-depth\n");
  862. return -ENXIO;
  863. }
  864. if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
  865. dev_err(dev, "couldn't determine fifo-width\n");
  866. return -ENXIO;
  867. }
  868. if (of_property_read_u32(np, "cdns,trigger-address",
  869. &cqspi->trigger_address)) {
  870. dev_err(dev, "couldn't determine trigger-address\n");
  871. return -ENXIO;
  872. }
  873. cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
  874. return 0;
  875. }
  876. static void cqspi_controller_init(struct cqspi_st *cqspi)
  877. {
  878. u32 reg;
  879. cqspi_controller_enable(cqspi, 0);
  880. /* Configure the remap address register, no remap */
  881. writel(0, cqspi->iobase + CQSPI_REG_REMAP);
  882. /* Disable all interrupts. */
  883. writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
  884. /* Configure the SRAM split to 1:1 . */
  885. writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
  886. /* Load indirect trigger address. */
  887. writel(cqspi->trigger_address,
  888. cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
  889. /* Program read watermark -- 1/2 of the FIFO. */
  890. writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
  891. cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
  892. /* Program write watermark -- 1/8 of the FIFO. */
  893. writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
  894. cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
  895. /* Enable Direct Access Controller */
  896. reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
  897. reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
  898. writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
  899. cqspi_controller_enable(cqspi, 1);
  900. }
  901. static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
  902. {
  903. dma_cap_mask_t mask;
  904. dma_cap_zero(mask);
  905. dma_cap_set(DMA_MEMCPY, mask);
  906. cqspi->rx_chan = dma_request_chan_by_mask(&mask);
  907. if (IS_ERR(cqspi->rx_chan)) {
  908. int ret = PTR_ERR(cqspi->rx_chan);
  909. cqspi->rx_chan = NULL;
  910. return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
  911. }
  912. init_completion(&cqspi->rx_dma_complete);
  913. return 0;
  914. }
  915. static const char *cqspi_get_name(struct spi_mem *mem)
  916. {
  917. struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
  918. struct device *dev = &cqspi->pdev->dev;
  919. return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
  920. }
  921. static const struct spi_controller_mem_ops cqspi_mem_ops = {
  922. .exec_op = cqspi_exec_mem_op,
  923. .get_name = cqspi_get_name,
  924. };
  925. static int cqspi_setup_flash(struct cqspi_st *cqspi)
  926. {
  927. struct platform_device *pdev = cqspi->pdev;
  928. struct device *dev = &pdev->dev;
  929. struct device_node *np = dev->of_node;
  930. struct cqspi_flash_pdata *f_pdata;
  931. unsigned int cs;
  932. int ret;
  933. /* Get flash device data */
  934. for_each_available_child_of_node(dev->of_node, np) {
  935. ret = of_property_read_u32(np, "reg", &cs);
  936. if (ret) {
  937. dev_err(dev, "Couldn't determine chip select.\n");
  938. return ret;
  939. }
  940. if (cs >= CQSPI_MAX_CHIPSELECT) {
  941. dev_err(dev, "Chip select %d out of range.\n", cs);
  942. return -EINVAL;
  943. }
  944. f_pdata = &cqspi->f_pdata[cs];
  945. f_pdata->cqspi = cqspi;
  946. f_pdata->cs = cs;
  947. ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
  948. if (ret)
  949. return ret;
  950. }
  951. return 0;
  952. }
  953. static int cqspi_probe(struct platform_device *pdev)
  954. {
  955. const struct cqspi_driver_platdata *ddata;
  956. struct reset_control *rstc, *rstc_ocp;
  957. struct device *dev = &pdev->dev;
  958. struct spi_master *master;
  959. struct resource *res_ahb;
  960. struct cqspi_st *cqspi;
  961. struct resource *res;
  962. int ret;
  963. int irq;
  964. master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
  965. if (!master) {
  966. dev_err(&pdev->dev, "spi_alloc_master failed\n");
  967. return -ENOMEM;
  968. }
  969. master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
  970. master->mem_ops = &cqspi_mem_ops;
  971. master->dev.of_node = pdev->dev.of_node;
  972. cqspi = spi_master_get_devdata(master);
  973. cqspi->pdev = pdev;
  974. platform_set_drvdata(pdev, cqspi);
  975. /* Obtain configuration from OF. */
  976. ret = cqspi_of_get_pdata(cqspi);
  977. if (ret) {
  978. dev_err(dev, "Cannot get mandatory OF data.\n");
  979. ret = -ENODEV;
  980. goto probe_master_put;
  981. }
  982. /* Obtain QSPI clock. */
  983. cqspi->clk = devm_clk_get(dev, NULL);
  984. if (IS_ERR(cqspi->clk)) {
  985. dev_err(dev, "Cannot claim QSPI clock.\n");
  986. ret = PTR_ERR(cqspi->clk);
  987. goto probe_master_put;
  988. }
  989. /* Obtain and remap controller address. */
  990. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  991. cqspi->iobase = devm_ioremap_resource(dev, res);
  992. if (IS_ERR(cqspi->iobase)) {
  993. dev_err(dev, "Cannot remap controller address.\n");
  994. ret = PTR_ERR(cqspi->iobase);
  995. goto probe_master_put;
  996. }
  997. /* Obtain and remap AHB address. */
  998. res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  999. cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
  1000. if (IS_ERR(cqspi->ahb_base)) {
  1001. dev_err(dev, "Cannot remap AHB address.\n");
  1002. ret = PTR_ERR(cqspi->ahb_base);
  1003. goto probe_master_put;
  1004. }
  1005. cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
  1006. cqspi->ahb_size = resource_size(res_ahb);
  1007. init_completion(&cqspi->transfer_complete);
  1008. /* Obtain IRQ line. */
  1009. irq = platform_get_irq(pdev, 0);
  1010. if (irq < 0) {
  1011. ret = -ENXIO;
  1012. goto probe_master_put;
  1013. }
  1014. pm_runtime_enable(dev);
  1015. ret = pm_runtime_get_sync(dev);
  1016. if (ret < 0) {
  1017. pm_runtime_put_noidle(dev);
  1018. goto probe_master_put;
  1019. }
  1020. ret = clk_prepare_enable(cqspi->clk);
  1021. if (ret) {
  1022. dev_err(dev, "Cannot enable QSPI clock.\n");
  1023. goto probe_clk_failed;
  1024. }
  1025. /* Obtain QSPI reset control */
  1026. rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
  1027. if (IS_ERR(rstc)) {
  1028. ret = PTR_ERR(rstc);
  1029. dev_err(dev, "Cannot get QSPI reset.\n");
  1030. goto probe_reset_failed;
  1031. }
  1032. rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
  1033. if (IS_ERR(rstc_ocp)) {
  1034. ret = PTR_ERR(rstc_ocp);
  1035. dev_err(dev, "Cannot get QSPI OCP reset.\n");
  1036. goto probe_reset_failed;
  1037. }
  1038. reset_control_assert(rstc);
  1039. reset_control_deassert(rstc);
  1040. reset_control_assert(rstc_ocp);
  1041. reset_control_deassert(rstc_ocp);
  1042. cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
  1043. ddata = of_device_get_match_data(dev);
  1044. if (ddata) {
  1045. if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
  1046. cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
  1047. cqspi->master_ref_clk_hz);
  1048. if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
  1049. master->mode_bits |= SPI_RX_OCTAL;
  1050. if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
  1051. cqspi->use_direct_mode = true;
  1052. }
  1053. ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
  1054. pdev->name, cqspi);
  1055. if (ret) {
  1056. dev_err(dev, "Cannot request IRQ.\n");
  1057. goto probe_reset_failed;
  1058. }
  1059. cqspi_wait_idle(cqspi);
  1060. cqspi_controller_init(cqspi);
  1061. cqspi->current_cs = -1;
  1062. cqspi->sclk = 0;
  1063. ret = cqspi_setup_flash(cqspi);
  1064. if (ret) {
  1065. dev_err(dev, "failed to setup flash parameters %d\n", ret);
  1066. goto probe_setup_failed;
  1067. }
  1068. if (cqspi->use_direct_mode) {
  1069. ret = cqspi_request_mmap_dma(cqspi);
  1070. if (ret == -EPROBE_DEFER)
  1071. goto probe_setup_failed;
  1072. }
  1073. ret = devm_spi_register_master(dev, master);
  1074. if (ret) {
  1075. dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
  1076. goto probe_setup_failed;
  1077. }
  1078. return 0;
  1079. probe_setup_failed:
  1080. cqspi_controller_enable(cqspi, 0);
  1081. probe_reset_failed:
  1082. clk_disable_unprepare(cqspi->clk);
  1083. probe_clk_failed:
  1084. pm_runtime_put_sync(dev);
  1085. pm_runtime_disable(dev);
  1086. probe_master_put:
  1087. spi_master_put(master);
  1088. return ret;
  1089. }
  1090. static int cqspi_remove(struct platform_device *pdev)
  1091. {
  1092. struct cqspi_st *cqspi = platform_get_drvdata(pdev);
  1093. cqspi_controller_enable(cqspi, 0);
  1094. if (cqspi->rx_chan)
  1095. dma_release_channel(cqspi->rx_chan);
  1096. clk_disable_unprepare(cqspi->clk);
  1097. pm_runtime_put_sync(&pdev->dev);
  1098. pm_runtime_disable(&pdev->dev);
  1099. return 0;
  1100. }
  1101. #ifdef CONFIG_PM_SLEEP
  1102. static int cqspi_suspend(struct device *dev)
  1103. {
  1104. struct cqspi_st *cqspi = dev_get_drvdata(dev);
  1105. cqspi_controller_enable(cqspi, 0);
  1106. return 0;
  1107. }
  1108. static int cqspi_resume(struct device *dev)
  1109. {
  1110. struct cqspi_st *cqspi = dev_get_drvdata(dev);
  1111. cqspi_controller_enable(cqspi, 1);
  1112. return 0;
  1113. }
  1114. static const struct dev_pm_ops cqspi__dev_pm_ops = {
  1115. .suspend = cqspi_suspend,
  1116. .resume = cqspi_resume,
  1117. };
  1118. #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops)
  1119. #else
  1120. #define CQSPI_DEV_PM_OPS NULL
  1121. #endif
  1122. static const struct cqspi_driver_platdata cdns_qspi = {
  1123. .quirks = CQSPI_DISABLE_DAC_MODE,
  1124. };
  1125. static const struct cqspi_driver_platdata k2g_qspi = {
  1126. .quirks = CQSPI_NEEDS_WR_DELAY,
  1127. };
  1128. static const struct cqspi_driver_platdata am654_ospi = {
  1129. .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
  1130. .quirks = CQSPI_NEEDS_WR_DELAY,
  1131. };
  1132. static const struct of_device_id cqspi_dt_ids[] = {
  1133. {
  1134. .compatible = "cdns,qspi-nor",
  1135. .data = &cdns_qspi,
  1136. },
  1137. {
  1138. .compatible = "ti,k2g-qspi",
  1139. .data = &k2g_qspi,
  1140. },
  1141. {
  1142. .compatible = "ti,am654-ospi",
  1143. .data = &am654_ospi,
  1144. },
  1145. { /* end of table */ }
  1146. };
  1147. MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
  1148. static struct platform_driver cqspi_platform_driver = {
  1149. .probe = cqspi_probe,
  1150. .remove = cqspi_remove,
  1151. .driver = {
  1152. .name = CQSPI_NAME,
  1153. .pm = CQSPI_DEV_PM_OPS,
  1154. .of_match_table = cqspi_dt_ids,
  1155. },
  1156. };
  1157. module_platform_driver(cqspi_platform_driver);
  1158. MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
  1159. MODULE_LICENSE("GPL v2");
  1160. MODULE_ALIAS("platform:" CQSPI_NAME);
  1161. MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
  1162. MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
  1163. MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
  1164. MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");