spi-bcm63xx.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Broadcom BCM63xx SPI controller support
  4. *
  5. * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
  6. * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/clk.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/completion.h>
  17. #include <linux/err.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/of.h>
  20. #include <linux/reset.h>
  21. /* BCM 6338/6348 SPI core */
  22. #define SPI_6348_RSET_SIZE 64
  23. #define SPI_6348_CMD 0x00 /* 16-bits register */
  24. #define SPI_6348_INT_STATUS 0x02
  25. #define SPI_6348_INT_MASK_ST 0x03
  26. #define SPI_6348_INT_MASK 0x04
  27. #define SPI_6348_ST 0x05
  28. #define SPI_6348_CLK_CFG 0x06
  29. #define SPI_6348_FILL_BYTE 0x07
  30. #define SPI_6348_MSG_TAIL 0x09
  31. #define SPI_6348_RX_TAIL 0x0b
  32. #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
  33. #define SPI_6348_MSG_CTL_WIDTH 8
  34. #define SPI_6348_MSG_DATA 0x41
  35. #define SPI_6348_MSG_DATA_SIZE 0x3f
  36. #define SPI_6348_RX_DATA 0x80
  37. #define SPI_6348_RX_DATA_SIZE 0x3f
  38. /* BCM 3368/6358/6262/6368 SPI core */
  39. #define SPI_6358_RSET_SIZE 1804
  40. #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
  41. #define SPI_6358_MSG_CTL_WIDTH 16
  42. #define SPI_6358_MSG_DATA 0x02
  43. #define SPI_6358_MSG_DATA_SIZE 0x21e
  44. #define SPI_6358_RX_DATA 0x400
  45. #define SPI_6358_RX_DATA_SIZE 0x220
  46. #define SPI_6358_CMD 0x700 /* 16-bits register */
  47. #define SPI_6358_INT_STATUS 0x702
  48. #define SPI_6358_INT_MASK_ST 0x703
  49. #define SPI_6358_INT_MASK 0x704
  50. #define SPI_6358_ST 0x705
  51. #define SPI_6358_CLK_CFG 0x706
  52. #define SPI_6358_FILL_BYTE 0x707
  53. #define SPI_6358_MSG_TAIL 0x709
  54. #define SPI_6358_RX_TAIL 0x70B
  55. /* Shared SPI definitions */
  56. /* Message configuration */
  57. #define SPI_FD_RW 0x00
  58. #define SPI_HD_W 0x01
  59. #define SPI_HD_R 0x02
  60. #define SPI_BYTE_CNT_SHIFT 0
  61. #define SPI_6348_MSG_TYPE_SHIFT 6
  62. #define SPI_6358_MSG_TYPE_SHIFT 14
  63. /* Command */
  64. #define SPI_CMD_NOOP 0x00
  65. #define SPI_CMD_SOFT_RESET 0x01
  66. #define SPI_CMD_HARD_RESET 0x02
  67. #define SPI_CMD_START_IMMEDIATE 0x03
  68. #define SPI_CMD_COMMAND_SHIFT 0
  69. #define SPI_CMD_COMMAND_MASK 0x000f
  70. #define SPI_CMD_DEVICE_ID_SHIFT 4
  71. #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
  72. #define SPI_CMD_ONE_BYTE_SHIFT 11
  73. #define SPI_CMD_ONE_WIRE_SHIFT 12
  74. #define SPI_DEV_ID_0 0
  75. #define SPI_DEV_ID_1 1
  76. #define SPI_DEV_ID_2 2
  77. #define SPI_DEV_ID_3 3
  78. /* Interrupt mask */
  79. #define SPI_INTR_CMD_DONE 0x01
  80. #define SPI_INTR_RX_OVERFLOW 0x02
  81. #define SPI_INTR_TX_UNDERFLOW 0x04
  82. #define SPI_INTR_TX_OVERFLOW 0x08
  83. #define SPI_INTR_RX_UNDERFLOW 0x10
  84. #define SPI_INTR_CLEAR_ALL 0x1f
  85. /* Status */
  86. #define SPI_RX_EMPTY 0x02
  87. #define SPI_CMD_BUSY 0x04
  88. #define SPI_SERIAL_BUSY 0x08
  89. /* Clock configuration */
  90. #define SPI_CLK_20MHZ 0x00
  91. #define SPI_CLK_0_391MHZ 0x01
  92. #define SPI_CLK_0_781MHZ 0x02 /* default */
  93. #define SPI_CLK_1_563MHZ 0x03
  94. #define SPI_CLK_3_125MHZ 0x04
  95. #define SPI_CLK_6_250MHZ 0x05
  96. #define SPI_CLK_12_50MHZ 0x06
  97. #define SPI_CLK_MASK 0x07
  98. #define SPI_SSOFFTIME_MASK 0x38
  99. #define SPI_SSOFFTIME_SHIFT 3
  100. #define SPI_BYTE_SWAP 0x80
  101. enum bcm63xx_regs_spi {
  102. SPI_CMD,
  103. SPI_INT_STATUS,
  104. SPI_INT_MASK_ST,
  105. SPI_INT_MASK,
  106. SPI_ST,
  107. SPI_CLK_CFG,
  108. SPI_FILL_BYTE,
  109. SPI_MSG_TAIL,
  110. SPI_RX_TAIL,
  111. SPI_MSG_CTL,
  112. SPI_MSG_DATA,
  113. SPI_RX_DATA,
  114. SPI_MSG_TYPE_SHIFT,
  115. SPI_MSG_CTL_WIDTH,
  116. SPI_MSG_DATA_SIZE,
  117. };
  118. #define BCM63XX_SPI_MAX_PREPEND 15
  119. #define BCM63XX_SPI_MAX_CS 8
  120. #define BCM63XX_SPI_BUS_NUM 0
  121. struct bcm63xx_spi {
  122. struct completion done;
  123. void __iomem *regs;
  124. int irq;
  125. /* Platform data */
  126. const unsigned long *reg_offsets;
  127. unsigned int fifo_size;
  128. unsigned int msg_type_shift;
  129. unsigned int msg_ctl_width;
  130. /* data iomem */
  131. u8 __iomem *tx_io;
  132. const u8 __iomem *rx_io;
  133. struct clk *clk;
  134. struct platform_device *pdev;
  135. };
  136. static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
  137. unsigned int offset)
  138. {
  139. return readb(bs->regs + bs->reg_offsets[offset]);
  140. }
  141. static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
  142. unsigned int offset)
  143. {
  144. #ifdef CONFIG_CPU_BIG_ENDIAN
  145. return ioread16be(bs->regs + bs->reg_offsets[offset]);
  146. #else
  147. return readw(bs->regs + bs->reg_offsets[offset]);
  148. #endif
  149. }
  150. static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
  151. u8 value, unsigned int offset)
  152. {
  153. writeb(value, bs->regs + bs->reg_offsets[offset]);
  154. }
  155. static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
  156. u16 value, unsigned int offset)
  157. {
  158. #ifdef CONFIG_CPU_BIG_ENDIAN
  159. iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
  160. #else
  161. writew(value, bs->regs + bs->reg_offsets[offset]);
  162. #endif
  163. }
  164. static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
  165. { 20000000, SPI_CLK_20MHZ },
  166. { 12500000, SPI_CLK_12_50MHZ },
  167. { 6250000, SPI_CLK_6_250MHZ },
  168. { 3125000, SPI_CLK_3_125MHZ },
  169. { 1563000, SPI_CLK_1_563MHZ },
  170. { 781000, SPI_CLK_0_781MHZ },
  171. { 391000, SPI_CLK_0_391MHZ }
  172. };
  173. static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
  174. struct spi_transfer *t)
  175. {
  176. struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
  177. u8 clk_cfg, reg;
  178. int i;
  179. /* Default to lowest clock configuration */
  180. clk_cfg = SPI_CLK_0_391MHZ;
  181. /* Find the closest clock configuration */
  182. for (i = 0; i < SPI_CLK_MASK; i++) {
  183. if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
  184. clk_cfg = bcm63xx_spi_freq_table[i][1];
  185. break;
  186. }
  187. }
  188. /* clear existing clock configuration bits of the register */
  189. reg = bcm_spi_readb(bs, SPI_CLK_CFG);
  190. reg &= ~SPI_CLK_MASK;
  191. reg |= clk_cfg;
  192. bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
  193. dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
  194. clk_cfg, t->speed_hz);
  195. }
  196. /* the spi->mode bits understood by this driver: */
  197. #define MODEBITS (SPI_CPOL | SPI_CPHA)
  198. static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
  199. unsigned int num_transfers)
  200. {
  201. struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
  202. u16 msg_ctl;
  203. u16 cmd;
  204. unsigned int i, timeout = 0, prepend_len = 0, len = 0;
  205. struct spi_transfer *t = first;
  206. bool do_rx = false;
  207. bool do_tx = false;
  208. /* Disable the CMD_DONE interrupt */
  209. bcm_spi_writeb(bs, 0, SPI_INT_MASK);
  210. dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
  211. t->tx_buf, t->rx_buf, t->len);
  212. if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
  213. prepend_len = t->len;
  214. /* prepare the buffer */
  215. for (i = 0; i < num_transfers; i++) {
  216. if (t->tx_buf) {
  217. do_tx = true;
  218. memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
  219. /* don't prepend more than one tx */
  220. if (t != first)
  221. prepend_len = 0;
  222. }
  223. if (t->rx_buf) {
  224. do_rx = true;
  225. /* prepend is half-duplex write only */
  226. if (t == first)
  227. prepend_len = 0;
  228. }
  229. len += t->len;
  230. t = list_entry(t->transfer_list.next, struct spi_transfer,
  231. transfer_list);
  232. }
  233. reinit_completion(&bs->done);
  234. /* Fill in the Message control register */
  235. msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
  236. if (do_rx && do_tx && prepend_len == 0)
  237. msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
  238. else if (do_rx)
  239. msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
  240. else if (do_tx)
  241. msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
  242. switch (bs->msg_ctl_width) {
  243. case 8:
  244. bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
  245. break;
  246. case 16:
  247. bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
  248. break;
  249. }
  250. /* Issue the transfer */
  251. cmd = SPI_CMD_START_IMMEDIATE;
  252. cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
  253. cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
  254. bcm_spi_writew(bs, cmd, SPI_CMD);
  255. /* Enable the CMD_DONE interrupt */
  256. bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
  257. timeout = wait_for_completion_timeout(&bs->done, HZ);
  258. if (!timeout)
  259. return -ETIMEDOUT;
  260. if (!do_rx)
  261. return 0;
  262. len = 0;
  263. t = first;
  264. /* Read out all the data */
  265. for (i = 0; i < num_transfers; i++) {
  266. if (t->rx_buf)
  267. memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
  268. if (t != first || prepend_len == 0)
  269. len += t->len;
  270. t = list_entry(t->transfer_list.next, struct spi_transfer,
  271. transfer_list);
  272. }
  273. return 0;
  274. }
  275. static int bcm63xx_spi_transfer_one(struct spi_master *master,
  276. struct spi_message *m)
  277. {
  278. struct bcm63xx_spi *bs = spi_master_get_devdata(master);
  279. struct spi_transfer *t, *first = NULL;
  280. struct spi_device *spi = m->spi;
  281. int status = 0;
  282. unsigned int n_transfers = 0, total_len = 0;
  283. bool can_use_prepend = false;
  284. /*
  285. * This SPI controller does not support keeping CS active after a
  286. * transfer.
  287. * Work around this by merging as many transfers we can into one big
  288. * full-duplex transfers.
  289. */
  290. list_for_each_entry(t, &m->transfers, transfer_list) {
  291. if (!first)
  292. first = t;
  293. n_transfers++;
  294. total_len += t->len;
  295. if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
  296. first->len <= BCM63XX_SPI_MAX_PREPEND)
  297. can_use_prepend = true;
  298. else if (can_use_prepend && t->tx_buf)
  299. can_use_prepend = false;
  300. /* we can only transfer one fifo worth of data */
  301. if ((can_use_prepend &&
  302. total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
  303. (!can_use_prepend && total_len > bs->fifo_size)) {
  304. dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
  305. total_len, bs->fifo_size);
  306. status = -EINVAL;
  307. goto exit;
  308. }
  309. /* all combined transfers have to have the same speed */
  310. if (t->speed_hz != first->speed_hz) {
  311. dev_err(&spi->dev, "unable to change speed between transfers\n");
  312. status = -EINVAL;
  313. goto exit;
  314. }
  315. /* CS will be deasserted directly after transfer */
  316. if (t->delay_usecs || t->delay.value) {
  317. dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
  318. status = -EINVAL;
  319. goto exit;
  320. }
  321. if (t->cs_change ||
  322. list_is_last(&t->transfer_list, &m->transfers)) {
  323. /* configure adapter for a new transfer */
  324. bcm63xx_spi_setup_transfer(spi, first);
  325. /* send the data */
  326. status = bcm63xx_txrx_bufs(spi, first, n_transfers);
  327. if (status)
  328. goto exit;
  329. m->actual_length += total_len;
  330. first = NULL;
  331. n_transfers = 0;
  332. total_len = 0;
  333. can_use_prepend = false;
  334. }
  335. }
  336. exit:
  337. m->status = status;
  338. spi_finalize_current_message(master);
  339. return 0;
  340. }
  341. /* This driver supports single master mode only. Hence
  342. * CMD_DONE is the only interrupt we care about
  343. */
  344. static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
  345. {
  346. struct spi_master *master = (struct spi_master *)dev_id;
  347. struct bcm63xx_spi *bs = spi_master_get_devdata(master);
  348. u8 intr;
  349. /* Read interupts and clear them immediately */
  350. intr = bcm_spi_readb(bs, SPI_INT_STATUS);
  351. bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
  352. bcm_spi_writeb(bs, 0, SPI_INT_MASK);
  353. /* A transfer completed */
  354. if (intr & SPI_INTR_CMD_DONE)
  355. complete(&bs->done);
  356. return IRQ_HANDLED;
  357. }
  358. static size_t bcm63xx_spi_max_length(struct spi_device *spi)
  359. {
  360. struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
  361. return bs->fifo_size;
  362. }
  363. static const unsigned long bcm6348_spi_reg_offsets[] = {
  364. [SPI_CMD] = SPI_6348_CMD,
  365. [SPI_INT_STATUS] = SPI_6348_INT_STATUS,
  366. [SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST,
  367. [SPI_INT_MASK] = SPI_6348_INT_MASK,
  368. [SPI_ST] = SPI_6348_ST,
  369. [SPI_CLK_CFG] = SPI_6348_CLK_CFG,
  370. [SPI_FILL_BYTE] = SPI_6348_FILL_BYTE,
  371. [SPI_MSG_TAIL] = SPI_6348_MSG_TAIL,
  372. [SPI_RX_TAIL] = SPI_6348_RX_TAIL,
  373. [SPI_MSG_CTL] = SPI_6348_MSG_CTL,
  374. [SPI_MSG_DATA] = SPI_6348_MSG_DATA,
  375. [SPI_RX_DATA] = SPI_6348_RX_DATA,
  376. [SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT,
  377. [SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH,
  378. [SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE,
  379. };
  380. static const unsigned long bcm6358_spi_reg_offsets[] = {
  381. [SPI_CMD] = SPI_6358_CMD,
  382. [SPI_INT_STATUS] = SPI_6358_INT_STATUS,
  383. [SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST,
  384. [SPI_INT_MASK] = SPI_6358_INT_MASK,
  385. [SPI_ST] = SPI_6358_ST,
  386. [SPI_CLK_CFG] = SPI_6358_CLK_CFG,
  387. [SPI_FILL_BYTE] = SPI_6358_FILL_BYTE,
  388. [SPI_MSG_TAIL] = SPI_6358_MSG_TAIL,
  389. [SPI_RX_TAIL] = SPI_6358_RX_TAIL,
  390. [SPI_MSG_CTL] = SPI_6358_MSG_CTL,
  391. [SPI_MSG_DATA] = SPI_6358_MSG_DATA,
  392. [SPI_RX_DATA] = SPI_6358_RX_DATA,
  393. [SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT,
  394. [SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH,
  395. [SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE,
  396. };
  397. static const struct platform_device_id bcm63xx_spi_dev_match[] = {
  398. {
  399. .name = "bcm6348-spi",
  400. .driver_data = (unsigned long)bcm6348_spi_reg_offsets,
  401. },
  402. {
  403. .name = "bcm6358-spi",
  404. .driver_data = (unsigned long)bcm6358_spi_reg_offsets,
  405. },
  406. {
  407. },
  408. };
  409. static const struct of_device_id bcm63xx_spi_of_match[] = {
  410. { .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets },
  411. { .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets },
  412. { },
  413. };
  414. static int bcm63xx_spi_probe(struct platform_device *pdev)
  415. {
  416. struct resource *r;
  417. const unsigned long *bcm63xx_spireg;
  418. struct device *dev = &pdev->dev;
  419. int irq, bus_num;
  420. struct spi_master *master;
  421. struct clk *clk;
  422. struct bcm63xx_spi *bs;
  423. int ret;
  424. u32 num_cs = BCM63XX_SPI_MAX_CS;
  425. struct reset_control *reset;
  426. if (dev->of_node) {
  427. const struct of_device_id *match;
  428. match = of_match_node(bcm63xx_spi_of_match, dev->of_node);
  429. if (!match)
  430. return -EINVAL;
  431. bcm63xx_spireg = match->data;
  432. of_property_read_u32(dev->of_node, "num-cs", &num_cs);
  433. if (num_cs > BCM63XX_SPI_MAX_CS) {
  434. dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
  435. num_cs);
  436. num_cs = BCM63XX_SPI_MAX_CS;
  437. }
  438. bus_num = -1;
  439. } else if (pdev->id_entry->driver_data) {
  440. const struct platform_device_id *match = pdev->id_entry;
  441. bcm63xx_spireg = (const unsigned long *)match->driver_data;
  442. bus_num = BCM63XX_SPI_BUS_NUM;
  443. } else {
  444. return -EINVAL;
  445. }
  446. irq = platform_get_irq(pdev, 0);
  447. if (irq < 0)
  448. return irq;
  449. clk = devm_clk_get(dev, "spi");
  450. if (IS_ERR(clk)) {
  451. dev_err(dev, "no clock for device\n");
  452. return PTR_ERR(clk);
  453. }
  454. reset = devm_reset_control_get_optional_exclusive(dev, NULL);
  455. if (IS_ERR(reset))
  456. return PTR_ERR(reset);
  457. master = spi_alloc_master(dev, sizeof(*bs));
  458. if (!master) {
  459. dev_err(dev, "out of memory\n");
  460. return -ENOMEM;
  461. }
  462. bs = spi_master_get_devdata(master);
  463. init_completion(&bs->done);
  464. platform_set_drvdata(pdev, master);
  465. bs->pdev = pdev;
  466. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  467. bs->regs = devm_ioremap_resource(&pdev->dev, r);
  468. if (IS_ERR(bs->regs)) {
  469. ret = PTR_ERR(bs->regs);
  470. goto out_err;
  471. }
  472. bs->irq = irq;
  473. bs->clk = clk;
  474. bs->reg_offsets = bcm63xx_spireg;
  475. bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
  476. ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
  477. pdev->name, master);
  478. if (ret) {
  479. dev_err(dev, "unable to request irq\n");
  480. goto out_err;
  481. }
  482. master->dev.of_node = dev->of_node;
  483. master->bus_num = bus_num;
  484. master->num_chipselect = num_cs;
  485. master->transfer_one_message = bcm63xx_spi_transfer_one;
  486. master->mode_bits = MODEBITS;
  487. master->bits_per_word_mask = SPI_BPW_MASK(8);
  488. master->max_transfer_size = bcm63xx_spi_max_length;
  489. master->max_message_size = bcm63xx_spi_max_length;
  490. master->auto_runtime_pm = true;
  491. bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
  492. bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
  493. bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
  494. bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
  495. /* Initialize hardware */
  496. ret = clk_prepare_enable(bs->clk);
  497. if (ret)
  498. goto out_err;
  499. ret = reset_control_reset(reset);
  500. if (ret) {
  501. dev_err(dev, "unable to reset device: %d\n", ret);
  502. goto out_clk_disable;
  503. }
  504. bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
  505. /* register and we are done */
  506. ret = devm_spi_register_master(dev, master);
  507. if (ret) {
  508. dev_err(dev, "spi register failed\n");
  509. goto out_clk_disable;
  510. }
  511. dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
  512. r, irq, bs->fifo_size);
  513. return 0;
  514. out_clk_disable:
  515. clk_disable_unprepare(clk);
  516. out_err:
  517. spi_master_put(master);
  518. return ret;
  519. }
  520. static int bcm63xx_spi_remove(struct platform_device *pdev)
  521. {
  522. struct spi_master *master = platform_get_drvdata(pdev);
  523. struct bcm63xx_spi *bs = spi_master_get_devdata(master);
  524. /* reset spi block */
  525. bcm_spi_writeb(bs, 0, SPI_INT_MASK);
  526. /* HW shutdown */
  527. clk_disable_unprepare(bs->clk);
  528. return 0;
  529. }
  530. #ifdef CONFIG_PM_SLEEP
  531. static int bcm63xx_spi_suspend(struct device *dev)
  532. {
  533. struct spi_master *master = dev_get_drvdata(dev);
  534. struct bcm63xx_spi *bs = spi_master_get_devdata(master);
  535. spi_master_suspend(master);
  536. clk_disable_unprepare(bs->clk);
  537. return 0;
  538. }
  539. static int bcm63xx_spi_resume(struct device *dev)
  540. {
  541. struct spi_master *master = dev_get_drvdata(dev);
  542. struct bcm63xx_spi *bs = spi_master_get_devdata(master);
  543. int ret;
  544. ret = clk_prepare_enable(bs->clk);
  545. if (ret)
  546. return ret;
  547. spi_master_resume(master);
  548. return 0;
  549. }
  550. #endif
  551. static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
  552. SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
  553. };
  554. static struct platform_driver bcm63xx_spi_driver = {
  555. .driver = {
  556. .name = "bcm63xx-spi",
  557. .pm = &bcm63xx_spi_pm_ops,
  558. .of_match_table = bcm63xx_spi_of_match,
  559. },
  560. .id_table = bcm63xx_spi_dev_match,
  561. .probe = bcm63xx_spi_probe,
  562. .remove = bcm63xx_spi_remove,
  563. };
  564. module_platform_driver(bcm63xx_spi_driver);
  565. MODULE_ALIAS("platform:bcm63xx_spi");
  566. MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
  567. MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
  568. MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
  569. MODULE_LICENSE("GPL");