spi-bcm63xx-hsspi.c 14 KB

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  1. /*
  2. * Broadcom BCM63XX High Speed SPI Controller driver
  3. *
  4. * Copyright 2000-2010 Broadcom Corporation
  5. * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
  6. *
  7. * Licensed under the GNU/GPL. See COPYING for details.
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/init.h>
  11. #include <linux/io.h>
  12. #include <linux/clk.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/delay.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/err.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/mutex.h>
  21. #include <linux/of.h>
  22. #include <linux/reset.h>
  23. #define HSSPI_GLOBAL_CTRL_REG 0x0
  24. #define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
  25. #define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
  26. #define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
  27. #define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
  28. #define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
  29. #define GLOBAL_CTRL_CLK_POLARITY BIT(17)
  30. #define GLOBAL_CTRL_MOSI_IDLE BIT(18)
  31. #define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
  32. #define HSSPI_INT_STATUS_REG 0x8
  33. #define HSSPI_INT_STATUS_MASKED_REG 0xc
  34. #define HSSPI_INT_MASK_REG 0x10
  35. #define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
  36. #define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
  37. #define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
  38. #define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
  39. #define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
  40. #define HSSPI_INT_CLEAR_ALL 0xff001f1f
  41. #define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
  42. #define PINGPONG_CMD_COMMAND_MASK 0xf
  43. #define PINGPONG_COMMAND_NOOP 0
  44. #define PINGPONG_COMMAND_START_NOW 1
  45. #define PINGPONG_COMMAND_START_TRIGGER 2
  46. #define PINGPONG_COMMAND_HALT 3
  47. #define PINGPONG_COMMAND_FLUSH 4
  48. #define PINGPONG_CMD_PROFILE_SHIFT 8
  49. #define PINGPONG_CMD_SS_SHIFT 12
  50. #define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
  51. #define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
  52. #define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
  53. #define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
  54. #define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
  55. #define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
  56. #define SIGNAL_CTRL_LATCH_RISING BIT(12)
  57. #define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
  58. #define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
  59. #define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
  60. #define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
  61. #define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
  62. #define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
  63. #define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
  64. #define MODE_CTRL_MODE_3WIRE BIT(20)
  65. #define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
  66. #define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
  67. #define HSSPI_OP_MULTIBIT BIT(11)
  68. #define HSSPI_OP_CODE_SHIFT 13
  69. #define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
  70. #define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
  71. #define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
  72. #define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
  73. #define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
  74. #define HSSPI_BUFFER_LEN 512
  75. #define HSSPI_OPCODE_LEN 2
  76. #define HSSPI_MAX_PREPEND_LEN 15
  77. #define HSSPI_MAX_SYNC_CLOCK 30000000
  78. #define HSSPI_SPI_MAX_CS 8
  79. #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
  80. struct bcm63xx_hsspi {
  81. struct completion done;
  82. struct mutex bus_mutex;
  83. struct platform_device *pdev;
  84. struct clk *clk;
  85. struct clk *pll_clk;
  86. void __iomem *regs;
  87. u8 __iomem *fifo;
  88. u32 speed_hz;
  89. u8 cs_polarity;
  90. };
  91. static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
  92. bool active)
  93. {
  94. u32 reg;
  95. mutex_lock(&bs->bus_mutex);
  96. reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
  97. reg &= ~BIT(cs);
  98. if (active == !(bs->cs_polarity & BIT(cs)))
  99. reg |= BIT(cs);
  100. __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
  101. mutex_unlock(&bs->bus_mutex);
  102. }
  103. static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
  104. struct spi_device *spi, int hz)
  105. {
  106. unsigned int profile = spi->chip_select;
  107. u32 reg;
  108. reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
  109. __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
  110. bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
  111. reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
  112. if (hz > HSSPI_MAX_SYNC_CLOCK)
  113. reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
  114. else
  115. reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
  116. __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
  117. mutex_lock(&bs->bus_mutex);
  118. /* setup clock polarity */
  119. reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
  120. reg &= ~GLOBAL_CTRL_CLK_POLARITY;
  121. if (spi->mode & SPI_CPOL)
  122. reg |= GLOBAL_CTRL_CLK_POLARITY;
  123. __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
  124. mutex_unlock(&bs->bus_mutex);
  125. }
  126. static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
  127. {
  128. struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
  129. unsigned int chip_select = spi->chip_select;
  130. u16 opcode = 0;
  131. int pending = t->len;
  132. int step_size = HSSPI_BUFFER_LEN;
  133. const u8 *tx = t->tx_buf;
  134. u8 *rx = t->rx_buf;
  135. bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
  136. bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
  137. if (tx && rx)
  138. opcode = HSSPI_OP_READ_WRITE;
  139. else if (tx)
  140. opcode = HSSPI_OP_WRITE;
  141. else if (rx)
  142. opcode = HSSPI_OP_READ;
  143. if (opcode != HSSPI_OP_READ)
  144. step_size -= HSSPI_OPCODE_LEN;
  145. if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
  146. (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
  147. opcode |= HSSPI_OP_MULTIBIT;
  148. __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
  149. 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
  150. bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
  151. while (pending > 0) {
  152. int curr_step = min_t(int, step_size, pending);
  153. reinit_completion(&bs->done);
  154. if (tx) {
  155. memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
  156. tx += curr_step;
  157. }
  158. __raw_writew(opcode | curr_step, bs->fifo);
  159. /* enable interrupt */
  160. __raw_writel(HSSPI_PINGx_CMD_DONE(0),
  161. bs->regs + HSSPI_INT_MASK_REG);
  162. /* start the transfer */
  163. __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
  164. chip_select << PINGPONG_CMD_PROFILE_SHIFT |
  165. PINGPONG_COMMAND_START_NOW,
  166. bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
  167. if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
  168. dev_err(&bs->pdev->dev, "transfer timed out!\n");
  169. return -ETIMEDOUT;
  170. }
  171. if (rx) {
  172. memcpy_fromio(rx, bs->fifo, curr_step);
  173. rx += curr_step;
  174. }
  175. pending -= curr_step;
  176. }
  177. return 0;
  178. }
  179. static int bcm63xx_hsspi_setup(struct spi_device *spi)
  180. {
  181. struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
  182. u32 reg;
  183. reg = __raw_readl(bs->regs +
  184. HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
  185. reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
  186. if (spi->mode & SPI_CPHA)
  187. reg |= SIGNAL_CTRL_LAUNCH_RISING;
  188. else
  189. reg |= SIGNAL_CTRL_LATCH_RISING;
  190. __raw_writel(reg, bs->regs +
  191. HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
  192. mutex_lock(&bs->bus_mutex);
  193. reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
  194. /* only change actual polarities if there is no transfer */
  195. if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
  196. if (spi->mode & SPI_CS_HIGH)
  197. reg |= BIT(spi->chip_select);
  198. else
  199. reg &= ~BIT(spi->chip_select);
  200. __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
  201. }
  202. if (spi->mode & SPI_CS_HIGH)
  203. bs->cs_polarity |= BIT(spi->chip_select);
  204. else
  205. bs->cs_polarity &= ~BIT(spi->chip_select);
  206. mutex_unlock(&bs->bus_mutex);
  207. return 0;
  208. }
  209. static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
  210. struct spi_message *msg)
  211. {
  212. struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
  213. struct spi_transfer *t;
  214. struct spi_device *spi = msg->spi;
  215. int status = -EINVAL;
  216. int dummy_cs;
  217. u32 reg;
  218. /* This controller does not support keeping CS active during idle.
  219. * To work around this, we use the following ugly hack:
  220. *
  221. * a. Invert the target chip select's polarity so it will be active.
  222. * b. Select a "dummy" chip select to use as the hardware target.
  223. * c. Invert the dummy chip select's polarity so it will be inactive
  224. * during the actual transfers.
  225. * d. Tell the hardware to send to the dummy chip select. Thanks to
  226. * the multiplexed nature of SPI the actual target will receive
  227. * the transfer and we see its response.
  228. *
  229. * e. At the end restore the polarities again to their default values.
  230. */
  231. dummy_cs = !spi->chip_select;
  232. bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
  233. list_for_each_entry(t, &msg->transfers, transfer_list) {
  234. status = bcm63xx_hsspi_do_txrx(spi, t);
  235. if (status)
  236. break;
  237. msg->actual_length += t->len;
  238. spi_transfer_delay_exec(t);
  239. if (t->cs_change)
  240. bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
  241. }
  242. mutex_lock(&bs->bus_mutex);
  243. reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
  244. reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
  245. reg |= bs->cs_polarity;
  246. __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
  247. mutex_unlock(&bs->bus_mutex);
  248. msg->status = status;
  249. spi_finalize_current_message(master);
  250. return 0;
  251. }
  252. static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
  253. {
  254. struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
  255. if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
  256. return IRQ_NONE;
  257. __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
  258. __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
  259. complete(&bs->done);
  260. return IRQ_HANDLED;
  261. }
  262. static int bcm63xx_hsspi_probe(struct platform_device *pdev)
  263. {
  264. struct spi_master *master;
  265. struct bcm63xx_hsspi *bs;
  266. void __iomem *regs;
  267. struct device *dev = &pdev->dev;
  268. struct clk *clk, *pll_clk = NULL;
  269. int irq, ret;
  270. u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
  271. struct reset_control *reset;
  272. irq = platform_get_irq(pdev, 0);
  273. if (irq < 0)
  274. return irq;
  275. regs = devm_platform_ioremap_resource(pdev, 0);
  276. if (IS_ERR(regs))
  277. return PTR_ERR(regs);
  278. clk = devm_clk_get(dev, "hsspi");
  279. if (IS_ERR(clk))
  280. return PTR_ERR(clk);
  281. reset = devm_reset_control_get_optional_exclusive(dev, NULL);
  282. if (IS_ERR(reset))
  283. return PTR_ERR(reset);
  284. ret = clk_prepare_enable(clk);
  285. if (ret)
  286. return ret;
  287. ret = reset_control_reset(reset);
  288. if (ret) {
  289. dev_err(dev, "unable to reset device: %d\n", ret);
  290. goto out_disable_clk;
  291. }
  292. rate = clk_get_rate(clk);
  293. if (!rate) {
  294. pll_clk = devm_clk_get(dev, "pll");
  295. if (IS_ERR(pll_clk)) {
  296. ret = PTR_ERR(pll_clk);
  297. goto out_disable_clk;
  298. }
  299. ret = clk_prepare_enable(pll_clk);
  300. if (ret)
  301. goto out_disable_clk;
  302. rate = clk_get_rate(pll_clk);
  303. if (!rate) {
  304. ret = -EINVAL;
  305. goto out_disable_pll_clk;
  306. }
  307. }
  308. master = spi_alloc_master(&pdev->dev, sizeof(*bs));
  309. if (!master) {
  310. ret = -ENOMEM;
  311. goto out_disable_pll_clk;
  312. }
  313. bs = spi_master_get_devdata(master);
  314. bs->pdev = pdev;
  315. bs->clk = clk;
  316. bs->pll_clk = pll_clk;
  317. bs->regs = regs;
  318. bs->speed_hz = rate;
  319. bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
  320. mutex_init(&bs->bus_mutex);
  321. init_completion(&bs->done);
  322. master->dev.of_node = dev->of_node;
  323. if (!dev->of_node)
  324. master->bus_num = HSSPI_BUS_NUM;
  325. of_property_read_u32(dev->of_node, "num-cs", &num_cs);
  326. if (num_cs > 8) {
  327. dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
  328. num_cs);
  329. num_cs = HSSPI_SPI_MAX_CS;
  330. }
  331. master->num_chipselect = num_cs;
  332. master->setup = bcm63xx_hsspi_setup;
  333. master->transfer_one_message = bcm63xx_hsspi_transfer_one;
  334. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
  335. SPI_RX_DUAL | SPI_TX_DUAL;
  336. master->bits_per_word_mask = SPI_BPW_MASK(8);
  337. master->auto_runtime_pm = true;
  338. platform_set_drvdata(pdev, master);
  339. /* Initialize the hardware */
  340. __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
  341. /* clean up any pending interrupts */
  342. __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
  343. /* read out default CS polarities */
  344. reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
  345. bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
  346. __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
  347. bs->regs + HSSPI_GLOBAL_CTRL_REG);
  348. ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
  349. pdev->name, bs);
  350. if (ret)
  351. goto out_put_master;
  352. /* register and we are done */
  353. ret = devm_spi_register_master(dev, master);
  354. if (ret)
  355. goto out_put_master;
  356. return 0;
  357. out_put_master:
  358. spi_master_put(master);
  359. out_disable_pll_clk:
  360. clk_disable_unprepare(pll_clk);
  361. out_disable_clk:
  362. clk_disable_unprepare(clk);
  363. return ret;
  364. }
  365. static int bcm63xx_hsspi_remove(struct platform_device *pdev)
  366. {
  367. struct spi_master *master = platform_get_drvdata(pdev);
  368. struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
  369. /* reset the hardware and block queue progress */
  370. __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
  371. clk_disable_unprepare(bs->pll_clk);
  372. clk_disable_unprepare(bs->clk);
  373. return 0;
  374. }
  375. #ifdef CONFIG_PM_SLEEP
  376. static int bcm63xx_hsspi_suspend(struct device *dev)
  377. {
  378. struct spi_master *master = dev_get_drvdata(dev);
  379. struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
  380. spi_master_suspend(master);
  381. clk_disable_unprepare(bs->pll_clk);
  382. clk_disable_unprepare(bs->clk);
  383. return 0;
  384. }
  385. static int bcm63xx_hsspi_resume(struct device *dev)
  386. {
  387. struct spi_master *master = dev_get_drvdata(dev);
  388. struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
  389. int ret;
  390. ret = clk_prepare_enable(bs->clk);
  391. if (ret)
  392. return ret;
  393. if (bs->pll_clk) {
  394. ret = clk_prepare_enable(bs->pll_clk);
  395. if (ret) {
  396. clk_disable_unprepare(bs->clk);
  397. return ret;
  398. }
  399. }
  400. spi_master_resume(master);
  401. return 0;
  402. }
  403. #endif
  404. static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
  405. bcm63xx_hsspi_resume);
  406. static const struct of_device_id bcm63xx_hsspi_of_match[] = {
  407. { .compatible = "brcm,bcm6328-hsspi", },
  408. { },
  409. };
  410. MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
  411. static struct platform_driver bcm63xx_hsspi_driver = {
  412. .driver = {
  413. .name = "bcm63xx-hsspi",
  414. .pm = &bcm63xx_hsspi_pm_ops,
  415. .of_match_table = bcm63xx_hsspi_of_match,
  416. },
  417. .probe = bcm63xx_hsspi_probe,
  418. .remove = bcm63xx_hsspi_remove,
  419. };
  420. module_platform_driver(bcm63xx_hsspi_driver);
  421. MODULE_ALIAS("platform:bcm63xx_hsspi");
  422. MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
  423. MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
  424. MODULE_LICENSE("GPL");