spi-bcm2835.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Broadcom BCM2835 SPI Controllers
  4. *
  5. * Copyright (C) 2012 Chris Boot
  6. * Copyright (C) 2013 Stephen Warren
  7. * Copyright (C) 2015 Martin Sperl
  8. *
  9. * This driver is inspired by:
  10. * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  11. * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/completion.h>
  15. #include <linux/debugfs.h>
  16. #include <linux/delay.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/dmaengine.h>
  19. #include <linux/err.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/io.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/of.h>
  25. #include <linux/of_address.h>
  26. #include <linux/of_device.h>
  27. #include <linux/gpio/consumer.h>
  28. #include <linux/gpio/machine.h> /* FIXME: using chip internals */
  29. #include <linux/gpio/driver.h> /* FIXME: using chip internals */
  30. #include <linux/of_irq.h>
  31. #include <linux/spi/spi.h>
  32. /* SPI register offsets */
  33. #define BCM2835_SPI_CS 0x00
  34. #define BCM2835_SPI_FIFO 0x04
  35. #define BCM2835_SPI_CLK 0x08
  36. #define BCM2835_SPI_DLEN 0x0c
  37. #define BCM2835_SPI_LTOH 0x10
  38. #define BCM2835_SPI_DC 0x14
  39. /* Bitfields in CS */
  40. #define BCM2835_SPI_CS_LEN_LONG 0x02000000
  41. #define BCM2835_SPI_CS_DMA_LEN 0x01000000
  42. #define BCM2835_SPI_CS_CSPOL2 0x00800000
  43. #define BCM2835_SPI_CS_CSPOL1 0x00400000
  44. #define BCM2835_SPI_CS_CSPOL0 0x00200000
  45. #define BCM2835_SPI_CS_RXF 0x00100000
  46. #define BCM2835_SPI_CS_RXR 0x00080000
  47. #define BCM2835_SPI_CS_TXD 0x00040000
  48. #define BCM2835_SPI_CS_RXD 0x00020000
  49. #define BCM2835_SPI_CS_DONE 0x00010000
  50. #define BCM2835_SPI_CS_LEN 0x00002000
  51. #define BCM2835_SPI_CS_REN 0x00001000
  52. #define BCM2835_SPI_CS_ADCS 0x00000800
  53. #define BCM2835_SPI_CS_INTR 0x00000400
  54. #define BCM2835_SPI_CS_INTD 0x00000200
  55. #define BCM2835_SPI_CS_DMAEN 0x00000100
  56. #define BCM2835_SPI_CS_TA 0x00000080
  57. #define BCM2835_SPI_CS_CSPOL 0x00000040
  58. #define BCM2835_SPI_CS_CLEAR_RX 0x00000020
  59. #define BCM2835_SPI_CS_CLEAR_TX 0x00000010
  60. #define BCM2835_SPI_CS_CPOL 0x00000008
  61. #define BCM2835_SPI_CS_CPHA 0x00000004
  62. #define BCM2835_SPI_CS_CS_10 0x00000002
  63. #define BCM2835_SPI_CS_CS_01 0x00000001
  64. #define BCM2835_SPI_FIFO_SIZE 64
  65. #define BCM2835_SPI_FIFO_SIZE_3_4 48
  66. #define BCM2835_SPI_DMA_MIN_LENGTH 96
  67. #define BCM2835_SPI_NUM_CS 24 /* raise as necessary */
  68. #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
  69. | SPI_NO_CS | SPI_3WIRE)
  70. #define DRV_NAME "spi-bcm2835"
  71. /* define polling limits */
  72. static unsigned int polling_limit_us = 30;
  73. module_param(polling_limit_us, uint, 0664);
  74. MODULE_PARM_DESC(polling_limit_us,
  75. "time in us to run a transfer in polling mode\n");
  76. /**
  77. * struct bcm2835_spi - BCM2835 SPI controller
  78. * @regs: base address of register map
  79. * @clk: core clock, divided to calculate serial clock
  80. * @clk_hz: core clock cached speed
  81. * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
  82. * @tfr: SPI transfer currently processed
  83. * @ctlr: SPI controller reverse lookup
  84. * @tx_buf: pointer whence next transmitted byte is read
  85. * @rx_buf: pointer where next received byte is written
  86. * @tx_len: remaining bytes to transmit
  87. * @rx_len: remaining bytes to receive
  88. * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's
  89. * length is not a multiple of 4 (to overcome hardware limitation)
  90. * @rx_prologue: bytes received without DMA if first RX sglist entry's
  91. * length is not a multiple of 4 (to overcome hardware limitation)
  92. * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry
  93. * @prepare_cs: precalculated CS register value for ->prepare_message()
  94. * (uses slave-specific clock polarity and phase settings)
  95. * @debugfs_dir: the debugfs directory - neede to remove debugfs when
  96. * unloading the module
  97. * @count_transfer_polling: count of how often polling mode is used
  98. * @count_transfer_irq: count of how often interrupt mode is used
  99. * @count_transfer_irq_after_polling: count of how often we fall back to
  100. * interrupt mode after starting in polling mode.
  101. * These are counted as well in @count_transfer_polling and
  102. * @count_transfer_irq
  103. * @count_transfer_dma: count how often dma mode is used
  104. * @chip_select: SPI slave currently selected
  105. * (used by bcm2835_spi_dma_tx_done() to write @clear_rx_cs)
  106. * @tx_dma_active: whether a TX DMA descriptor is in progress
  107. * @rx_dma_active: whether a RX DMA descriptor is in progress
  108. * (used by bcm2835_spi_dma_tx_done() to handle a race)
  109. * @fill_tx_desc: preallocated TX DMA descriptor used for RX-only transfers
  110. * (cyclically copies from zero page to TX FIFO)
  111. * @fill_tx_addr: bus address of zero page
  112. * @clear_rx_desc: preallocated RX DMA descriptor used for TX-only transfers
  113. * (cyclically clears RX FIFO by writing @clear_rx_cs to CS register)
  114. * @clear_rx_addr: bus address of @clear_rx_cs
  115. * @clear_rx_cs: precalculated CS register value to clear RX FIFO
  116. * (uses slave-specific clock polarity and phase settings)
  117. */
  118. struct bcm2835_spi {
  119. void __iomem *regs;
  120. struct clk *clk;
  121. unsigned long clk_hz;
  122. int irq;
  123. struct spi_transfer *tfr;
  124. struct spi_controller *ctlr;
  125. const u8 *tx_buf;
  126. u8 *rx_buf;
  127. int tx_len;
  128. int rx_len;
  129. int tx_prologue;
  130. int rx_prologue;
  131. unsigned int tx_spillover;
  132. u32 prepare_cs[BCM2835_SPI_NUM_CS];
  133. struct dentry *debugfs_dir;
  134. u64 count_transfer_polling;
  135. u64 count_transfer_irq;
  136. u64 count_transfer_irq_after_polling;
  137. u64 count_transfer_dma;
  138. u8 chip_select;
  139. unsigned int tx_dma_active;
  140. unsigned int rx_dma_active;
  141. struct dma_async_tx_descriptor *fill_tx_desc;
  142. dma_addr_t fill_tx_addr;
  143. struct dma_async_tx_descriptor *clear_rx_desc[BCM2835_SPI_NUM_CS];
  144. dma_addr_t clear_rx_addr;
  145. u32 clear_rx_cs[BCM2835_SPI_NUM_CS] ____cacheline_aligned;
  146. };
  147. #if defined(CONFIG_DEBUG_FS)
  148. static void bcm2835_debugfs_create(struct bcm2835_spi *bs,
  149. const char *dname)
  150. {
  151. char name[64];
  152. struct dentry *dir;
  153. /* get full name */
  154. snprintf(name, sizeof(name), "spi-bcm2835-%s", dname);
  155. /* the base directory */
  156. dir = debugfs_create_dir(name, NULL);
  157. bs->debugfs_dir = dir;
  158. /* the counters */
  159. debugfs_create_u64("count_transfer_polling", 0444, dir,
  160. &bs->count_transfer_polling);
  161. debugfs_create_u64("count_transfer_irq", 0444, dir,
  162. &bs->count_transfer_irq);
  163. debugfs_create_u64("count_transfer_irq_after_polling", 0444, dir,
  164. &bs->count_transfer_irq_after_polling);
  165. debugfs_create_u64("count_transfer_dma", 0444, dir,
  166. &bs->count_transfer_dma);
  167. }
  168. static void bcm2835_debugfs_remove(struct bcm2835_spi *bs)
  169. {
  170. debugfs_remove_recursive(bs->debugfs_dir);
  171. bs->debugfs_dir = NULL;
  172. }
  173. #else
  174. static void bcm2835_debugfs_create(struct bcm2835_spi *bs,
  175. const char *dname)
  176. {
  177. }
  178. static void bcm2835_debugfs_remove(struct bcm2835_spi *bs)
  179. {
  180. }
  181. #endif /* CONFIG_DEBUG_FS */
  182. static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned int reg)
  183. {
  184. return readl(bs->regs + reg);
  185. }
  186. static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned int reg, u32 val)
  187. {
  188. writel(val, bs->regs + reg);
  189. }
  190. static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
  191. {
  192. u8 byte;
  193. while ((bs->rx_len) &&
  194. (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
  195. byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
  196. if (bs->rx_buf)
  197. *bs->rx_buf++ = byte;
  198. bs->rx_len--;
  199. }
  200. }
  201. static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
  202. {
  203. u8 byte;
  204. while ((bs->tx_len) &&
  205. (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
  206. byte = bs->tx_buf ? *bs->tx_buf++ : 0;
  207. bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
  208. bs->tx_len--;
  209. }
  210. }
  211. /**
  212. * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO
  213. * @bs: BCM2835 SPI controller
  214. * @count: bytes to read from RX FIFO
  215. *
  216. * The caller must ensure that @bs->rx_len is greater than or equal to @count,
  217. * that the RX FIFO contains at least @count bytes and that the DMA Enable flag
  218. * in the CS register is set (such that a read from the FIFO register receives
  219. * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL.
  220. */
  221. static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count)
  222. {
  223. u32 val;
  224. int len;
  225. bs->rx_len -= count;
  226. do {
  227. val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
  228. len = min(count, 4);
  229. memcpy(bs->rx_buf, &val, len);
  230. bs->rx_buf += len;
  231. count -= 4;
  232. } while (count > 0);
  233. }
  234. /**
  235. * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO
  236. * @bs: BCM2835 SPI controller
  237. * @count: bytes to write to TX FIFO
  238. *
  239. * The caller must ensure that @bs->tx_len is greater than or equal to @count,
  240. * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag
  241. * in the CS register is set (such that a write to the FIFO register transmits
  242. * 32-bit instead of just 8-bit).
  243. */
  244. static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count)
  245. {
  246. u32 val;
  247. int len;
  248. bs->tx_len -= count;
  249. do {
  250. if (bs->tx_buf) {
  251. len = min(count, 4);
  252. memcpy(&val, bs->tx_buf, len);
  253. bs->tx_buf += len;
  254. } else {
  255. val = 0;
  256. }
  257. bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
  258. count -= 4;
  259. } while (count > 0);
  260. }
  261. /**
  262. * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty
  263. * @bs: BCM2835 SPI controller
  264. *
  265. * The caller must ensure that the RX FIFO can accommodate as many bytes
  266. * as have been written to the TX FIFO: Transmission is halted once the
  267. * RX FIFO is full, causing this function to spin forever.
  268. */
  269. static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs)
  270. {
  271. while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
  272. cpu_relax();
  273. }
  274. /**
  275. * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO
  276. * @bs: BCM2835 SPI controller
  277. * @count: bytes available for reading in RX FIFO
  278. */
  279. static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count)
  280. {
  281. u8 val;
  282. count = min(count, bs->rx_len);
  283. bs->rx_len -= count;
  284. do {
  285. val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
  286. if (bs->rx_buf)
  287. *bs->rx_buf++ = val;
  288. } while (--count);
  289. }
  290. /**
  291. * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO
  292. * @bs: BCM2835 SPI controller
  293. * @count: bytes available for writing in TX FIFO
  294. */
  295. static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count)
  296. {
  297. u8 val;
  298. count = min(count, bs->tx_len);
  299. bs->tx_len -= count;
  300. do {
  301. val = bs->tx_buf ? *bs->tx_buf++ : 0;
  302. bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
  303. } while (--count);
  304. }
  305. static void bcm2835_spi_reset_hw(struct bcm2835_spi *bs)
  306. {
  307. u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
  308. /* Disable SPI interrupts and transfer */
  309. cs &= ~(BCM2835_SPI_CS_INTR |
  310. BCM2835_SPI_CS_INTD |
  311. BCM2835_SPI_CS_DMAEN |
  312. BCM2835_SPI_CS_TA);
  313. /*
  314. * Transmission sometimes breaks unless the DONE bit is written at the
  315. * end of every transfer. The spec says it's a RO bit. Either the
  316. * spec is wrong and the bit is actually of type RW1C, or it's a
  317. * hardware erratum.
  318. */
  319. cs |= BCM2835_SPI_CS_DONE;
  320. /* and reset RX/TX FIFOS */
  321. cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
  322. /* and reset the SPI_HW */
  323. bcm2835_wr(bs, BCM2835_SPI_CS, cs);
  324. /* as well as DLEN */
  325. bcm2835_wr(bs, BCM2835_SPI_DLEN, 0);
  326. }
  327. static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
  328. {
  329. struct bcm2835_spi *bs = dev_id;
  330. u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
  331. /*
  332. * An interrupt is signaled either if DONE is set (TX FIFO empty)
  333. * or if RXR is set (RX FIFO >= ¾ full).
  334. */
  335. if (cs & BCM2835_SPI_CS_RXF)
  336. bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
  337. else if (cs & BCM2835_SPI_CS_RXR)
  338. bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4);
  339. if (bs->tx_len && cs & BCM2835_SPI_CS_DONE)
  340. bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
  341. /* Read as many bytes as possible from FIFO */
  342. bcm2835_rd_fifo(bs);
  343. /* Write as many bytes as possible to FIFO */
  344. bcm2835_wr_fifo(bs);
  345. if (!bs->rx_len) {
  346. /* Transfer complete - reset SPI HW */
  347. bcm2835_spi_reset_hw(bs);
  348. /* wake up the framework */
  349. complete(&bs->ctlr->xfer_completion);
  350. }
  351. return IRQ_HANDLED;
  352. }
  353. static int bcm2835_spi_transfer_one_irq(struct spi_controller *ctlr,
  354. struct spi_device *spi,
  355. struct spi_transfer *tfr,
  356. u32 cs, bool fifo_empty)
  357. {
  358. struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
  359. /* update usage statistics */
  360. bs->count_transfer_irq++;
  361. /*
  362. * Enable HW block, but with interrupts still disabled.
  363. * Otherwise the empty TX FIFO would immediately trigger an interrupt.
  364. */
  365. bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
  366. /* fill TX FIFO as much as possible */
  367. if (fifo_empty)
  368. bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
  369. bcm2835_wr_fifo(bs);
  370. /* enable interrupts */
  371. cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
  372. bcm2835_wr(bs, BCM2835_SPI_CS, cs);
  373. /* signal that we need to wait for completion */
  374. return 1;
  375. }
  376. /**
  377. * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA
  378. * @ctlr: SPI master controller
  379. * @tfr: SPI transfer
  380. * @bs: BCM2835 SPI controller
  381. * @cs: CS register
  382. *
  383. * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks.
  384. * Only the final write access is permitted to transmit less than 4 bytes, the
  385. * SPI controller deduces its intended size from the DLEN register.
  386. *
  387. * If a TX or RX sglist contains multiple entries, one per page, and the first
  388. * entry starts in the middle of a page, that first entry's length may not be
  389. * a multiple of 4. Subsequent entries are fine because they span an entire
  390. * page, hence do have a length that's a multiple of 4.
  391. *
  392. * This cannot happen with kmalloc'ed buffers (which is what most clients use)
  393. * because they are contiguous in physical memory and therefore not split on
  394. * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed
  395. * buffers.
  396. *
  397. * The DMA engine is incapable of combining sglist entries into a continuous
  398. * stream of 4 byte chunks, it treats every entry separately: A TX entry is
  399. * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX
  400. * entry is rounded up by throwing away received bytes.
  401. *
  402. * Overcome this limitation by transferring the first few bytes without DMA:
  403. * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42,
  404. * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO.
  405. * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with
  406. * the rest of the first RX sglist entry it makes up a multiple of 4 bytes.
  407. *
  408. * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1,
  409. * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO.
  410. * Caution, the additional 4 bytes spill over to the second TX sglist entry
  411. * if the length of the first is *exactly* 1.
  412. *
  413. * At most 6 bytes are written and at most 3 bytes read. Do we know the
  414. * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH.
  415. *
  416. * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width
  417. * by the DMA engine. Toggling the DMA Enable flag in the CS register switches
  418. * the width but also garbles the FIFO's contents. The prologue must therefore
  419. * be transmitted in 32-bit width to ensure that the following DMA transfer can
  420. * pick up the residue in the RX FIFO in ungarbled form.
  421. */
  422. static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr,
  423. struct spi_transfer *tfr,
  424. struct bcm2835_spi *bs,
  425. u32 cs)
  426. {
  427. int tx_remaining;
  428. bs->tfr = tfr;
  429. bs->tx_prologue = 0;
  430. bs->rx_prologue = 0;
  431. bs->tx_spillover = false;
  432. if (bs->tx_buf && !sg_is_last(&tfr->tx_sg.sgl[0]))
  433. bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3;
  434. if (bs->rx_buf && !sg_is_last(&tfr->rx_sg.sgl[0])) {
  435. bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3;
  436. if (bs->rx_prologue > bs->tx_prologue) {
  437. if (!bs->tx_buf || sg_is_last(&tfr->tx_sg.sgl[0])) {
  438. bs->tx_prologue = bs->rx_prologue;
  439. } else {
  440. bs->tx_prologue += 4;
  441. bs->tx_spillover =
  442. !(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3);
  443. }
  444. }
  445. }
  446. /* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */
  447. if (!bs->tx_prologue)
  448. return;
  449. /* Write and read RX prologue. Adjust first entry in RX sglist. */
  450. if (bs->rx_prologue) {
  451. bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue);
  452. bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
  453. | BCM2835_SPI_CS_DMAEN);
  454. bcm2835_wr_fifo_count(bs, bs->rx_prologue);
  455. bcm2835_wait_tx_fifo_empty(bs);
  456. bcm2835_rd_fifo_count(bs, bs->rx_prologue);
  457. bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_RX
  458. | BCM2835_SPI_CS_CLEAR_TX
  459. | BCM2835_SPI_CS_DONE);
  460. dma_sync_single_for_device(ctlr->dma_rx->device->dev,
  461. sg_dma_address(&tfr->rx_sg.sgl[0]),
  462. bs->rx_prologue, DMA_FROM_DEVICE);
  463. sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
  464. sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
  465. }
  466. if (!bs->tx_buf)
  467. return;
  468. /*
  469. * Write remaining TX prologue. Adjust first entry in TX sglist.
  470. * Also adjust second entry if prologue spills over to it.
  471. */
  472. tx_remaining = bs->tx_prologue - bs->rx_prologue;
  473. if (tx_remaining) {
  474. bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining);
  475. bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
  476. | BCM2835_SPI_CS_DMAEN);
  477. bcm2835_wr_fifo_count(bs, tx_remaining);
  478. bcm2835_wait_tx_fifo_empty(bs);
  479. bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX
  480. | BCM2835_SPI_CS_DONE);
  481. }
  482. if (likely(!bs->tx_spillover)) {
  483. sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
  484. sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
  485. } else {
  486. sg_dma_len(&tfr->tx_sg.sgl[0]) = 0;
  487. sg_dma_address(&tfr->tx_sg.sgl[1]) += 4;
  488. sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4;
  489. }
  490. }
  491. /**
  492. * bcm2835_spi_undo_prologue() - reconstruct original sglist state
  493. * @bs: BCM2835 SPI controller
  494. *
  495. * Undo changes which were made to an SPI transfer's sglist when transmitting
  496. * the prologue. This is necessary to ensure the same memory ranges are
  497. * unmapped that were originally mapped.
  498. */
  499. static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs)
  500. {
  501. struct spi_transfer *tfr = bs->tfr;
  502. if (!bs->tx_prologue)
  503. return;
  504. if (bs->rx_prologue) {
  505. sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
  506. sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
  507. }
  508. if (!bs->tx_buf)
  509. goto out;
  510. if (likely(!bs->tx_spillover)) {
  511. sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
  512. sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
  513. } else {
  514. sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4;
  515. sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4;
  516. sg_dma_len(&tfr->tx_sg.sgl[1]) += 4;
  517. }
  518. out:
  519. bs->tx_prologue = 0;
  520. }
  521. /**
  522. * bcm2835_spi_dma_rx_done() - callback for DMA RX channel
  523. * @data: SPI master controller
  524. *
  525. * Used for bidirectional and RX-only transfers.
  526. */
  527. static void bcm2835_spi_dma_rx_done(void *data)
  528. {
  529. struct spi_controller *ctlr = data;
  530. struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
  531. /* terminate tx-dma as we do not have an irq for it
  532. * because when the rx dma will terminate and this callback
  533. * is called the tx-dma must have finished - can't get to this
  534. * situation otherwise...
  535. */
  536. dmaengine_terminate_async(ctlr->dma_tx);
  537. bs->tx_dma_active = false;
  538. bs->rx_dma_active = false;
  539. bcm2835_spi_undo_prologue(bs);
  540. /* reset fifo and HW */
  541. bcm2835_spi_reset_hw(bs);
  542. /* and mark as completed */;
  543. complete(&ctlr->xfer_completion);
  544. }
  545. /**
  546. * bcm2835_spi_dma_tx_done() - callback for DMA TX channel
  547. * @data: SPI master controller
  548. *
  549. * Used for TX-only transfers.
  550. */
  551. static void bcm2835_spi_dma_tx_done(void *data)
  552. {
  553. struct spi_controller *ctlr = data;
  554. struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
  555. /* busy-wait for TX FIFO to empty */
  556. while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
  557. bcm2835_wr(bs, BCM2835_SPI_CS,
  558. bs->clear_rx_cs[bs->chip_select]);
  559. bs->tx_dma_active = false;
  560. smp_wmb();
  561. /*
  562. * In case of a very short transfer, RX DMA may not have been
  563. * issued yet. The onus is then on bcm2835_spi_transfer_one_dma()
  564. * to terminate it immediately after issuing.
  565. */
  566. if (cmpxchg(&bs->rx_dma_active, true, false))
  567. dmaengine_terminate_async(ctlr->dma_rx);
  568. bcm2835_spi_undo_prologue(bs);
  569. bcm2835_spi_reset_hw(bs);
  570. complete(&ctlr->xfer_completion);
  571. }
  572. /**
  573. * bcm2835_spi_prepare_sg() - prepare and submit DMA descriptor for sglist
  574. * @ctlr: SPI master controller
  575. * @spi: SPI slave
  576. * @tfr: SPI transfer
  577. * @bs: BCM2835 SPI controller
  578. * @is_tx: whether to submit DMA descriptor for TX or RX sglist
  579. *
  580. * Prepare and submit a DMA descriptor for the TX or RX sglist of @tfr.
  581. * Return 0 on success or a negative error number.
  582. */
  583. static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
  584. struct spi_device *spi,
  585. struct spi_transfer *tfr,
  586. struct bcm2835_spi *bs,
  587. bool is_tx)
  588. {
  589. struct dma_chan *chan;
  590. struct scatterlist *sgl;
  591. unsigned int nents;
  592. enum dma_transfer_direction dir;
  593. unsigned long flags;
  594. struct dma_async_tx_descriptor *desc;
  595. dma_cookie_t cookie;
  596. if (is_tx) {
  597. dir = DMA_MEM_TO_DEV;
  598. chan = ctlr->dma_tx;
  599. nents = tfr->tx_sg.nents;
  600. sgl = tfr->tx_sg.sgl;
  601. flags = tfr->rx_buf ? 0 : DMA_PREP_INTERRUPT;
  602. } else {
  603. dir = DMA_DEV_TO_MEM;
  604. chan = ctlr->dma_rx;
  605. nents = tfr->rx_sg.nents;
  606. sgl = tfr->rx_sg.sgl;
  607. flags = DMA_PREP_INTERRUPT;
  608. }
  609. /* prepare the channel */
  610. desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
  611. if (!desc)
  612. return -EINVAL;
  613. /*
  614. * Completion is signaled by the RX channel for bidirectional and
  615. * RX-only transfers; else by the TX channel for TX-only transfers.
  616. */
  617. if (!is_tx) {
  618. desc->callback = bcm2835_spi_dma_rx_done;
  619. desc->callback_param = ctlr;
  620. } else if (!tfr->rx_buf) {
  621. desc->callback = bcm2835_spi_dma_tx_done;
  622. desc->callback_param = ctlr;
  623. bs->chip_select = spi->chip_select;
  624. }
  625. /* submit it to DMA-engine */
  626. cookie = dmaengine_submit(desc);
  627. return dma_submit_error(cookie);
  628. }
  629. /**
  630. * bcm2835_spi_transfer_one_dma() - perform SPI transfer using DMA engine
  631. * @ctlr: SPI master controller
  632. * @spi: SPI slave
  633. * @tfr: SPI transfer
  634. * @cs: CS register
  635. *
  636. * For *bidirectional* transfers (both tx_buf and rx_buf are non-%NULL), set up
  637. * the TX and RX DMA channel to copy between memory and FIFO register.
  638. *
  639. * For *TX-only* transfers (rx_buf is %NULL), copying the RX FIFO's contents to
  640. * memory is pointless. However not reading the RX FIFO isn't an option either
  641. * because transmission is halted once it's full. As a workaround, cyclically
  642. * clear the RX FIFO by setting the CLEAR_RX bit in the CS register.
  643. *
  644. * The CS register value is precalculated in bcm2835_spi_setup(). Normally
  645. * this is called only once, on slave registration. A DMA descriptor to write
  646. * this value is preallocated in bcm2835_dma_init(). All that's left to do
  647. * when performing a TX-only transfer is to submit this descriptor to the RX
  648. * DMA channel. Latency is thereby minimized. The descriptor does not
  649. * generate any interrupts while running. It must be terminated once the
  650. * TX DMA channel is done.
  651. *
  652. * Clearing the RX FIFO is paced by the DREQ signal. The signal is asserted
  653. * when the RX FIFO becomes half full, i.e. 32 bytes. (Tuneable with the DC
  654. * register.) Reading 32 bytes from the RX FIFO would normally require 8 bus
  655. * accesses, whereas clearing it requires only 1 bus access. So an 8-fold
  656. * reduction in bus traffic and thus energy consumption is achieved.
  657. *
  658. * For *RX-only* transfers (tx_buf is %NULL), fill the TX FIFO by cyclically
  659. * copying from the zero page. The DMA descriptor to do this is preallocated
  660. * in bcm2835_dma_init(). It must be terminated once the RX DMA channel is
  661. * done and can then be reused.
  662. *
  663. * The BCM2835 DMA driver autodetects when a transaction copies from the zero
  664. * page and utilizes the DMA controller's ability to synthesize zeroes instead
  665. * of copying them from memory. This reduces traffic on the memory bus. The
  666. * feature is not available on so-called "lite" channels, but normally TX DMA
  667. * is backed by a full-featured channel.
  668. *
  669. * Zero-filling the TX FIFO is paced by the DREQ signal. Unfortunately the
  670. * BCM2835 SPI controller continues to assert DREQ even after the DLEN register
  671. * has been counted down to zero (hardware erratum). Thus, when the transfer
  672. * has finished, the DMA engine zero-fills the TX FIFO until it is half full.
  673. * (Tuneable with the DC register.) So up to 9 gratuitous bus accesses are
  674. * performed at the end of an RX-only transfer.
  675. */
  676. static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
  677. struct spi_device *spi,
  678. struct spi_transfer *tfr,
  679. u32 cs)
  680. {
  681. struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
  682. dma_cookie_t cookie;
  683. int ret;
  684. /* update usage statistics */
  685. bs->count_transfer_dma++;
  686. /*
  687. * Transfer first few bytes without DMA if length of first TX or RX
  688. * sglist entry is not a multiple of 4 bytes (hardware limitation).
  689. */
  690. bcm2835_spi_transfer_prologue(ctlr, tfr, bs, cs);
  691. /* setup tx-DMA */
  692. if (bs->tx_buf) {
  693. ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, true);
  694. } else {
  695. cookie = dmaengine_submit(bs->fill_tx_desc);
  696. ret = dma_submit_error(cookie);
  697. }
  698. if (ret)
  699. goto err_reset_hw;
  700. /* set the DMA length */
  701. bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len);
  702. /* start the HW */
  703. bcm2835_wr(bs, BCM2835_SPI_CS,
  704. cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN);
  705. bs->tx_dma_active = true;
  706. smp_wmb();
  707. /* start TX early */
  708. dma_async_issue_pending(ctlr->dma_tx);
  709. /* setup rx-DMA late - to run transfers while
  710. * mapping of the rx buffers still takes place
  711. * this saves 10us or more.
  712. */
  713. if (bs->rx_buf) {
  714. ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, false);
  715. } else {
  716. cookie = dmaengine_submit(bs->clear_rx_desc[spi->chip_select]);
  717. ret = dma_submit_error(cookie);
  718. }
  719. if (ret) {
  720. /* need to reset on errors */
  721. dmaengine_terminate_sync(ctlr->dma_tx);
  722. bs->tx_dma_active = false;
  723. goto err_reset_hw;
  724. }
  725. /* start rx dma late */
  726. dma_async_issue_pending(ctlr->dma_rx);
  727. bs->rx_dma_active = true;
  728. smp_mb();
  729. /*
  730. * In case of a very short TX-only transfer, bcm2835_spi_dma_tx_done()
  731. * may run before RX DMA is issued. Terminate RX DMA if so.
  732. */
  733. if (!bs->rx_buf && !bs->tx_dma_active &&
  734. cmpxchg(&bs->rx_dma_active, true, false)) {
  735. dmaengine_terminate_async(ctlr->dma_rx);
  736. bcm2835_spi_reset_hw(bs);
  737. }
  738. /* wait for wakeup in framework */
  739. return 1;
  740. err_reset_hw:
  741. bcm2835_spi_reset_hw(bs);
  742. bcm2835_spi_undo_prologue(bs);
  743. return ret;
  744. }
  745. static bool bcm2835_spi_can_dma(struct spi_controller *ctlr,
  746. struct spi_device *spi,
  747. struct spi_transfer *tfr)
  748. {
  749. /* we start DMA efforts only on bigger transfers */
  750. if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH)
  751. return false;
  752. /* return OK */
  753. return true;
  754. }
  755. static void bcm2835_dma_release(struct spi_controller *ctlr,
  756. struct bcm2835_spi *bs)
  757. {
  758. int i;
  759. if (ctlr->dma_tx) {
  760. dmaengine_terminate_sync(ctlr->dma_tx);
  761. if (bs->fill_tx_desc)
  762. dmaengine_desc_free(bs->fill_tx_desc);
  763. if (bs->fill_tx_addr)
  764. dma_unmap_page_attrs(ctlr->dma_tx->device->dev,
  765. bs->fill_tx_addr, sizeof(u32),
  766. DMA_TO_DEVICE,
  767. DMA_ATTR_SKIP_CPU_SYNC);
  768. dma_release_channel(ctlr->dma_tx);
  769. ctlr->dma_tx = NULL;
  770. }
  771. if (ctlr->dma_rx) {
  772. dmaengine_terminate_sync(ctlr->dma_rx);
  773. for (i = 0; i < BCM2835_SPI_NUM_CS; i++)
  774. if (bs->clear_rx_desc[i])
  775. dmaengine_desc_free(bs->clear_rx_desc[i]);
  776. if (bs->clear_rx_addr)
  777. dma_unmap_single(ctlr->dma_rx->device->dev,
  778. bs->clear_rx_addr,
  779. sizeof(bs->clear_rx_cs),
  780. DMA_TO_DEVICE);
  781. dma_release_channel(ctlr->dma_rx);
  782. ctlr->dma_rx = NULL;
  783. }
  784. }
  785. static int bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev,
  786. struct bcm2835_spi *bs)
  787. {
  788. struct dma_slave_config slave_config;
  789. const __be32 *addr;
  790. dma_addr_t dma_reg_base;
  791. int ret, i;
  792. /* base address in dma-space */
  793. addr = of_get_address(ctlr->dev.of_node, 0, NULL, NULL);
  794. if (!addr) {
  795. dev_err(dev, "could not get DMA-register address - not using dma mode\n");
  796. /* Fall back to interrupt mode */
  797. return 0;
  798. }
  799. dma_reg_base = be32_to_cpup(addr);
  800. /* get tx/rx dma */
  801. ctlr->dma_tx = dma_request_chan(dev, "tx");
  802. if (IS_ERR(ctlr->dma_tx)) {
  803. dev_err(dev, "no tx-dma configuration found - not using dma mode\n");
  804. ret = PTR_ERR(ctlr->dma_tx);
  805. ctlr->dma_tx = NULL;
  806. goto err;
  807. }
  808. ctlr->dma_rx = dma_request_chan(dev, "rx");
  809. if (IS_ERR(ctlr->dma_rx)) {
  810. dev_err(dev, "no rx-dma configuration found - not using dma mode\n");
  811. ret = PTR_ERR(ctlr->dma_rx);
  812. ctlr->dma_rx = NULL;
  813. goto err_release;
  814. }
  815. /*
  816. * The TX DMA channel either copies a transfer's TX buffer to the FIFO
  817. * or, in case of an RX-only transfer, cyclically copies from the zero
  818. * page to the FIFO using a preallocated, reusable descriptor.
  819. */
  820. slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
  821. slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  822. ret = dmaengine_slave_config(ctlr->dma_tx, &slave_config);
  823. if (ret)
  824. goto err_config;
  825. bs->fill_tx_addr = dma_map_page_attrs(ctlr->dma_tx->device->dev,
  826. ZERO_PAGE(0), 0, sizeof(u32),
  827. DMA_TO_DEVICE,
  828. DMA_ATTR_SKIP_CPU_SYNC);
  829. if (dma_mapping_error(ctlr->dma_tx->device->dev, bs->fill_tx_addr)) {
  830. dev_err(dev, "cannot map zero page - not using DMA mode\n");
  831. bs->fill_tx_addr = 0;
  832. ret = -ENOMEM;
  833. goto err_release;
  834. }
  835. bs->fill_tx_desc = dmaengine_prep_dma_cyclic(ctlr->dma_tx,
  836. bs->fill_tx_addr,
  837. sizeof(u32), 0,
  838. DMA_MEM_TO_DEV, 0);
  839. if (!bs->fill_tx_desc) {
  840. dev_err(dev, "cannot prepare fill_tx_desc - not using DMA mode\n");
  841. ret = -ENOMEM;
  842. goto err_release;
  843. }
  844. ret = dmaengine_desc_set_reuse(bs->fill_tx_desc);
  845. if (ret) {
  846. dev_err(dev, "cannot reuse fill_tx_desc - not using DMA mode\n");
  847. goto err_release;
  848. }
  849. /*
  850. * The RX DMA channel is used bidirectionally: It either reads the
  851. * RX FIFO or, in case of a TX-only transfer, cyclically writes a
  852. * precalculated value to the CS register to clear the RX FIFO.
  853. */
  854. slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
  855. slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  856. slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_CS);
  857. slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  858. ret = dmaengine_slave_config(ctlr->dma_rx, &slave_config);
  859. if (ret)
  860. goto err_config;
  861. bs->clear_rx_addr = dma_map_single(ctlr->dma_rx->device->dev,
  862. bs->clear_rx_cs,
  863. sizeof(bs->clear_rx_cs),
  864. DMA_TO_DEVICE);
  865. if (dma_mapping_error(ctlr->dma_rx->device->dev, bs->clear_rx_addr)) {
  866. dev_err(dev, "cannot map clear_rx_cs - not using DMA mode\n");
  867. bs->clear_rx_addr = 0;
  868. ret = -ENOMEM;
  869. goto err_release;
  870. }
  871. for (i = 0; i < BCM2835_SPI_NUM_CS; i++) {
  872. bs->clear_rx_desc[i] = dmaengine_prep_dma_cyclic(ctlr->dma_rx,
  873. bs->clear_rx_addr + i * sizeof(u32),
  874. sizeof(u32), 0,
  875. DMA_MEM_TO_DEV, 0);
  876. if (!bs->clear_rx_desc[i]) {
  877. dev_err(dev, "cannot prepare clear_rx_desc - not using DMA mode\n");
  878. ret = -ENOMEM;
  879. goto err_release;
  880. }
  881. ret = dmaengine_desc_set_reuse(bs->clear_rx_desc[i]);
  882. if (ret) {
  883. dev_err(dev, "cannot reuse clear_rx_desc - not using DMA mode\n");
  884. goto err_release;
  885. }
  886. }
  887. /* all went well, so set can_dma */
  888. ctlr->can_dma = bcm2835_spi_can_dma;
  889. return 0;
  890. err_config:
  891. dev_err(dev, "issue configuring dma: %d - not using DMA mode\n",
  892. ret);
  893. err_release:
  894. bcm2835_dma_release(ctlr, bs);
  895. err:
  896. /*
  897. * Only report error for deferred probing, otherwise fall back to
  898. * interrupt mode
  899. */
  900. if (ret != -EPROBE_DEFER)
  901. ret = 0;
  902. return ret;
  903. }
  904. static int bcm2835_spi_transfer_one_poll(struct spi_controller *ctlr,
  905. struct spi_device *spi,
  906. struct spi_transfer *tfr,
  907. u32 cs)
  908. {
  909. struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
  910. unsigned long timeout;
  911. /* update usage statistics */
  912. bs->count_transfer_polling++;
  913. /* enable HW block without interrupts */
  914. bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
  915. /* fill in the fifo before timeout calculations
  916. * if we are interrupted here, then the data is
  917. * getting transferred by the HW while we are interrupted
  918. */
  919. bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
  920. /* set the timeout to at least 2 jiffies */
  921. timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
  922. /* loop until finished the transfer */
  923. while (bs->rx_len) {
  924. /* fill in tx fifo with remaining data */
  925. bcm2835_wr_fifo(bs);
  926. /* read from fifo as much as possible */
  927. bcm2835_rd_fifo(bs);
  928. /* if there is still data pending to read
  929. * then check the timeout
  930. */
  931. if (bs->rx_len && time_after(jiffies, timeout)) {
  932. dev_dbg_ratelimited(&spi->dev,
  933. "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
  934. jiffies - timeout,
  935. bs->tx_len, bs->rx_len);
  936. /* fall back to interrupt mode */
  937. /* update usage statistics */
  938. bs->count_transfer_irq_after_polling++;
  939. return bcm2835_spi_transfer_one_irq(ctlr, spi,
  940. tfr, cs, false);
  941. }
  942. }
  943. /* Transfer complete - reset SPI HW */
  944. bcm2835_spi_reset_hw(bs);
  945. /* and return without waiting for completion */
  946. return 0;
  947. }
  948. static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
  949. struct spi_device *spi,
  950. struct spi_transfer *tfr)
  951. {
  952. struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
  953. unsigned long spi_hz, cdiv;
  954. unsigned long hz_per_byte, byte_limit;
  955. u32 cs = bs->prepare_cs[spi->chip_select];
  956. /* set clock */
  957. spi_hz = tfr->speed_hz;
  958. if (spi_hz >= bs->clk_hz / 2) {
  959. cdiv = 2; /* clk_hz/2 is the fastest we can go */
  960. } else if (spi_hz) {
  961. /* CDIV must be a multiple of two */
  962. cdiv = DIV_ROUND_UP(bs->clk_hz, spi_hz);
  963. cdiv += (cdiv % 2);
  964. if (cdiv >= 65536)
  965. cdiv = 0; /* 0 is the slowest we can go */
  966. } else {
  967. cdiv = 0; /* 0 is the slowest we can go */
  968. }
  969. tfr->effective_speed_hz = cdiv ? (bs->clk_hz / cdiv) : (bs->clk_hz / 65536);
  970. bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
  971. /* handle all the 3-wire mode */
  972. if (spi->mode & SPI_3WIRE && tfr->rx_buf)
  973. cs |= BCM2835_SPI_CS_REN;
  974. /* set transmit buffers and length */
  975. bs->tx_buf = tfr->tx_buf;
  976. bs->rx_buf = tfr->rx_buf;
  977. bs->tx_len = tfr->len;
  978. bs->rx_len = tfr->len;
  979. /* Calculate the estimated time in us the transfer runs. Note that
  980. * there is 1 idle clocks cycles after each byte getting transferred
  981. * so we have 9 cycles/byte. This is used to find the number of Hz
  982. * per byte per polling limit. E.g., we can transfer 1 byte in 30 us
  983. * per 300,000 Hz of bus clock.
  984. */
  985. hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
  986. byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1;
  987. /* run in polling mode for short transfers */
  988. if (tfr->len < byte_limit)
  989. return bcm2835_spi_transfer_one_poll(ctlr, spi, tfr, cs);
  990. /* run in dma mode if conditions are right
  991. * Note that unlike poll or interrupt mode DMA mode does not have
  992. * this 1 idle clock cycle pattern but runs the spi clock without gaps
  993. */
  994. if (ctlr->can_dma && bcm2835_spi_can_dma(ctlr, spi, tfr))
  995. return bcm2835_spi_transfer_one_dma(ctlr, spi, tfr, cs);
  996. /* run in interrupt-mode */
  997. return bcm2835_spi_transfer_one_irq(ctlr, spi, tfr, cs, true);
  998. }
  999. static int bcm2835_spi_prepare_message(struct spi_controller *ctlr,
  1000. struct spi_message *msg)
  1001. {
  1002. struct spi_device *spi = msg->spi;
  1003. struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
  1004. int ret;
  1005. if (ctlr->can_dma) {
  1006. /*
  1007. * DMA transfers are limited to 16 bit (0 to 65535 bytes) by
  1008. * the SPI HW due to DLEN. Split up transfers (32-bit FIFO
  1009. * aligned) if the limit is exceeded.
  1010. */
  1011. ret = spi_split_transfers_maxsize(ctlr, msg, 65532,
  1012. GFP_KERNEL | GFP_DMA);
  1013. if (ret)
  1014. return ret;
  1015. }
  1016. /*
  1017. * Set up clock polarity before spi_transfer_one_message() asserts
  1018. * chip select to avoid a gratuitous clock signal edge.
  1019. */
  1020. bcm2835_wr(bs, BCM2835_SPI_CS, bs->prepare_cs[spi->chip_select]);
  1021. return 0;
  1022. }
  1023. static void bcm2835_spi_handle_err(struct spi_controller *ctlr,
  1024. struct spi_message *msg)
  1025. {
  1026. struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
  1027. /* if an error occurred and we have an active dma, then terminate */
  1028. dmaengine_terminate_sync(ctlr->dma_tx);
  1029. bs->tx_dma_active = false;
  1030. dmaengine_terminate_sync(ctlr->dma_rx);
  1031. bs->rx_dma_active = false;
  1032. bcm2835_spi_undo_prologue(bs);
  1033. /* and reset */
  1034. bcm2835_spi_reset_hw(bs);
  1035. }
  1036. static int chip_match_name(struct gpio_chip *chip, void *data)
  1037. {
  1038. return !strcmp(chip->label, data);
  1039. }
  1040. static int bcm2835_spi_setup(struct spi_device *spi)
  1041. {
  1042. struct spi_controller *ctlr = spi->controller;
  1043. struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
  1044. struct gpio_chip *chip;
  1045. u32 cs;
  1046. if (spi->chip_select >= BCM2835_SPI_NUM_CS) {
  1047. dev_err(&spi->dev, "only %d chip-selects supported\n",
  1048. BCM2835_SPI_NUM_CS - 1);
  1049. return -EINVAL;
  1050. }
  1051. /*
  1052. * Precalculate SPI slave's CS register value for ->prepare_message():
  1053. * The driver always uses software-controlled GPIO chip select, hence
  1054. * set the hardware-controlled native chip select to an invalid value
  1055. * to prevent it from interfering.
  1056. */
  1057. cs = BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
  1058. if (spi->mode & SPI_CPOL)
  1059. cs |= BCM2835_SPI_CS_CPOL;
  1060. if (spi->mode & SPI_CPHA)
  1061. cs |= BCM2835_SPI_CS_CPHA;
  1062. bs->prepare_cs[spi->chip_select] = cs;
  1063. /*
  1064. * Precalculate SPI slave's CS register value to clear RX FIFO
  1065. * in case of a TX-only DMA transfer.
  1066. */
  1067. if (ctlr->dma_rx) {
  1068. bs->clear_rx_cs[spi->chip_select] = cs |
  1069. BCM2835_SPI_CS_TA |
  1070. BCM2835_SPI_CS_DMAEN |
  1071. BCM2835_SPI_CS_CLEAR_RX;
  1072. dma_sync_single_for_device(ctlr->dma_rx->device->dev,
  1073. bs->clear_rx_addr,
  1074. sizeof(bs->clear_rx_cs),
  1075. DMA_TO_DEVICE);
  1076. }
  1077. /*
  1078. * sanity checking the native-chipselects
  1079. */
  1080. if (spi->mode & SPI_NO_CS)
  1081. return 0;
  1082. /*
  1083. * The SPI core has successfully requested the CS GPIO line from the
  1084. * device tree, so we are done.
  1085. */
  1086. if (spi->cs_gpiod)
  1087. return 0;
  1088. if (spi->chip_select > 1) {
  1089. /* error in the case of native CS requested with CS > 1
  1090. * officially there is a CS2, but it is not documented
  1091. * which GPIO is connected with that...
  1092. */
  1093. dev_err(&spi->dev,
  1094. "setup: only two native chip-selects are supported\n");
  1095. return -EINVAL;
  1096. }
  1097. /*
  1098. * Translate native CS to GPIO
  1099. *
  1100. * FIXME: poking around in the gpiolib internals like this is
  1101. * not very good practice. Find a way to locate the real problem
  1102. * and fix it. Why is the GPIO descriptor in spi->cs_gpiod
  1103. * sometimes not assigned correctly? Erroneous device trees?
  1104. */
  1105. /* get the gpio chip for the base */
  1106. chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
  1107. if (!chip)
  1108. return 0;
  1109. spi->cs_gpiod = gpiochip_request_own_desc(chip, 8 - spi->chip_select,
  1110. DRV_NAME,
  1111. GPIO_LOOKUP_FLAGS_DEFAULT,
  1112. GPIOD_OUT_LOW);
  1113. if (IS_ERR(spi->cs_gpiod))
  1114. return PTR_ERR(spi->cs_gpiod);
  1115. /* and set up the "mode" and level */
  1116. dev_info(&spi->dev, "setting up native-CS%i to use GPIO\n",
  1117. spi->chip_select);
  1118. return 0;
  1119. }
  1120. static int bcm2835_spi_probe(struct platform_device *pdev)
  1121. {
  1122. struct spi_controller *ctlr;
  1123. struct bcm2835_spi *bs;
  1124. int err;
  1125. ctlr = devm_spi_alloc_master(&pdev->dev, ALIGN(sizeof(*bs),
  1126. dma_get_cache_alignment()));
  1127. if (!ctlr)
  1128. return -ENOMEM;
  1129. platform_set_drvdata(pdev, ctlr);
  1130. ctlr->use_gpio_descriptors = true;
  1131. ctlr->mode_bits = BCM2835_SPI_MODE_BITS;
  1132. ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
  1133. ctlr->num_chipselect = 3;
  1134. ctlr->setup = bcm2835_spi_setup;
  1135. ctlr->transfer_one = bcm2835_spi_transfer_one;
  1136. ctlr->handle_err = bcm2835_spi_handle_err;
  1137. ctlr->prepare_message = bcm2835_spi_prepare_message;
  1138. ctlr->dev.of_node = pdev->dev.of_node;
  1139. bs = spi_controller_get_devdata(ctlr);
  1140. bs->ctlr = ctlr;
  1141. bs->regs = devm_platform_ioremap_resource(pdev, 0);
  1142. if (IS_ERR(bs->regs))
  1143. return PTR_ERR(bs->regs);
  1144. bs->clk = devm_clk_get(&pdev->dev, NULL);
  1145. if (IS_ERR(bs->clk))
  1146. return dev_err_probe(&pdev->dev, PTR_ERR(bs->clk),
  1147. "could not get clk\n");
  1148. bs->irq = platform_get_irq(pdev, 0);
  1149. if (bs->irq <= 0)
  1150. return bs->irq ? bs->irq : -ENODEV;
  1151. clk_prepare_enable(bs->clk);
  1152. bs->clk_hz = clk_get_rate(bs->clk);
  1153. err = bcm2835_dma_init(ctlr, &pdev->dev, bs);
  1154. if (err)
  1155. goto out_clk_disable;
  1156. /* initialise the hardware with the default polarities */
  1157. bcm2835_wr(bs, BCM2835_SPI_CS,
  1158. BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
  1159. err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
  1160. dev_name(&pdev->dev), bs);
  1161. if (err) {
  1162. dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
  1163. goto out_dma_release;
  1164. }
  1165. err = spi_register_controller(ctlr);
  1166. if (err) {
  1167. dev_err(&pdev->dev, "could not register SPI controller: %d\n",
  1168. err);
  1169. goto out_dma_release;
  1170. }
  1171. bcm2835_debugfs_create(bs, dev_name(&pdev->dev));
  1172. return 0;
  1173. out_dma_release:
  1174. bcm2835_dma_release(ctlr, bs);
  1175. out_clk_disable:
  1176. clk_disable_unprepare(bs->clk);
  1177. return err;
  1178. }
  1179. static int bcm2835_spi_remove(struct platform_device *pdev)
  1180. {
  1181. struct spi_controller *ctlr = platform_get_drvdata(pdev);
  1182. struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
  1183. bcm2835_debugfs_remove(bs);
  1184. spi_unregister_controller(ctlr);
  1185. bcm2835_dma_release(ctlr, bs);
  1186. /* Clear FIFOs, and disable the HW block */
  1187. bcm2835_wr(bs, BCM2835_SPI_CS,
  1188. BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
  1189. clk_disable_unprepare(bs->clk);
  1190. return 0;
  1191. }
  1192. static void bcm2835_spi_shutdown(struct platform_device *pdev)
  1193. {
  1194. int ret;
  1195. ret = bcm2835_spi_remove(pdev);
  1196. if (ret)
  1197. dev_err(&pdev->dev, "failed to shutdown\n");
  1198. }
  1199. static const struct of_device_id bcm2835_spi_match[] = {
  1200. { .compatible = "brcm,bcm2835-spi", },
  1201. {}
  1202. };
  1203. MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
  1204. static struct platform_driver bcm2835_spi_driver = {
  1205. .driver = {
  1206. .name = DRV_NAME,
  1207. .of_match_table = bcm2835_spi_match,
  1208. },
  1209. .probe = bcm2835_spi_probe,
  1210. .remove = bcm2835_spi_remove,
  1211. .shutdown = bcm2835_spi_shutdown,
  1212. };
  1213. module_platform_driver(bcm2835_spi_driver);
  1214. MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
  1215. MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
  1216. MODULE_LICENSE("GPL");