spi-atmel.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for Atmel AT32 and AT91 SPI Controllers
  4. *
  5. * Copyright (C) 2006 Atmel Corporation
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/clk.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/delay.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/dmaengine.h>
  14. #include <linux/err.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/slab.h>
  18. #include <linux/of.h>
  19. #include <linux/io.h>
  20. #include <linux/gpio/consumer.h>
  21. #include <linux/pinctrl/consumer.h>
  22. #include <linux/pm_runtime.h>
  23. #include <trace/events/spi.h>
  24. /* SPI register offsets */
  25. #define SPI_CR 0x0000
  26. #define SPI_MR 0x0004
  27. #define SPI_RDR 0x0008
  28. #define SPI_TDR 0x000c
  29. #define SPI_SR 0x0010
  30. #define SPI_IER 0x0014
  31. #define SPI_IDR 0x0018
  32. #define SPI_IMR 0x001c
  33. #define SPI_CSR0 0x0030
  34. #define SPI_CSR1 0x0034
  35. #define SPI_CSR2 0x0038
  36. #define SPI_CSR3 0x003c
  37. #define SPI_FMR 0x0040
  38. #define SPI_FLR 0x0044
  39. #define SPI_VERSION 0x00fc
  40. #define SPI_RPR 0x0100
  41. #define SPI_RCR 0x0104
  42. #define SPI_TPR 0x0108
  43. #define SPI_TCR 0x010c
  44. #define SPI_RNPR 0x0110
  45. #define SPI_RNCR 0x0114
  46. #define SPI_TNPR 0x0118
  47. #define SPI_TNCR 0x011c
  48. #define SPI_PTCR 0x0120
  49. #define SPI_PTSR 0x0124
  50. /* Bitfields in CR */
  51. #define SPI_SPIEN_OFFSET 0
  52. #define SPI_SPIEN_SIZE 1
  53. #define SPI_SPIDIS_OFFSET 1
  54. #define SPI_SPIDIS_SIZE 1
  55. #define SPI_SWRST_OFFSET 7
  56. #define SPI_SWRST_SIZE 1
  57. #define SPI_LASTXFER_OFFSET 24
  58. #define SPI_LASTXFER_SIZE 1
  59. #define SPI_TXFCLR_OFFSET 16
  60. #define SPI_TXFCLR_SIZE 1
  61. #define SPI_RXFCLR_OFFSET 17
  62. #define SPI_RXFCLR_SIZE 1
  63. #define SPI_FIFOEN_OFFSET 30
  64. #define SPI_FIFOEN_SIZE 1
  65. #define SPI_FIFODIS_OFFSET 31
  66. #define SPI_FIFODIS_SIZE 1
  67. /* Bitfields in MR */
  68. #define SPI_MSTR_OFFSET 0
  69. #define SPI_MSTR_SIZE 1
  70. #define SPI_PS_OFFSET 1
  71. #define SPI_PS_SIZE 1
  72. #define SPI_PCSDEC_OFFSET 2
  73. #define SPI_PCSDEC_SIZE 1
  74. #define SPI_FDIV_OFFSET 3
  75. #define SPI_FDIV_SIZE 1
  76. #define SPI_MODFDIS_OFFSET 4
  77. #define SPI_MODFDIS_SIZE 1
  78. #define SPI_WDRBT_OFFSET 5
  79. #define SPI_WDRBT_SIZE 1
  80. #define SPI_LLB_OFFSET 7
  81. #define SPI_LLB_SIZE 1
  82. #define SPI_PCS_OFFSET 16
  83. #define SPI_PCS_SIZE 4
  84. #define SPI_DLYBCS_OFFSET 24
  85. #define SPI_DLYBCS_SIZE 8
  86. /* Bitfields in RDR */
  87. #define SPI_RD_OFFSET 0
  88. #define SPI_RD_SIZE 16
  89. /* Bitfields in TDR */
  90. #define SPI_TD_OFFSET 0
  91. #define SPI_TD_SIZE 16
  92. /* Bitfields in SR */
  93. #define SPI_RDRF_OFFSET 0
  94. #define SPI_RDRF_SIZE 1
  95. #define SPI_TDRE_OFFSET 1
  96. #define SPI_TDRE_SIZE 1
  97. #define SPI_MODF_OFFSET 2
  98. #define SPI_MODF_SIZE 1
  99. #define SPI_OVRES_OFFSET 3
  100. #define SPI_OVRES_SIZE 1
  101. #define SPI_ENDRX_OFFSET 4
  102. #define SPI_ENDRX_SIZE 1
  103. #define SPI_ENDTX_OFFSET 5
  104. #define SPI_ENDTX_SIZE 1
  105. #define SPI_RXBUFF_OFFSET 6
  106. #define SPI_RXBUFF_SIZE 1
  107. #define SPI_TXBUFE_OFFSET 7
  108. #define SPI_TXBUFE_SIZE 1
  109. #define SPI_NSSR_OFFSET 8
  110. #define SPI_NSSR_SIZE 1
  111. #define SPI_TXEMPTY_OFFSET 9
  112. #define SPI_TXEMPTY_SIZE 1
  113. #define SPI_SPIENS_OFFSET 16
  114. #define SPI_SPIENS_SIZE 1
  115. #define SPI_TXFEF_OFFSET 24
  116. #define SPI_TXFEF_SIZE 1
  117. #define SPI_TXFFF_OFFSET 25
  118. #define SPI_TXFFF_SIZE 1
  119. #define SPI_TXFTHF_OFFSET 26
  120. #define SPI_TXFTHF_SIZE 1
  121. #define SPI_RXFEF_OFFSET 27
  122. #define SPI_RXFEF_SIZE 1
  123. #define SPI_RXFFF_OFFSET 28
  124. #define SPI_RXFFF_SIZE 1
  125. #define SPI_RXFTHF_OFFSET 29
  126. #define SPI_RXFTHF_SIZE 1
  127. #define SPI_TXFPTEF_OFFSET 30
  128. #define SPI_TXFPTEF_SIZE 1
  129. #define SPI_RXFPTEF_OFFSET 31
  130. #define SPI_RXFPTEF_SIZE 1
  131. /* Bitfields in CSR0 */
  132. #define SPI_CPOL_OFFSET 0
  133. #define SPI_CPOL_SIZE 1
  134. #define SPI_NCPHA_OFFSET 1
  135. #define SPI_NCPHA_SIZE 1
  136. #define SPI_CSAAT_OFFSET 3
  137. #define SPI_CSAAT_SIZE 1
  138. #define SPI_BITS_OFFSET 4
  139. #define SPI_BITS_SIZE 4
  140. #define SPI_SCBR_OFFSET 8
  141. #define SPI_SCBR_SIZE 8
  142. #define SPI_DLYBS_OFFSET 16
  143. #define SPI_DLYBS_SIZE 8
  144. #define SPI_DLYBCT_OFFSET 24
  145. #define SPI_DLYBCT_SIZE 8
  146. /* Bitfields in RCR */
  147. #define SPI_RXCTR_OFFSET 0
  148. #define SPI_RXCTR_SIZE 16
  149. /* Bitfields in TCR */
  150. #define SPI_TXCTR_OFFSET 0
  151. #define SPI_TXCTR_SIZE 16
  152. /* Bitfields in RNCR */
  153. #define SPI_RXNCR_OFFSET 0
  154. #define SPI_RXNCR_SIZE 16
  155. /* Bitfields in TNCR */
  156. #define SPI_TXNCR_OFFSET 0
  157. #define SPI_TXNCR_SIZE 16
  158. /* Bitfields in PTCR */
  159. #define SPI_RXTEN_OFFSET 0
  160. #define SPI_RXTEN_SIZE 1
  161. #define SPI_RXTDIS_OFFSET 1
  162. #define SPI_RXTDIS_SIZE 1
  163. #define SPI_TXTEN_OFFSET 8
  164. #define SPI_TXTEN_SIZE 1
  165. #define SPI_TXTDIS_OFFSET 9
  166. #define SPI_TXTDIS_SIZE 1
  167. /* Bitfields in FMR */
  168. #define SPI_TXRDYM_OFFSET 0
  169. #define SPI_TXRDYM_SIZE 2
  170. #define SPI_RXRDYM_OFFSET 4
  171. #define SPI_RXRDYM_SIZE 2
  172. #define SPI_TXFTHRES_OFFSET 16
  173. #define SPI_TXFTHRES_SIZE 6
  174. #define SPI_RXFTHRES_OFFSET 24
  175. #define SPI_RXFTHRES_SIZE 6
  176. /* Bitfields in FLR */
  177. #define SPI_TXFL_OFFSET 0
  178. #define SPI_TXFL_SIZE 6
  179. #define SPI_RXFL_OFFSET 16
  180. #define SPI_RXFL_SIZE 6
  181. /* Constants for BITS */
  182. #define SPI_BITS_8_BPT 0
  183. #define SPI_BITS_9_BPT 1
  184. #define SPI_BITS_10_BPT 2
  185. #define SPI_BITS_11_BPT 3
  186. #define SPI_BITS_12_BPT 4
  187. #define SPI_BITS_13_BPT 5
  188. #define SPI_BITS_14_BPT 6
  189. #define SPI_BITS_15_BPT 7
  190. #define SPI_BITS_16_BPT 8
  191. #define SPI_ONE_DATA 0
  192. #define SPI_TWO_DATA 1
  193. #define SPI_FOUR_DATA 2
  194. /* Bit manipulation macros */
  195. #define SPI_BIT(name) \
  196. (1 << SPI_##name##_OFFSET)
  197. #define SPI_BF(name, value) \
  198. (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
  199. #define SPI_BFEXT(name, value) \
  200. (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
  201. #define SPI_BFINS(name, value, old) \
  202. (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
  203. | SPI_BF(name, value))
  204. /* Register access macros */
  205. #define spi_readl(port, reg) \
  206. readl_relaxed((port)->regs + SPI_##reg)
  207. #define spi_writel(port, reg, value) \
  208. writel_relaxed((value), (port)->regs + SPI_##reg)
  209. #define spi_writew(port, reg, value) \
  210. writew_relaxed((value), (port)->regs + SPI_##reg)
  211. /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
  212. * cache operations; better heuristics consider wordsize and bitrate.
  213. */
  214. #define DMA_MIN_BYTES 16
  215. #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
  216. #define AUTOSUSPEND_TIMEOUT 2000
  217. struct atmel_spi_caps {
  218. bool is_spi2;
  219. bool has_wdrbt;
  220. bool has_dma_support;
  221. bool has_pdc_support;
  222. };
  223. /*
  224. * The core SPI transfer engine just talks to a register bank to set up
  225. * DMA transfers; transfer queue progress is driven by IRQs. The clock
  226. * framework provides the base clock, subdivided for each spi_device.
  227. */
  228. struct atmel_spi {
  229. spinlock_t lock;
  230. unsigned long flags;
  231. phys_addr_t phybase;
  232. void __iomem *regs;
  233. int irq;
  234. struct clk *clk;
  235. struct platform_device *pdev;
  236. unsigned long spi_clk;
  237. struct spi_transfer *current_transfer;
  238. int current_remaining_bytes;
  239. int done_status;
  240. dma_addr_t dma_addr_rx_bbuf;
  241. dma_addr_t dma_addr_tx_bbuf;
  242. void *addr_rx_bbuf;
  243. void *addr_tx_bbuf;
  244. struct completion xfer_completion;
  245. struct atmel_spi_caps caps;
  246. bool use_dma;
  247. bool use_pdc;
  248. bool keep_cs;
  249. u32 fifo_size;
  250. u8 native_cs_free;
  251. u8 native_cs_for_gpio;
  252. };
  253. /* Controller-specific per-slave state */
  254. struct atmel_spi_device {
  255. u32 csr;
  256. };
  257. #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
  258. #define INVALID_DMA_ADDRESS 0xffffffff
  259. /*
  260. * Version 2 of the SPI controller has
  261. * - CR.LASTXFER
  262. * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
  263. * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
  264. * - SPI_CSRx.CSAAT
  265. * - SPI_CSRx.SBCR allows faster clocking
  266. */
  267. static bool atmel_spi_is_v2(struct atmel_spi *as)
  268. {
  269. return as->caps.is_spi2;
  270. }
  271. /*
  272. * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
  273. * they assume that spi slave device state will not change on deselect, so
  274. * that automagic deselection is OK. ("NPCSx rises if no data is to be
  275. * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
  276. * controllers have CSAAT and friends.
  277. *
  278. * Even controller newer than ar91rm9200, using GPIOs can make sens as
  279. * it lets us support active-high chipselects despite the controller's
  280. * belief that only active-low devices/systems exists.
  281. *
  282. * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
  283. * right when driven with GPIO. ("Mode Fault does not allow more than one
  284. * Master on Chip Select 0.") No workaround exists for that ... so for
  285. * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
  286. * and (c) will trigger that first erratum in some cases.
  287. */
  288. static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
  289. {
  290. struct atmel_spi_device *asd = spi->controller_state;
  291. int chip_select;
  292. u32 mr;
  293. if (spi->cs_gpiod)
  294. chip_select = as->native_cs_for_gpio;
  295. else
  296. chip_select = spi->chip_select;
  297. if (atmel_spi_is_v2(as)) {
  298. spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
  299. /* For the low SPI version, there is a issue that PDC transfer
  300. * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
  301. */
  302. spi_writel(as, CSR0, asd->csr);
  303. if (as->caps.has_wdrbt) {
  304. spi_writel(as, MR,
  305. SPI_BF(PCS, ~(0x01 << chip_select))
  306. | SPI_BIT(WDRBT)
  307. | SPI_BIT(MODFDIS)
  308. | SPI_BIT(MSTR));
  309. } else {
  310. spi_writel(as, MR,
  311. SPI_BF(PCS, ~(0x01 << chip_select))
  312. | SPI_BIT(MODFDIS)
  313. | SPI_BIT(MSTR));
  314. }
  315. mr = spi_readl(as, MR);
  316. if (spi->cs_gpiod)
  317. gpiod_set_value(spi->cs_gpiod, 1);
  318. } else {
  319. u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
  320. int i;
  321. u32 csr;
  322. /* Make sure clock polarity is correct */
  323. for (i = 0; i < spi->master->num_chipselect; i++) {
  324. csr = spi_readl(as, CSR0 + 4 * i);
  325. if ((csr ^ cpol) & SPI_BIT(CPOL))
  326. spi_writel(as, CSR0 + 4 * i,
  327. csr ^ SPI_BIT(CPOL));
  328. }
  329. mr = spi_readl(as, MR);
  330. mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
  331. if (spi->cs_gpiod)
  332. gpiod_set_value(spi->cs_gpiod, 1);
  333. spi_writel(as, MR, mr);
  334. }
  335. dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
  336. }
  337. static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
  338. {
  339. int chip_select;
  340. u32 mr;
  341. if (spi->cs_gpiod)
  342. chip_select = as->native_cs_for_gpio;
  343. else
  344. chip_select = spi->chip_select;
  345. /* only deactivate *this* device; sometimes transfers to
  346. * another device may be active when this routine is called.
  347. */
  348. mr = spi_readl(as, MR);
  349. if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) {
  350. mr = SPI_BFINS(PCS, 0xf, mr);
  351. spi_writel(as, MR, mr);
  352. }
  353. dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
  354. if (!spi->cs_gpiod)
  355. spi_writel(as, CR, SPI_BIT(LASTXFER));
  356. else
  357. gpiod_set_value(spi->cs_gpiod, 0);
  358. }
  359. static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
  360. {
  361. spin_lock_irqsave(&as->lock, as->flags);
  362. }
  363. static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
  364. {
  365. spin_unlock_irqrestore(&as->lock, as->flags);
  366. }
  367. static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
  368. {
  369. return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
  370. }
  371. static inline bool atmel_spi_use_dma(struct atmel_spi *as,
  372. struct spi_transfer *xfer)
  373. {
  374. return as->use_dma && xfer->len >= DMA_MIN_BYTES;
  375. }
  376. static bool atmel_spi_can_dma(struct spi_master *master,
  377. struct spi_device *spi,
  378. struct spi_transfer *xfer)
  379. {
  380. struct atmel_spi *as = spi_master_get_devdata(master);
  381. if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
  382. return atmel_spi_use_dma(as, xfer) &&
  383. !atmel_spi_is_vmalloc_xfer(xfer);
  384. else
  385. return atmel_spi_use_dma(as, xfer);
  386. }
  387. static int atmel_spi_dma_slave_config(struct atmel_spi *as,
  388. struct dma_slave_config *slave_config,
  389. u8 bits_per_word)
  390. {
  391. struct spi_master *master = platform_get_drvdata(as->pdev);
  392. int err = 0;
  393. if (bits_per_word > 8) {
  394. slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  395. slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  396. } else {
  397. slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  398. slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  399. }
  400. slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
  401. slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
  402. slave_config->src_maxburst = 1;
  403. slave_config->dst_maxburst = 1;
  404. slave_config->device_fc = false;
  405. /*
  406. * This driver uses fixed peripheral select mode (PS bit set to '0' in
  407. * the Mode Register).
  408. * So according to the datasheet, when FIFOs are available (and
  409. * enabled), the Transmit FIFO operates in Multiple Data Mode.
  410. * In this mode, up to 2 data, not 4, can be written into the Transmit
  411. * Data Register in a single access.
  412. * However, the first data has to be written into the lowest 16 bits and
  413. * the second data into the highest 16 bits of the Transmit
  414. * Data Register. For 8bit data (the most frequent case), it would
  415. * require to rework tx_buf so each data would actualy fit 16 bits.
  416. * So we'd rather write only one data at the time. Hence the transmit
  417. * path works the same whether FIFOs are available (and enabled) or not.
  418. */
  419. slave_config->direction = DMA_MEM_TO_DEV;
  420. if (dmaengine_slave_config(master->dma_tx, slave_config)) {
  421. dev_err(&as->pdev->dev,
  422. "failed to configure tx dma channel\n");
  423. err = -EINVAL;
  424. }
  425. /*
  426. * This driver configures the spi controller for master mode (MSTR bit
  427. * set to '1' in the Mode Register).
  428. * So according to the datasheet, when FIFOs are available (and
  429. * enabled), the Receive FIFO operates in Single Data Mode.
  430. * So the receive path works the same whether FIFOs are available (and
  431. * enabled) or not.
  432. */
  433. slave_config->direction = DMA_DEV_TO_MEM;
  434. if (dmaengine_slave_config(master->dma_rx, slave_config)) {
  435. dev_err(&as->pdev->dev,
  436. "failed to configure rx dma channel\n");
  437. err = -EINVAL;
  438. }
  439. return err;
  440. }
  441. static int atmel_spi_configure_dma(struct spi_master *master,
  442. struct atmel_spi *as)
  443. {
  444. struct dma_slave_config slave_config;
  445. struct device *dev = &as->pdev->dev;
  446. int err;
  447. dma_cap_mask_t mask;
  448. dma_cap_zero(mask);
  449. dma_cap_set(DMA_SLAVE, mask);
  450. master->dma_tx = dma_request_chan(dev, "tx");
  451. if (IS_ERR(master->dma_tx)) {
  452. err = dev_err_probe(dev, PTR_ERR(master->dma_tx),
  453. "No TX DMA channel, DMA is disabled\n");
  454. goto error_clear;
  455. }
  456. master->dma_rx = dma_request_chan(dev, "rx");
  457. if (IS_ERR(master->dma_rx)) {
  458. err = PTR_ERR(master->dma_rx);
  459. /*
  460. * No reason to check EPROBE_DEFER here since we have already
  461. * requested tx channel.
  462. */
  463. dev_err(dev, "No RX DMA channel, DMA is disabled\n");
  464. goto error;
  465. }
  466. err = atmel_spi_dma_slave_config(as, &slave_config, 8);
  467. if (err)
  468. goto error;
  469. dev_info(&as->pdev->dev,
  470. "Using %s (tx) and %s (rx) for DMA transfers\n",
  471. dma_chan_name(master->dma_tx),
  472. dma_chan_name(master->dma_rx));
  473. return 0;
  474. error:
  475. if (!IS_ERR(master->dma_rx))
  476. dma_release_channel(master->dma_rx);
  477. if (!IS_ERR(master->dma_tx))
  478. dma_release_channel(master->dma_tx);
  479. error_clear:
  480. master->dma_tx = master->dma_rx = NULL;
  481. return err;
  482. }
  483. static void atmel_spi_stop_dma(struct spi_master *master)
  484. {
  485. if (master->dma_rx)
  486. dmaengine_terminate_all(master->dma_rx);
  487. if (master->dma_tx)
  488. dmaengine_terminate_all(master->dma_tx);
  489. }
  490. static void atmel_spi_release_dma(struct spi_master *master)
  491. {
  492. if (master->dma_rx) {
  493. dma_release_channel(master->dma_rx);
  494. master->dma_rx = NULL;
  495. }
  496. if (master->dma_tx) {
  497. dma_release_channel(master->dma_tx);
  498. master->dma_tx = NULL;
  499. }
  500. }
  501. /* This function is called by the DMA driver from tasklet context */
  502. static void dma_callback(void *data)
  503. {
  504. struct spi_master *master = data;
  505. struct atmel_spi *as = spi_master_get_devdata(master);
  506. if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
  507. IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
  508. memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
  509. as->current_transfer->len);
  510. }
  511. complete(&as->xfer_completion);
  512. }
  513. /*
  514. * Next transfer using PIO without FIFO.
  515. */
  516. static void atmel_spi_next_xfer_single(struct spi_master *master,
  517. struct spi_transfer *xfer)
  518. {
  519. struct atmel_spi *as = spi_master_get_devdata(master);
  520. unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
  521. dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
  522. /* Make sure data is not remaining in RDR */
  523. spi_readl(as, RDR);
  524. while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
  525. spi_readl(as, RDR);
  526. cpu_relax();
  527. }
  528. if (xfer->bits_per_word > 8)
  529. spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
  530. else
  531. spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
  532. dev_dbg(master->dev.parent,
  533. " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
  534. xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
  535. xfer->bits_per_word);
  536. /* Enable relevant interrupts */
  537. spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
  538. }
  539. /*
  540. * Next transfer using PIO with FIFO.
  541. */
  542. static void atmel_spi_next_xfer_fifo(struct spi_master *master,
  543. struct spi_transfer *xfer)
  544. {
  545. struct atmel_spi *as = spi_master_get_devdata(master);
  546. u32 current_remaining_data, num_data;
  547. u32 offset = xfer->len - as->current_remaining_bytes;
  548. const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
  549. const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
  550. u16 td0, td1;
  551. u32 fifomr;
  552. dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
  553. /* Compute the number of data to transfer in the current iteration */
  554. current_remaining_data = ((xfer->bits_per_word > 8) ?
  555. ((u32)as->current_remaining_bytes >> 1) :
  556. (u32)as->current_remaining_bytes);
  557. num_data = min(current_remaining_data, as->fifo_size);
  558. /* Flush RX and TX FIFOs */
  559. spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
  560. while (spi_readl(as, FLR))
  561. cpu_relax();
  562. /* Set RX FIFO Threshold to the number of data to transfer */
  563. fifomr = spi_readl(as, FMR);
  564. spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
  565. /* Clear FIFO flags in the Status Register, especially RXFTHF */
  566. (void)spi_readl(as, SR);
  567. /* Fill TX FIFO */
  568. while (num_data >= 2) {
  569. if (xfer->bits_per_word > 8) {
  570. td0 = *words++;
  571. td1 = *words++;
  572. } else {
  573. td0 = *bytes++;
  574. td1 = *bytes++;
  575. }
  576. spi_writel(as, TDR, (td1 << 16) | td0);
  577. num_data -= 2;
  578. }
  579. if (num_data) {
  580. if (xfer->bits_per_word > 8)
  581. td0 = *words++;
  582. else
  583. td0 = *bytes++;
  584. spi_writew(as, TDR, td0);
  585. num_data--;
  586. }
  587. dev_dbg(master->dev.parent,
  588. " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
  589. xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
  590. xfer->bits_per_word);
  591. /*
  592. * Enable RX FIFO Threshold Flag interrupt to be notified about
  593. * transfer completion.
  594. */
  595. spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
  596. }
  597. /*
  598. * Next transfer using PIO.
  599. */
  600. static void atmel_spi_next_xfer_pio(struct spi_master *master,
  601. struct spi_transfer *xfer)
  602. {
  603. struct atmel_spi *as = spi_master_get_devdata(master);
  604. if (as->fifo_size)
  605. atmel_spi_next_xfer_fifo(master, xfer);
  606. else
  607. atmel_spi_next_xfer_single(master, xfer);
  608. }
  609. /*
  610. * Submit next transfer for DMA.
  611. */
  612. static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
  613. struct spi_transfer *xfer,
  614. u32 *plen)
  615. __must_hold(&as->lock)
  616. {
  617. struct atmel_spi *as = spi_master_get_devdata(master);
  618. struct dma_chan *rxchan = master->dma_rx;
  619. struct dma_chan *txchan = master->dma_tx;
  620. struct dma_async_tx_descriptor *rxdesc;
  621. struct dma_async_tx_descriptor *txdesc;
  622. struct dma_slave_config slave_config;
  623. dma_cookie_t cookie;
  624. dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
  625. /* Check that the channels are available */
  626. if (!rxchan || !txchan)
  627. return -ENODEV;
  628. /* release lock for DMA operations */
  629. atmel_spi_unlock(as);
  630. *plen = xfer->len;
  631. if (atmel_spi_dma_slave_config(as, &slave_config,
  632. xfer->bits_per_word))
  633. goto err_exit;
  634. /* Send both scatterlists */
  635. if (atmel_spi_is_vmalloc_xfer(xfer) &&
  636. IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
  637. rxdesc = dmaengine_prep_slave_single(rxchan,
  638. as->dma_addr_rx_bbuf,
  639. xfer->len,
  640. DMA_DEV_TO_MEM,
  641. DMA_PREP_INTERRUPT |
  642. DMA_CTRL_ACK);
  643. } else {
  644. rxdesc = dmaengine_prep_slave_sg(rxchan,
  645. xfer->rx_sg.sgl,
  646. xfer->rx_sg.nents,
  647. DMA_DEV_TO_MEM,
  648. DMA_PREP_INTERRUPT |
  649. DMA_CTRL_ACK);
  650. }
  651. if (!rxdesc)
  652. goto err_dma;
  653. if (atmel_spi_is_vmalloc_xfer(xfer) &&
  654. IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
  655. memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
  656. txdesc = dmaengine_prep_slave_single(txchan,
  657. as->dma_addr_tx_bbuf,
  658. xfer->len, DMA_MEM_TO_DEV,
  659. DMA_PREP_INTERRUPT |
  660. DMA_CTRL_ACK);
  661. } else {
  662. txdesc = dmaengine_prep_slave_sg(txchan,
  663. xfer->tx_sg.sgl,
  664. xfer->tx_sg.nents,
  665. DMA_MEM_TO_DEV,
  666. DMA_PREP_INTERRUPT |
  667. DMA_CTRL_ACK);
  668. }
  669. if (!txdesc)
  670. goto err_dma;
  671. dev_dbg(master->dev.parent,
  672. " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
  673. xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
  674. xfer->rx_buf, (unsigned long long)xfer->rx_dma);
  675. /* Enable relevant interrupts */
  676. spi_writel(as, IER, SPI_BIT(OVRES));
  677. /* Put the callback on the RX transfer only, that should finish last */
  678. rxdesc->callback = dma_callback;
  679. rxdesc->callback_param = master;
  680. /* Submit and fire RX and TX with TX last so we're ready to read! */
  681. cookie = rxdesc->tx_submit(rxdesc);
  682. if (dma_submit_error(cookie))
  683. goto err_dma;
  684. cookie = txdesc->tx_submit(txdesc);
  685. if (dma_submit_error(cookie))
  686. goto err_dma;
  687. rxchan->device->device_issue_pending(rxchan);
  688. txchan->device->device_issue_pending(txchan);
  689. /* take back lock */
  690. atmel_spi_lock(as);
  691. return 0;
  692. err_dma:
  693. spi_writel(as, IDR, SPI_BIT(OVRES));
  694. atmel_spi_stop_dma(master);
  695. err_exit:
  696. atmel_spi_lock(as);
  697. return -ENOMEM;
  698. }
  699. static void atmel_spi_next_xfer_data(struct spi_master *master,
  700. struct spi_transfer *xfer,
  701. dma_addr_t *tx_dma,
  702. dma_addr_t *rx_dma,
  703. u32 *plen)
  704. {
  705. *rx_dma = xfer->rx_dma + xfer->len - *plen;
  706. *tx_dma = xfer->tx_dma + xfer->len - *plen;
  707. if (*plen > master->max_dma_len)
  708. *plen = master->max_dma_len;
  709. }
  710. static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
  711. struct spi_device *spi,
  712. struct spi_transfer *xfer)
  713. {
  714. u32 scbr, csr;
  715. unsigned long bus_hz;
  716. int chip_select;
  717. if (spi->cs_gpiod)
  718. chip_select = as->native_cs_for_gpio;
  719. else
  720. chip_select = spi->chip_select;
  721. /* v1 chips start out at half the peripheral bus speed. */
  722. bus_hz = as->spi_clk;
  723. if (!atmel_spi_is_v2(as))
  724. bus_hz /= 2;
  725. /*
  726. * Calculate the lowest divider that satisfies the
  727. * constraint, assuming div32/fdiv/mbz == 0.
  728. */
  729. scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
  730. /*
  731. * If the resulting divider doesn't fit into the
  732. * register bitfield, we can't satisfy the constraint.
  733. */
  734. if (scbr >= (1 << SPI_SCBR_SIZE)) {
  735. dev_err(&spi->dev,
  736. "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
  737. xfer->speed_hz, scbr, bus_hz/255);
  738. return -EINVAL;
  739. }
  740. if (scbr == 0) {
  741. dev_err(&spi->dev,
  742. "setup: %d Hz too high, scbr %u; max %ld Hz\n",
  743. xfer->speed_hz, scbr, bus_hz);
  744. return -EINVAL;
  745. }
  746. csr = spi_readl(as, CSR0 + 4 * chip_select);
  747. csr = SPI_BFINS(SCBR, scbr, csr);
  748. spi_writel(as, CSR0 + 4 * chip_select, csr);
  749. xfer->effective_speed_hz = bus_hz / scbr;
  750. return 0;
  751. }
  752. /*
  753. * Submit next transfer for PDC.
  754. * lock is held, spi irq is blocked
  755. */
  756. static void atmel_spi_pdc_next_xfer(struct spi_master *master,
  757. struct spi_message *msg,
  758. struct spi_transfer *xfer)
  759. {
  760. struct atmel_spi *as = spi_master_get_devdata(master);
  761. u32 len;
  762. dma_addr_t tx_dma, rx_dma;
  763. spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
  764. len = as->current_remaining_bytes;
  765. atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
  766. as->current_remaining_bytes -= len;
  767. spi_writel(as, RPR, rx_dma);
  768. spi_writel(as, TPR, tx_dma);
  769. if (msg->spi->bits_per_word > 8)
  770. len >>= 1;
  771. spi_writel(as, RCR, len);
  772. spi_writel(as, TCR, len);
  773. dev_dbg(&msg->spi->dev,
  774. " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
  775. xfer, xfer->len, xfer->tx_buf,
  776. (unsigned long long)xfer->tx_dma, xfer->rx_buf,
  777. (unsigned long long)xfer->rx_dma);
  778. if (as->current_remaining_bytes) {
  779. len = as->current_remaining_bytes;
  780. atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
  781. as->current_remaining_bytes -= len;
  782. spi_writel(as, RNPR, rx_dma);
  783. spi_writel(as, TNPR, tx_dma);
  784. if (msg->spi->bits_per_word > 8)
  785. len >>= 1;
  786. spi_writel(as, RNCR, len);
  787. spi_writel(as, TNCR, len);
  788. dev_dbg(&msg->spi->dev,
  789. " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
  790. xfer, xfer->len, xfer->tx_buf,
  791. (unsigned long long)xfer->tx_dma, xfer->rx_buf,
  792. (unsigned long long)xfer->rx_dma);
  793. }
  794. /* REVISIT: We're waiting for RXBUFF before we start the next
  795. * transfer because we need to handle some difficult timing
  796. * issues otherwise. If we wait for TXBUFE in one transfer and
  797. * then starts waiting for RXBUFF in the next, it's difficult
  798. * to tell the difference between the RXBUFF interrupt we're
  799. * actually waiting for and the RXBUFF interrupt of the
  800. * previous transfer.
  801. *
  802. * It should be doable, though. Just not now...
  803. */
  804. spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
  805. spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
  806. }
  807. /*
  808. * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
  809. * - The buffer is either valid for CPU access, else NULL
  810. * - If the buffer is valid, so is its DMA address
  811. *
  812. * This driver manages the dma address unless message->is_dma_mapped.
  813. */
  814. static int
  815. atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
  816. {
  817. struct device *dev = &as->pdev->dev;
  818. xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
  819. if (xfer->tx_buf) {
  820. /* tx_buf is a const void* where we need a void * for the dma
  821. * mapping */
  822. void *nonconst_tx = (void *)xfer->tx_buf;
  823. xfer->tx_dma = dma_map_single(dev,
  824. nonconst_tx, xfer->len,
  825. DMA_TO_DEVICE);
  826. if (dma_mapping_error(dev, xfer->tx_dma))
  827. return -ENOMEM;
  828. }
  829. if (xfer->rx_buf) {
  830. xfer->rx_dma = dma_map_single(dev,
  831. xfer->rx_buf, xfer->len,
  832. DMA_FROM_DEVICE);
  833. if (dma_mapping_error(dev, xfer->rx_dma)) {
  834. if (xfer->tx_buf)
  835. dma_unmap_single(dev,
  836. xfer->tx_dma, xfer->len,
  837. DMA_TO_DEVICE);
  838. return -ENOMEM;
  839. }
  840. }
  841. return 0;
  842. }
  843. static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
  844. struct spi_transfer *xfer)
  845. {
  846. if (xfer->tx_dma != INVALID_DMA_ADDRESS)
  847. dma_unmap_single(master->dev.parent, xfer->tx_dma,
  848. xfer->len, DMA_TO_DEVICE);
  849. if (xfer->rx_dma != INVALID_DMA_ADDRESS)
  850. dma_unmap_single(master->dev.parent, xfer->rx_dma,
  851. xfer->len, DMA_FROM_DEVICE);
  852. }
  853. static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
  854. {
  855. spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
  856. }
  857. static void
  858. atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
  859. {
  860. u8 *rxp;
  861. u16 *rxp16;
  862. unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
  863. if (xfer->bits_per_word > 8) {
  864. rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
  865. *rxp16 = spi_readl(as, RDR);
  866. } else {
  867. rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
  868. *rxp = spi_readl(as, RDR);
  869. }
  870. if (xfer->bits_per_word > 8) {
  871. if (as->current_remaining_bytes > 2)
  872. as->current_remaining_bytes -= 2;
  873. else
  874. as->current_remaining_bytes = 0;
  875. } else {
  876. as->current_remaining_bytes--;
  877. }
  878. }
  879. static void
  880. atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
  881. {
  882. u32 fifolr = spi_readl(as, FLR);
  883. u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
  884. u32 offset = xfer->len - as->current_remaining_bytes;
  885. u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
  886. u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
  887. u16 rd; /* RD field is the lowest 16 bits of RDR */
  888. /* Update the number of remaining bytes to transfer */
  889. num_bytes = ((xfer->bits_per_word > 8) ?
  890. (num_data << 1) :
  891. num_data);
  892. if (as->current_remaining_bytes > num_bytes)
  893. as->current_remaining_bytes -= num_bytes;
  894. else
  895. as->current_remaining_bytes = 0;
  896. /* Handle odd number of bytes when data are more than 8bit width */
  897. if (xfer->bits_per_word > 8)
  898. as->current_remaining_bytes &= ~0x1;
  899. /* Read data */
  900. while (num_data) {
  901. rd = spi_readl(as, RDR);
  902. if (xfer->bits_per_word > 8)
  903. *words++ = rd;
  904. else
  905. *bytes++ = rd;
  906. num_data--;
  907. }
  908. }
  909. /* Called from IRQ
  910. *
  911. * Must update "current_remaining_bytes" to keep track of data
  912. * to transfer.
  913. */
  914. static void
  915. atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
  916. {
  917. if (as->fifo_size)
  918. atmel_spi_pump_fifo_data(as, xfer);
  919. else
  920. atmel_spi_pump_single_data(as, xfer);
  921. }
  922. /* Interrupt
  923. *
  924. * No need for locking in this Interrupt handler: done_status is the
  925. * only information modified.
  926. */
  927. static irqreturn_t
  928. atmel_spi_pio_interrupt(int irq, void *dev_id)
  929. {
  930. struct spi_master *master = dev_id;
  931. struct atmel_spi *as = spi_master_get_devdata(master);
  932. u32 status, pending, imr;
  933. struct spi_transfer *xfer;
  934. int ret = IRQ_NONE;
  935. imr = spi_readl(as, IMR);
  936. status = spi_readl(as, SR);
  937. pending = status & imr;
  938. if (pending & SPI_BIT(OVRES)) {
  939. ret = IRQ_HANDLED;
  940. spi_writel(as, IDR, SPI_BIT(OVRES));
  941. dev_warn(master->dev.parent, "overrun\n");
  942. /*
  943. * When we get an overrun, we disregard the current
  944. * transfer. Data will not be copied back from any
  945. * bounce buffer and msg->actual_len will not be
  946. * updated with the last xfer.
  947. *
  948. * We will also not process any remaning transfers in
  949. * the message.
  950. */
  951. as->done_status = -EIO;
  952. smp_wmb();
  953. /* Clear any overrun happening while cleaning up */
  954. spi_readl(as, SR);
  955. complete(&as->xfer_completion);
  956. } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
  957. atmel_spi_lock(as);
  958. if (as->current_remaining_bytes) {
  959. ret = IRQ_HANDLED;
  960. xfer = as->current_transfer;
  961. atmel_spi_pump_pio_data(as, xfer);
  962. if (!as->current_remaining_bytes)
  963. spi_writel(as, IDR, pending);
  964. complete(&as->xfer_completion);
  965. }
  966. atmel_spi_unlock(as);
  967. } else {
  968. WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
  969. ret = IRQ_HANDLED;
  970. spi_writel(as, IDR, pending);
  971. }
  972. return ret;
  973. }
  974. static irqreturn_t
  975. atmel_spi_pdc_interrupt(int irq, void *dev_id)
  976. {
  977. struct spi_master *master = dev_id;
  978. struct atmel_spi *as = spi_master_get_devdata(master);
  979. u32 status, pending, imr;
  980. int ret = IRQ_NONE;
  981. imr = spi_readl(as, IMR);
  982. status = spi_readl(as, SR);
  983. pending = status & imr;
  984. if (pending & SPI_BIT(OVRES)) {
  985. ret = IRQ_HANDLED;
  986. spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
  987. | SPI_BIT(OVRES)));
  988. /* Clear any overrun happening while cleaning up */
  989. spi_readl(as, SR);
  990. as->done_status = -EIO;
  991. complete(&as->xfer_completion);
  992. } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
  993. ret = IRQ_HANDLED;
  994. spi_writel(as, IDR, pending);
  995. complete(&as->xfer_completion);
  996. }
  997. return ret;
  998. }
  999. static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as)
  1000. {
  1001. struct spi_delay *delay = &spi->word_delay;
  1002. u32 value = delay->value;
  1003. switch (delay->unit) {
  1004. case SPI_DELAY_UNIT_NSECS:
  1005. value /= 1000;
  1006. break;
  1007. case SPI_DELAY_UNIT_USECS:
  1008. break;
  1009. default:
  1010. return -EINVAL;
  1011. }
  1012. return (as->spi_clk / 1000000 * value) >> 5;
  1013. }
  1014. static void initialize_native_cs_for_gpio(struct atmel_spi *as)
  1015. {
  1016. int i;
  1017. struct spi_master *master = platform_get_drvdata(as->pdev);
  1018. if (!as->native_cs_free)
  1019. return; /* already initialized */
  1020. if (!master->cs_gpiods)
  1021. return; /* No CS GPIO */
  1022. /*
  1023. * On the first version of the controller (AT91RM9200), CS0
  1024. * can't be used associated with GPIO
  1025. */
  1026. if (atmel_spi_is_v2(as))
  1027. i = 0;
  1028. else
  1029. i = 1;
  1030. for (; i < 4; i++)
  1031. if (master->cs_gpiods[i])
  1032. as->native_cs_free |= BIT(i);
  1033. if (as->native_cs_free)
  1034. as->native_cs_for_gpio = ffs(as->native_cs_free);
  1035. }
  1036. static int atmel_spi_setup(struct spi_device *spi)
  1037. {
  1038. struct atmel_spi *as;
  1039. struct atmel_spi_device *asd;
  1040. u32 csr;
  1041. unsigned int bits = spi->bits_per_word;
  1042. int chip_select;
  1043. int word_delay_csr;
  1044. as = spi_master_get_devdata(spi->master);
  1045. /* see notes above re chipselect */
  1046. if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
  1047. dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
  1048. return -EINVAL;
  1049. }
  1050. /* Setup() is called during spi_register_controller(aka
  1051. * spi_register_master) but after all membmers of the cs_gpiod
  1052. * array have been filled, so we can looked for which native
  1053. * CS will be free for using with GPIO
  1054. */
  1055. initialize_native_cs_for_gpio(as);
  1056. if (spi->cs_gpiod && as->native_cs_free) {
  1057. dev_err(&spi->dev,
  1058. "No native CS available to support this GPIO CS\n");
  1059. return -EBUSY;
  1060. }
  1061. if (spi->cs_gpiod)
  1062. chip_select = as->native_cs_for_gpio;
  1063. else
  1064. chip_select = spi->chip_select;
  1065. csr = SPI_BF(BITS, bits - 8);
  1066. if (spi->mode & SPI_CPOL)
  1067. csr |= SPI_BIT(CPOL);
  1068. if (!(spi->mode & SPI_CPHA))
  1069. csr |= SPI_BIT(NCPHA);
  1070. if (!spi->cs_gpiod)
  1071. csr |= SPI_BIT(CSAAT);
  1072. csr |= SPI_BF(DLYBS, 0);
  1073. word_delay_csr = atmel_word_delay_csr(spi, as);
  1074. if (word_delay_csr < 0)
  1075. return word_delay_csr;
  1076. /* DLYBCT adds delays between words. This is useful for slow devices
  1077. * that need a bit of time to setup the next transfer.
  1078. */
  1079. csr |= SPI_BF(DLYBCT, word_delay_csr);
  1080. asd = spi->controller_state;
  1081. if (!asd) {
  1082. asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
  1083. if (!asd)
  1084. return -ENOMEM;
  1085. spi->controller_state = asd;
  1086. }
  1087. asd->csr = csr;
  1088. dev_dbg(&spi->dev,
  1089. "setup: bpw %u mode 0x%x -> csr%d %08x\n",
  1090. bits, spi->mode, spi->chip_select, csr);
  1091. if (!atmel_spi_is_v2(as))
  1092. spi_writel(as, CSR0 + 4 * chip_select, csr);
  1093. return 0;
  1094. }
  1095. static int atmel_spi_one_transfer(struct spi_master *master,
  1096. struct spi_message *msg,
  1097. struct spi_transfer *xfer)
  1098. {
  1099. struct atmel_spi *as;
  1100. struct spi_device *spi = msg->spi;
  1101. u8 bits;
  1102. u32 len;
  1103. struct atmel_spi_device *asd;
  1104. int timeout;
  1105. int ret;
  1106. unsigned long dma_timeout;
  1107. as = spi_master_get_devdata(master);
  1108. if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
  1109. dev_dbg(&spi->dev, "missing rx or tx buf\n");
  1110. return -EINVAL;
  1111. }
  1112. asd = spi->controller_state;
  1113. bits = (asd->csr >> 4) & 0xf;
  1114. if (bits != xfer->bits_per_word - 8) {
  1115. dev_dbg(&spi->dev,
  1116. "you can't yet change bits_per_word in transfers\n");
  1117. return -ENOPROTOOPT;
  1118. }
  1119. /*
  1120. * DMA map early, for performance (empties dcache ASAP) and
  1121. * better fault reporting.
  1122. */
  1123. if ((!msg->is_dma_mapped)
  1124. && as->use_pdc) {
  1125. if (atmel_spi_dma_map_xfer(as, xfer) < 0)
  1126. return -ENOMEM;
  1127. }
  1128. atmel_spi_set_xfer_speed(as, msg->spi, xfer);
  1129. as->done_status = 0;
  1130. as->current_transfer = xfer;
  1131. as->current_remaining_bytes = xfer->len;
  1132. while (as->current_remaining_bytes) {
  1133. reinit_completion(&as->xfer_completion);
  1134. if (as->use_pdc) {
  1135. atmel_spi_pdc_next_xfer(master, msg, xfer);
  1136. } else if (atmel_spi_use_dma(as, xfer)) {
  1137. len = as->current_remaining_bytes;
  1138. ret = atmel_spi_next_xfer_dma_submit(master,
  1139. xfer, &len);
  1140. if (ret) {
  1141. dev_err(&spi->dev,
  1142. "unable to use DMA, fallback to PIO\n");
  1143. atmel_spi_next_xfer_pio(master, xfer);
  1144. } else {
  1145. as->current_remaining_bytes -= len;
  1146. if (as->current_remaining_bytes < 0)
  1147. as->current_remaining_bytes = 0;
  1148. }
  1149. } else {
  1150. atmel_spi_next_xfer_pio(master, xfer);
  1151. }
  1152. /* interrupts are disabled, so free the lock for schedule */
  1153. atmel_spi_unlock(as);
  1154. dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
  1155. SPI_DMA_TIMEOUT);
  1156. atmel_spi_lock(as);
  1157. if (WARN_ON(dma_timeout == 0)) {
  1158. dev_err(&spi->dev, "spi transfer timeout\n");
  1159. as->done_status = -EIO;
  1160. }
  1161. if (as->done_status)
  1162. break;
  1163. }
  1164. if (as->done_status) {
  1165. if (as->use_pdc) {
  1166. dev_warn(master->dev.parent,
  1167. "overrun (%u/%u remaining)\n",
  1168. spi_readl(as, TCR), spi_readl(as, RCR));
  1169. /*
  1170. * Clean up DMA registers and make sure the data
  1171. * registers are empty.
  1172. */
  1173. spi_writel(as, RNCR, 0);
  1174. spi_writel(as, TNCR, 0);
  1175. spi_writel(as, RCR, 0);
  1176. spi_writel(as, TCR, 0);
  1177. for (timeout = 1000; timeout; timeout--)
  1178. if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
  1179. break;
  1180. if (!timeout)
  1181. dev_warn(master->dev.parent,
  1182. "timeout waiting for TXEMPTY");
  1183. while (spi_readl(as, SR) & SPI_BIT(RDRF))
  1184. spi_readl(as, RDR);
  1185. /* Clear any overrun happening while cleaning up */
  1186. spi_readl(as, SR);
  1187. } else if (atmel_spi_use_dma(as, xfer)) {
  1188. atmel_spi_stop_dma(master);
  1189. }
  1190. if (!msg->is_dma_mapped
  1191. && as->use_pdc)
  1192. atmel_spi_dma_unmap_xfer(master, xfer);
  1193. return 0;
  1194. } else {
  1195. /* only update length if no error */
  1196. msg->actual_length += xfer->len;
  1197. }
  1198. if (!msg->is_dma_mapped
  1199. && as->use_pdc)
  1200. atmel_spi_dma_unmap_xfer(master, xfer);
  1201. spi_transfer_delay_exec(xfer);
  1202. if (xfer->cs_change) {
  1203. if (list_is_last(&xfer->transfer_list,
  1204. &msg->transfers)) {
  1205. as->keep_cs = true;
  1206. } else {
  1207. cs_deactivate(as, msg->spi);
  1208. udelay(10);
  1209. cs_activate(as, msg->spi);
  1210. }
  1211. }
  1212. return 0;
  1213. }
  1214. static int atmel_spi_transfer_one_message(struct spi_master *master,
  1215. struct spi_message *msg)
  1216. {
  1217. struct atmel_spi *as;
  1218. struct spi_transfer *xfer;
  1219. struct spi_device *spi = msg->spi;
  1220. int ret = 0;
  1221. as = spi_master_get_devdata(master);
  1222. dev_dbg(&spi->dev, "new message %p submitted for %s\n",
  1223. msg, dev_name(&spi->dev));
  1224. atmel_spi_lock(as);
  1225. cs_activate(as, spi);
  1226. as->keep_cs = false;
  1227. msg->status = 0;
  1228. msg->actual_length = 0;
  1229. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  1230. trace_spi_transfer_start(msg, xfer);
  1231. ret = atmel_spi_one_transfer(master, msg, xfer);
  1232. if (ret)
  1233. goto msg_done;
  1234. trace_spi_transfer_stop(msg, xfer);
  1235. }
  1236. if (as->use_pdc)
  1237. atmel_spi_disable_pdc_transfer(as);
  1238. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  1239. dev_dbg(&spi->dev,
  1240. " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
  1241. xfer, xfer->len,
  1242. xfer->tx_buf, &xfer->tx_dma,
  1243. xfer->rx_buf, &xfer->rx_dma);
  1244. }
  1245. msg_done:
  1246. if (!as->keep_cs)
  1247. cs_deactivate(as, msg->spi);
  1248. atmel_spi_unlock(as);
  1249. msg->status = as->done_status;
  1250. spi_finalize_current_message(spi->master);
  1251. return ret;
  1252. }
  1253. static void atmel_spi_cleanup(struct spi_device *spi)
  1254. {
  1255. struct atmel_spi_device *asd = spi->controller_state;
  1256. if (!asd)
  1257. return;
  1258. spi->controller_state = NULL;
  1259. kfree(asd);
  1260. }
  1261. static inline unsigned int atmel_get_version(struct atmel_spi *as)
  1262. {
  1263. return spi_readl(as, VERSION) & 0x00000fff;
  1264. }
  1265. static void atmel_get_caps(struct atmel_spi *as)
  1266. {
  1267. unsigned int version;
  1268. version = atmel_get_version(as);
  1269. as->caps.is_spi2 = version > 0x121;
  1270. as->caps.has_wdrbt = version >= 0x210;
  1271. as->caps.has_dma_support = version >= 0x212;
  1272. as->caps.has_pdc_support = version < 0x212;
  1273. }
  1274. static void atmel_spi_init(struct atmel_spi *as)
  1275. {
  1276. spi_writel(as, CR, SPI_BIT(SWRST));
  1277. spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
  1278. /* It is recommended to enable FIFOs first thing after reset */
  1279. if (as->fifo_size)
  1280. spi_writel(as, CR, SPI_BIT(FIFOEN));
  1281. if (as->caps.has_wdrbt) {
  1282. spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
  1283. | SPI_BIT(MSTR));
  1284. } else {
  1285. spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
  1286. }
  1287. if (as->use_pdc)
  1288. spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
  1289. spi_writel(as, CR, SPI_BIT(SPIEN));
  1290. }
  1291. static int atmel_spi_probe(struct platform_device *pdev)
  1292. {
  1293. struct resource *regs;
  1294. int irq;
  1295. struct clk *clk;
  1296. int ret;
  1297. struct spi_master *master;
  1298. struct atmel_spi *as;
  1299. /* Select default pin state */
  1300. pinctrl_pm_select_default_state(&pdev->dev);
  1301. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1302. if (!regs)
  1303. return -ENXIO;
  1304. irq = platform_get_irq(pdev, 0);
  1305. if (irq < 0)
  1306. return irq;
  1307. clk = devm_clk_get(&pdev->dev, "spi_clk");
  1308. if (IS_ERR(clk))
  1309. return PTR_ERR(clk);
  1310. /* setup spi core then atmel-specific driver state */
  1311. master = spi_alloc_master(&pdev->dev, sizeof(*as));
  1312. if (!master)
  1313. return -ENOMEM;
  1314. /* the spi->mode bits understood by this driver: */
  1315. master->use_gpio_descriptors = true;
  1316. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  1317. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
  1318. master->dev.of_node = pdev->dev.of_node;
  1319. master->bus_num = pdev->id;
  1320. master->num_chipselect = 4;
  1321. master->setup = atmel_spi_setup;
  1322. master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
  1323. master->transfer_one_message = atmel_spi_transfer_one_message;
  1324. master->cleanup = atmel_spi_cleanup;
  1325. master->auto_runtime_pm = true;
  1326. master->max_dma_len = SPI_MAX_DMA_XFER;
  1327. master->can_dma = atmel_spi_can_dma;
  1328. platform_set_drvdata(pdev, master);
  1329. as = spi_master_get_devdata(master);
  1330. spin_lock_init(&as->lock);
  1331. as->pdev = pdev;
  1332. as->regs = devm_ioremap_resource(&pdev->dev, regs);
  1333. if (IS_ERR(as->regs)) {
  1334. ret = PTR_ERR(as->regs);
  1335. goto out_unmap_regs;
  1336. }
  1337. as->phybase = regs->start;
  1338. as->irq = irq;
  1339. as->clk = clk;
  1340. init_completion(&as->xfer_completion);
  1341. atmel_get_caps(as);
  1342. as->use_dma = false;
  1343. as->use_pdc = false;
  1344. if (as->caps.has_dma_support) {
  1345. ret = atmel_spi_configure_dma(master, as);
  1346. if (ret == 0) {
  1347. as->use_dma = true;
  1348. } else if (ret == -EPROBE_DEFER) {
  1349. goto out_unmap_regs;
  1350. }
  1351. } else if (as->caps.has_pdc_support) {
  1352. as->use_pdc = true;
  1353. }
  1354. if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
  1355. as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
  1356. SPI_MAX_DMA_XFER,
  1357. &as->dma_addr_rx_bbuf,
  1358. GFP_KERNEL | GFP_DMA);
  1359. if (!as->addr_rx_bbuf) {
  1360. as->use_dma = false;
  1361. } else {
  1362. as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
  1363. SPI_MAX_DMA_XFER,
  1364. &as->dma_addr_tx_bbuf,
  1365. GFP_KERNEL | GFP_DMA);
  1366. if (!as->addr_tx_bbuf) {
  1367. as->use_dma = false;
  1368. dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
  1369. as->addr_rx_bbuf,
  1370. as->dma_addr_rx_bbuf);
  1371. }
  1372. }
  1373. if (!as->use_dma)
  1374. dev_info(master->dev.parent,
  1375. " can not allocate dma coherent memory\n");
  1376. }
  1377. if (as->caps.has_dma_support && !as->use_dma)
  1378. dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
  1379. if (as->use_pdc) {
  1380. ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
  1381. 0, dev_name(&pdev->dev), master);
  1382. } else {
  1383. ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
  1384. 0, dev_name(&pdev->dev), master);
  1385. }
  1386. if (ret)
  1387. goto out_unmap_regs;
  1388. /* Initialize the hardware */
  1389. ret = clk_prepare_enable(clk);
  1390. if (ret)
  1391. goto out_free_irq;
  1392. as->spi_clk = clk_get_rate(clk);
  1393. as->fifo_size = 0;
  1394. if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
  1395. &as->fifo_size)) {
  1396. dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
  1397. }
  1398. atmel_spi_init(as);
  1399. pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
  1400. pm_runtime_use_autosuspend(&pdev->dev);
  1401. pm_runtime_set_active(&pdev->dev);
  1402. pm_runtime_enable(&pdev->dev);
  1403. ret = devm_spi_register_master(&pdev->dev, master);
  1404. if (ret)
  1405. goto out_free_dma;
  1406. /* go! */
  1407. dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
  1408. atmel_get_version(as), (unsigned long)regs->start,
  1409. irq);
  1410. return 0;
  1411. out_free_dma:
  1412. pm_runtime_disable(&pdev->dev);
  1413. pm_runtime_set_suspended(&pdev->dev);
  1414. if (as->use_dma)
  1415. atmel_spi_release_dma(master);
  1416. spi_writel(as, CR, SPI_BIT(SWRST));
  1417. spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
  1418. clk_disable_unprepare(clk);
  1419. out_free_irq:
  1420. out_unmap_regs:
  1421. spi_master_put(master);
  1422. return ret;
  1423. }
  1424. static int atmel_spi_remove(struct platform_device *pdev)
  1425. {
  1426. struct spi_master *master = platform_get_drvdata(pdev);
  1427. struct atmel_spi *as = spi_master_get_devdata(master);
  1428. pm_runtime_get_sync(&pdev->dev);
  1429. /* reset the hardware and block queue progress */
  1430. if (as->use_dma) {
  1431. atmel_spi_stop_dma(master);
  1432. atmel_spi_release_dma(master);
  1433. if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
  1434. dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
  1435. as->addr_tx_bbuf,
  1436. as->dma_addr_tx_bbuf);
  1437. dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
  1438. as->addr_rx_bbuf,
  1439. as->dma_addr_rx_bbuf);
  1440. }
  1441. }
  1442. spin_lock_irq(&as->lock);
  1443. spi_writel(as, CR, SPI_BIT(SWRST));
  1444. spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
  1445. spi_readl(as, SR);
  1446. spin_unlock_irq(&as->lock);
  1447. clk_disable_unprepare(as->clk);
  1448. pm_runtime_put_noidle(&pdev->dev);
  1449. pm_runtime_disable(&pdev->dev);
  1450. return 0;
  1451. }
  1452. #ifdef CONFIG_PM
  1453. static int atmel_spi_runtime_suspend(struct device *dev)
  1454. {
  1455. struct spi_master *master = dev_get_drvdata(dev);
  1456. struct atmel_spi *as = spi_master_get_devdata(master);
  1457. clk_disable_unprepare(as->clk);
  1458. pinctrl_pm_select_sleep_state(dev);
  1459. return 0;
  1460. }
  1461. static int atmel_spi_runtime_resume(struct device *dev)
  1462. {
  1463. struct spi_master *master = dev_get_drvdata(dev);
  1464. struct atmel_spi *as = spi_master_get_devdata(master);
  1465. pinctrl_pm_select_default_state(dev);
  1466. return clk_prepare_enable(as->clk);
  1467. }
  1468. #ifdef CONFIG_PM_SLEEP
  1469. static int atmel_spi_suspend(struct device *dev)
  1470. {
  1471. struct spi_master *master = dev_get_drvdata(dev);
  1472. int ret;
  1473. /* Stop the queue running */
  1474. ret = spi_master_suspend(master);
  1475. if (ret)
  1476. return ret;
  1477. if (!pm_runtime_suspended(dev))
  1478. atmel_spi_runtime_suspend(dev);
  1479. return 0;
  1480. }
  1481. static int atmel_spi_resume(struct device *dev)
  1482. {
  1483. struct spi_master *master = dev_get_drvdata(dev);
  1484. struct atmel_spi *as = spi_master_get_devdata(master);
  1485. int ret;
  1486. ret = clk_prepare_enable(as->clk);
  1487. if (ret)
  1488. return ret;
  1489. atmel_spi_init(as);
  1490. clk_disable_unprepare(as->clk);
  1491. if (!pm_runtime_suspended(dev)) {
  1492. ret = atmel_spi_runtime_resume(dev);
  1493. if (ret)
  1494. return ret;
  1495. }
  1496. /* Start the queue running */
  1497. return spi_master_resume(master);
  1498. }
  1499. #endif
  1500. static const struct dev_pm_ops atmel_spi_pm_ops = {
  1501. SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
  1502. SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
  1503. atmel_spi_runtime_resume, NULL)
  1504. };
  1505. #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
  1506. #else
  1507. #define ATMEL_SPI_PM_OPS NULL
  1508. #endif
  1509. static const struct of_device_id atmel_spi_dt_ids[] = {
  1510. { .compatible = "atmel,at91rm9200-spi" },
  1511. { /* sentinel */ }
  1512. };
  1513. MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
  1514. static struct platform_driver atmel_spi_driver = {
  1515. .driver = {
  1516. .name = "atmel_spi",
  1517. .pm = ATMEL_SPI_PM_OPS,
  1518. .of_match_table = atmel_spi_dt_ids,
  1519. },
  1520. .probe = atmel_spi_probe,
  1521. .remove = atmel_spi_remove,
  1522. };
  1523. module_platform_driver(atmel_spi_driver);
  1524. MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
  1525. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  1526. MODULE_LICENSE("GPL");
  1527. MODULE_ALIAS("platform:atmel_spi");