spi-ath79.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
  4. *
  5. * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  6. *
  7. * This driver has been based on the spi-gpio.c:
  8. * Copyright (C) 2006,2008 David Brownell
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/delay.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/io.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/spi/spi_bitbang.h>
  18. #include <linux/bitops.h>
  19. #include <linux/clk.h>
  20. #include <linux/err.h>
  21. #include <linux/platform_data/spi-ath79.h>
  22. #define DRV_NAME "ath79-spi"
  23. #define ATH79_SPI_RRW_DELAY_FACTOR 12000
  24. #define MHZ (1000 * 1000)
  25. #define AR71XX_SPI_REG_FS 0x00 /* Function Select */
  26. #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
  27. #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
  28. #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
  29. #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
  30. #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
  31. #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
  32. #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
  33. struct ath79_spi {
  34. struct spi_bitbang bitbang;
  35. u32 ioc_base;
  36. u32 reg_ctrl;
  37. void __iomem *base;
  38. struct clk *clk;
  39. unsigned int rrw_delay;
  40. };
  41. static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
  42. {
  43. return ioread32(sp->base + reg);
  44. }
  45. static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
  46. {
  47. iowrite32(val, sp->base + reg);
  48. }
  49. static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
  50. {
  51. return spi_master_get_devdata(spi->master);
  52. }
  53. static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
  54. {
  55. if (nsecs > sp->rrw_delay)
  56. ndelay(nsecs - sp->rrw_delay);
  57. }
  58. static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
  59. {
  60. struct ath79_spi *sp = ath79_spidev_to_sp(spi);
  61. int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
  62. u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
  63. if (cs_high)
  64. sp->ioc_base |= cs_bit;
  65. else
  66. sp->ioc_base &= ~cs_bit;
  67. ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
  68. }
  69. static void ath79_spi_enable(struct ath79_spi *sp)
  70. {
  71. /* enable GPIO mode */
  72. ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
  73. /* save CTRL register */
  74. sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
  75. sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
  76. /* clear clk and mosi in the base state */
  77. sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
  78. /* TODO: setup speed? */
  79. ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
  80. }
  81. static void ath79_spi_disable(struct ath79_spi *sp)
  82. {
  83. /* restore CTRL register */
  84. ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
  85. /* disable GPIO mode */
  86. ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
  87. }
  88. static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
  89. u32 word, u8 bits, unsigned flags)
  90. {
  91. struct ath79_spi *sp = ath79_spidev_to_sp(spi);
  92. u32 ioc = sp->ioc_base;
  93. /* clock starts at inactive polarity */
  94. for (word <<= (32 - bits); likely(bits); bits--) {
  95. u32 out;
  96. if (word & (1 << 31))
  97. out = ioc | AR71XX_SPI_IOC_DO;
  98. else
  99. out = ioc & ~AR71XX_SPI_IOC_DO;
  100. /* setup MSB (to slave) on trailing edge */
  101. ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
  102. ath79_spi_delay(sp, nsecs);
  103. ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
  104. ath79_spi_delay(sp, nsecs);
  105. if (bits == 1)
  106. ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
  107. word <<= 1;
  108. }
  109. return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
  110. }
  111. static int ath79_spi_probe(struct platform_device *pdev)
  112. {
  113. struct spi_master *master;
  114. struct ath79_spi *sp;
  115. struct ath79_spi_platform_data *pdata;
  116. unsigned long rate;
  117. int ret;
  118. master = spi_alloc_master(&pdev->dev, sizeof(*sp));
  119. if (master == NULL) {
  120. dev_err(&pdev->dev, "failed to allocate spi master\n");
  121. return -ENOMEM;
  122. }
  123. sp = spi_master_get_devdata(master);
  124. master->dev.of_node = pdev->dev.of_node;
  125. platform_set_drvdata(pdev, sp);
  126. pdata = dev_get_platdata(&pdev->dev);
  127. master->use_gpio_descriptors = true;
  128. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
  129. master->flags = SPI_MASTER_GPIO_SS;
  130. if (pdata) {
  131. master->bus_num = pdata->bus_num;
  132. master->num_chipselect = pdata->num_chipselect;
  133. }
  134. sp->bitbang.master = master;
  135. sp->bitbang.chipselect = ath79_spi_chipselect;
  136. sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
  137. sp->bitbang.flags = SPI_CS_HIGH;
  138. sp->base = devm_platform_ioremap_resource(pdev, 0);
  139. if (IS_ERR(sp->base)) {
  140. ret = PTR_ERR(sp->base);
  141. goto err_put_master;
  142. }
  143. sp->clk = devm_clk_get(&pdev->dev, "ahb");
  144. if (IS_ERR(sp->clk)) {
  145. ret = PTR_ERR(sp->clk);
  146. goto err_put_master;
  147. }
  148. ret = clk_prepare_enable(sp->clk);
  149. if (ret)
  150. goto err_put_master;
  151. rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
  152. if (!rate) {
  153. ret = -EINVAL;
  154. goto err_clk_disable;
  155. }
  156. sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
  157. dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
  158. sp->rrw_delay);
  159. ath79_spi_enable(sp);
  160. ret = spi_bitbang_start(&sp->bitbang);
  161. if (ret)
  162. goto err_disable;
  163. return 0;
  164. err_disable:
  165. ath79_spi_disable(sp);
  166. err_clk_disable:
  167. clk_disable_unprepare(sp->clk);
  168. err_put_master:
  169. spi_master_put(sp->bitbang.master);
  170. return ret;
  171. }
  172. static int ath79_spi_remove(struct platform_device *pdev)
  173. {
  174. struct ath79_spi *sp = platform_get_drvdata(pdev);
  175. spi_bitbang_stop(&sp->bitbang);
  176. ath79_spi_disable(sp);
  177. clk_disable_unprepare(sp->clk);
  178. spi_master_put(sp->bitbang.master);
  179. return 0;
  180. }
  181. static void ath79_spi_shutdown(struct platform_device *pdev)
  182. {
  183. ath79_spi_remove(pdev);
  184. }
  185. static const struct of_device_id ath79_spi_of_match[] = {
  186. { .compatible = "qca,ar7100-spi", },
  187. { },
  188. };
  189. MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
  190. static struct platform_driver ath79_spi_driver = {
  191. .probe = ath79_spi_probe,
  192. .remove = ath79_spi_remove,
  193. .shutdown = ath79_spi_shutdown,
  194. .driver = {
  195. .name = DRV_NAME,
  196. .of_match_table = ath79_spi_of_match,
  197. },
  198. };
  199. module_platform_driver(ath79_spi_driver);
  200. MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
  201. MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  202. MODULE_LICENSE("GPL v2");
  203. MODULE_ALIAS("platform:" DRV_NAME);