spi-at91-usart.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Driver for AT91 USART Controllers as SPI
  4. //
  5. // Copyright (C) 2018 Microchip Technology Inc.
  6. //
  7. // Author: Radu Pirea <radu.pirea@microchip.com>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/dma-direction.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/of_gpio.h>
  17. #include <linux/pinctrl/consumer.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/spi/spi.h>
  21. #define US_CR 0x00
  22. #define US_MR 0x04
  23. #define US_IER 0x08
  24. #define US_IDR 0x0C
  25. #define US_CSR 0x14
  26. #define US_RHR 0x18
  27. #define US_THR 0x1C
  28. #define US_BRGR 0x20
  29. #define US_VERSION 0xFC
  30. #define US_CR_RSTRX BIT(2)
  31. #define US_CR_RSTTX BIT(3)
  32. #define US_CR_RXEN BIT(4)
  33. #define US_CR_RXDIS BIT(5)
  34. #define US_CR_TXEN BIT(6)
  35. #define US_CR_TXDIS BIT(7)
  36. #define US_MR_SPI_MASTER 0x0E
  37. #define US_MR_CHRL GENMASK(7, 6)
  38. #define US_MR_CPHA BIT(8)
  39. #define US_MR_CPOL BIT(16)
  40. #define US_MR_CLKO BIT(18)
  41. #define US_MR_WRDBT BIT(20)
  42. #define US_MR_LOOP BIT(15)
  43. #define US_IR_RXRDY BIT(0)
  44. #define US_IR_TXRDY BIT(1)
  45. #define US_IR_OVRE BIT(5)
  46. #define US_BRGR_SIZE BIT(16)
  47. #define US_MIN_CLK_DIV 0x06
  48. #define US_MAX_CLK_DIV BIT(16)
  49. #define US_RESET (US_CR_RSTRX | US_CR_RSTTX)
  50. #define US_DISABLE (US_CR_RXDIS | US_CR_TXDIS)
  51. #define US_ENABLE (US_CR_RXEN | US_CR_TXEN)
  52. #define US_OVRE_RXRDY_IRQS (US_IR_OVRE | US_IR_RXRDY)
  53. #define US_INIT \
  54. (US_MR_SPI_MASTER | US_MR_CHRL | US_MR_CLKO | US_MR_WRDBT)
  55. #define US_DMA_MIN_BYTES 16
  56. #define US_DMA_TIMEOUT (msecs_to_jiffies(1000))
  57. /* Register access macros */
  58. #define at91_usart_spi_readl(port, reg) \
  59. readl_relaxed((port)->regs + US_##reg)
  60. #define at91_usart_spi_writel(port, reg, value) \
  61. writel_relaxed((value), (port)->regs + US_##reg)
  62. #define at91_usart_spi_readb(port, reg) \
  63. readb_relaxed((port)->regs + US_##reg)
  64. #define at91_usart_spi_writeb(port, reg, value) \
  65. writeb_relaxed((value), (port)->regs + US_##reg)
  66. struct at91_usart_spi {
  67. struct platform_device *mpdev;
  68. struct spi_transfer *current_transfer;
  69. void __iomem *regs;
  70. struct device *dev;
  71. struct clk *clk;
  72. struct completion xfer_completion;
  73. /*used in interrupt to protect data reading*/
  74. spinlock_t lock;
  75. phys_addr_t phybase;
  76. int irq;
  77. unsigned int current_tx_remaining_bytes;
  78. unsigned int current_rx_remaining_bytes;
  79. u32 spi_clk;
  80. u32 status;
  81. bool xfer_failed;
  82. bool use_dma;
  83. };
  84. static void dma_callback(void *data)
  85. {
  86. struct spi_controller *ctlr = data;
  87. struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
  88. at91_usart_spi_writel(aus, IER, US_IR_RXRDY);
  89. aus->current_rx_remaining_bytes = 0;
  90. complete(&aus->xfer_completion);
  91. }
  92. static bool at91_usart_spi_can_dma(struct spi_controller *ctrl,
  93. struct spi_device *spi,
  94. struct spi_transfer *xfer)
  95. {
  96. struct at91_usart_spi *aus = spi_master_get_devdata(ctrl);
  97. return aus->use_dma && xfer->len >= US_DMA_MIN_BYTES;
  98. }
  99. static int at91_usart_spi_configure_dma(struct spi_controller *ctlr,
  100. struct at91_usart_spi *aus)
  101. {
  102. struct dma_slave_config slave_config;
  103. struct device *dev = &aus->mpdev->dev;
  104. phys_addr_t phybase = aus->phybase;
  105. dma_cap_mask_t mask;
  106. int err = 0;
  107. dma_cap_zero(mask);
  108. dma_cap_set(DMA_SLAVE, mask);
  109. ctlr->dma_tx = dma_request_chan(dev, "tx");
  110. if (IS_ERR_OR_NULL(ctlr->dma_tx)) {
  111. if (IS_ERR(ctlr->dma_tx)) {
  112. err = PTR_ERR(ctlr->dma_tx);
  113. goto at91_usart_spi_error_clear;
  114. }
  115. dev_dbg(dev,
  116. "DMA TX channel not available, SPI unable to use DMA\n");
  117. err = -EBUSY;
  118. goto at91_usart_spi_error_clear;
  119. }
  120. ctlr->dma_rx = dma_request_chan(dev, "rx");
  121. if (IS_ERR_OR_NULL(ctlr->dma_rx)) {
  122. if (IS_ERR(ctlr->dma_rx)) {
  123. err = PTR_ERR(ctlr->dma_rx);
  124. goto at91_usart_spi_error;
  125. }
  126. dev_dbg(dev,
  127. "DMA RX channel not available, SPI unable to use DMA\n");
  128. err = -EBUSY;
  129. goto at91_usart_spi_error;
  130. }
  131. slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  132. slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  133. slave_config.dst_addr = (dma_addr_t)phybase + US_THR;
  134. slave_config.src_addr = (dma_addr_t)phybase + US_RHR;
  135. slave_config.src_maxburst = 1;
  136. slave_config.dst_maxburst = 1;
  137. slave_config.device_fc = false;
  138. slave_config.direction = DMA_DEV_TO_MEM;
  139. if (dmaengine_slave_config(ctlr->dma_rx, &slave_config)) {
  140. dev_err(&ctlr->dev,
  141. "failed to configure rx dma channel\n");
  142. err = -EINVAL;
  143. goto at91_usart_spi_error;
  144. }
  145. slave_config.direction = DMA_MEM_TO_DEV;
  146. if (dmaengine_slave_config(ctlr->dma_tx, &slave_config)) {
  147. dev_err(&ctlr->dev,
  148. "failed to configure tx dma channel\n");
  149. err = -EINVAL;
  150. goto at91_usart_spi_error;
  151. }
  152. aus->use_dma = true;
  153. return 0;
  154. at91_usart_spi_error:
  155. if (!IS_ERR_OR_NULL(ctlr->dma_tx))
  156. dma_release_channel(ctlr->dma_tx);
  157. if (!IS_ERR_OR_NULL(ctlr->dma_rx))
  158. dma_release_channel(ctlr->dma_rx);
  159. ctlr->dma_tx = NULL;
  160. ctlr->dma_rx = NULL;
  161. at91_usart_spi_error_clear:
  162. return err;
  163. }
  164. static void at91_usart_spi_release_dma(struct spi_controller *ctlr)
  165. {
  166. if (ctlr->dma_rx)
  167. dma_release_channel(ctlr->dma_rx);
  168. if (ctlr->dma_tx)
  169. dma_release_channel(ctlr->dma_tx);
  170. }
  171. static void at91_usart_spi_stop_dma(struct spi_controller *ctlr)
  172. {
  173. if (ctlr->dma_rx)
  174. dmaengine_terminate_all(ctlr->dma_rx);
  175. if (ctlr->dma_tx)
  176. dmaengine_terminate_all(ctlr->dma_tx);
  177. }
  178. static int at91_usart_spi_dma_transfer(struct spi_controller *ctlr,
  179. struct spi_transfer *xfer)
  180. {
  181. struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
  182. struct dma_chan *rxchan = ctlr->dma_rx;
  183. struct dma_chan *txchan = ctlr->dma_tx;
  184. struct dma_async_tx_descriptor *rxdesc;
  185. struct dma_async_tx_descriptor *txdesc;
  186. dma_cookie_t cookie;
  187. /* Disable RX interrupt */
  188. at91_usart_spi_writel(aus, IDR, US_IR_RXRDY);
  189. rxdesc = dmaengine_prep_slave_sg(rxchan,
  190. xfer->rx_sg.sgl,
  191. xfer->rx_sg.nents,
  192. DMA_DEV_TO_MEM,
  193. DMA_PREP_INTERRUPT |
  194. DMA_CTRL_ACK);
  195. if (!rxdesc)
  196. goto at91_usart_spi_err_dma;
  197. txdesc = dmaengine_prep_slave_sg(txchan,
  198. xfer->tx_sg.sgl,
  199. xfer->tx_sg.nents,
  200. DMA_MEM_TO_DEV,
  201. DMA_PREP_INTERRUPT |
  202. DMA_CTRL_ACK);
  203. if (!txdesc)
  204. goto at91_usart_spi_err_dma;
  205. rxdesc->callback = dma_callback;
  206. rxdesc->callback_param = ctlr;
  207. cookie = rxdesc->tx_submit(rxdesc);
  208. if (dma_submit_error(cookie))
  209. goto at91_usart_spi_err_dma;
  210. cookie = txdesc->tx_submit(txdesc);
  211. if (dma_submit_error(cookie))
  212. goto at91_usart_spi_err_dma;
  213. rxchan->device->device_issue_pending(rxchan);
  214. txchan->device->device_issue_pending(txchan);
  215. return 0;
  216. at91_usart_spi_err_dma:
  217. /* Enable RX interrupt if something fails and fallback to PIO */
  218. at91_usart_spi_writel(aus, IER, US_IR_RXRDY);
  219. at91_usart_spi_stop_dma(ctlr);
  220. return -ENOMEM;
  221. }
  222. static unsigned long at91_usart_spi_dma_timeout(struct at91_usart_spi *aus)
  223. {
  224. return wait_for_completion_timeout(&aus->xfer_completion,
  225. US_DMA_TIMEOUT);
  226. }
  227. static inline u32 at91_usart_spi_tx_ready(struct at91_usart_spi *aus)
  228. {
  229. return aus->status & US_IR_TXRDY;
  230. }
  231. static inline u32 at91_usart_spi_rx_ready(struct at91_usart_spi *aus)
  232. {
  233. return aus->status & US_IR_RXRDY;
  234. }
  235. static inline u32 at91_usart_spi_check_overrun(struct at91_usart_spi *aus)
  236. {
  237. return aus->status & US_IR_OVRE;
  238. }
  239. static inline u32 at91_usart_spi_read_status(struct at91_usart_spi *aus)
  240. {
  241. aus->status = at91_usart_spi_readl(aus, CSR);
  242. return aus->status;
  243. }
  244. static inline void at91_usart_spi_tx(struct at91_usart_spi *aus)
  245. {
  246. unsigned int len = aus->current_transfer->len;
  247. unsigned int remaining = aus->current_tx_remaining_bytes;
  248. const u8 *tx_buf = aus->current_transfer->tx_buf;
  249. if (!remaining)
  250. return;
  251. if (at91_usart_spi_tx_ready(aus)) {
  252. at91_usart_spi_writeb(aus, THR, tx_buf[len - remaining]);
  253. aus->current_tx_remaining_bytes--;
  254. }
  255. }
  256. static inline void at91_usart_spi_rx(struct at91_usart_spi *aus)
  257. {
  258. int len = aus->current_transfer->len;
  259. int remaining = aus->current_rx_remaining_bytes;
  260. u8 *rx_buf = aus->current_transfer->rx_buf;
  261. if (!remaining)
  262. return;
  263. rx_buf[len - remaining] = at91_usart_spi_readb(aus, RHR);
  264. aus->current_rx_remaining_bytes--;
  265. }
  266. static inline void
  267. at91_usart_spi_set_xfer_speed(struct at91_usart_spi *aus,
  268. struct spi_transfer *xfer)
  269. {
  270. at91_usart_spi_writel(aus, BRGR,
  271. DIV_ROUND_UP(aus->spi_clk, xfer->speed_hz));
  272. }
  273. static irqreturn_t at91_usart_spi_interrupt(int irq, void *dev_id)
  274. {
  275. struct spi_controller *controller = dev_id;
  276. struct at91_usart_spi *aus = spi_master_get_devdata(controller);
  277. spin_lock(&aus->lock);
  278. at91_usart_spi_read_status(aus);
  279. if (at91_usart_spi_check_overrun(aus)) {
  280. aus->xfer_failed = true;
  281. at91_usart_spi_writel(aus, IDR, US_IR_OVRE | US_IR_RXRDY);
  282. spin_unlock(&aus->lock);
  283. return IRQ_HANDLED;
  284. }
  285. if (at91_usart_spi_rx_ready(aus)) {
  286. at91_usart_spi_rx(aus);
  287. spin_unlock(&aus->lock);
  288. return IRQ_HANDLED;
  289. }
  290. spin_unlock(&aus->lock);
  291. return IRQ_NONE;
  292. }
  293. static int at91_usart_spi_setup(struct spi_device *spi)
  294. {
  295. struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller);
  296. u32 *ausd = spi->controller_state;
  297. unsigned int mr = at91_usart_spi_readl(aus, MR);
  298. if (spi->mode & SPI_CPOL)
  299. mr |= US_MR_CPOL;
  300. else
  301. mr &= ~US_MR_CPOL;
  302. if (spi->mode & SPI_CPHA)
  303. mr |= US_MR_CPHA;
  304. else
  305. mr &= ~US_MR_CPHA;
  306. if (spi->mode & SPI_LOOP)
  307. mr |= US_MR_LOOP;
  308. else
  309. mr &= ~US_MR_LOOP;
  310. if (!ausd) {
  311. ausd = kzalloc(sizeof(*ausd), GFP_KERNEL);
  312. if (!ausd)
  313. return -ENOMEM;
  314. spi->controller_state = ausd;
  315. }
  316. *ausd = mr;
  317. dev_dbg(&spi->dev,
  318. "setup: bpw %u mode 0x%x -> mr %d %08x\n",
  319. spi->bits_per_word, spi->mode, spi->chip_select, mr);
  320. return 0;
  321. }
  322. static int at91_usart_spi_transfer_one(struct spi_controller *ctlr,
  323. struct spi_device *spi,
  324. struct spi_transfer *xfer)
  325. {
  326. struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
  327. unsigned long dma_timeout = 0;
  328. int ret = 0;
  329. at91_usart_spi_set_xfer_speed(aus, xfer);
  330. aus->xfer_failed = false;
  331. aus->current_transfer = xfer;
  332. aus->current_tx_remaining_bytes = xfer->len;
  333. aus->current_rx_remaining_bytes = xfer->len;
  334. while ((aus->current_tx_remaining_bytes ||
  335. aus->current_rx_remaining_bytes) && !aus->xfer_failed) {
  336. reinit_completion(&aus->xfer_completion);
  337. if (at91_usart_spi_can_dma(ctlr, spi, xfer) &&
  338. !ret) {
  339. ret = at91_usart_spi_dma_transfer(ctlr, xfer);
  340. if (ret)
  341. continue;
  342. dma_timeout = at91_usart_spi_dma_timeout(aus);
  343. if (WARN_ON(dma_timeout == 0)) {
  344. dev_err(&spi->dev, "DMA transfer timeout\n");
  345. return -EIO;
  346. }
  347. aus->current_tx_remaining_bytes = 0;
  348. } else {
  349. at91_usart_spi_read_status(aus);
  350. at91_usart_spi_tx(aus);
  351. }
  352. cpu_relax();
  353. }
  354. if (aus->xfer_failed) {
  355. dev_err(aus->dev, "Overrun!\n");
  356. return -EIO;
  357. }
  358. return 0;
  359. }
  360. static int at91_usart_spi_prepare_message(struct spi_controller *ctlr,
  361. struct spi_message *message)
  362. {
  363. struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
  364. struct spi_device *spi = message->spi;
  365. u32 *ausd = spi->controller_state;
  366. at91_usart_spi_writel(aus, CR, US_ENABLE);
  367. at91_usart_spi_writel(aus, IER, US_OVRE_RXRDY_IRQS);
  368. at91_usart_spi_writel(aus, MR, *ausd);
  369. return 0;
  370. }
  371. static int at91_usart_spi_unprepare_message(struct spi_controller *ctlr,
  372. struct spi_message *message)
  373. {
  374. struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
  375. at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
  376. at91_usart_spi_writel(aus, IDR, US_OVRE_RXRDY_IRQS);
  377. return 0;
  378. }
  379. static void at91_usart_spi_cleanup(struct spi_device *spi)
  380. {
  381. struct at91_usart_spi_device *ausd = spi->controller_state;
  382. spi->controller_state = NULL;
  383. kfree(ausd);
  384. }
  385. static void at91_usart_spi_init(struct at91_usart_spi *aus)
  386. {
  387. at91_usart_spi_writel(aus, MR, US_INIT);
  388. at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
  389. }
  390. static int at91_usart_gpio_setup(struct platform_device *pdev)
  391. {
  392. struct device_node *np = pdev->dev.parent->of_node;
  393. int i;
  394. int ret;
  395. int nb;
  396. if (!np)
  397. return -EINVAL;
  398. nb = of_gpio_named_count(np, "cs-gpios");
  399. for (i = 0; i < nb; i++) {
  400. int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
  401. if (cs_gpio < 0)
  402. return cs_gpio;
  403. if (gpio_is_valid(cs_gpio)) {
  404. ret = devm_gpio_request_one(&pdev->dev, cs_gpio,
  405. GPIOF_DIR_OUT,
  406. dev_name(&pdev->dev));
  407. if (ret)
  408. return ret;
  409. }
  410. }
  411. return 0;
  412. }
  413. static int at91_usart_spi_probe(struct platform_device *pdev)
  414. {
  415. struct resource *regs;
  416. struct spi_controller *controller;
  417. struct at91_usart_spi *aus;
  418. struct clk *clk;
  419. int irq;
  420. int ret;
  421. regs = platform_get_resource(to_platform_device(pdev->dev.parent),
  422. IORESOURCE_MEM, 0);
  423. if (!regs)
  424. return -EINVAL;
  425. irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
  426. if (irq < 0)
  427. return irq;
  428. clk = devm_clk_get(pdev->dev.parent, "usart");
  429. if (IS_ERR(clk))
  430. return PTR_ERR(clk);
  431. ret = -ENOMEM;
  432. controller = spi_alloc_master(&pdev->dev, sizeof(*aus));
  433. if (!controller)
  434. goto at91_usart_spi_probe_fail;
  435. ret = at91_usart_gpio_setup(pdev);
  436. if (ret)
  437. goto at91_usart_spi_probe_fail;
  438. controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
  439. controller->dev.of_node = pdev->dev.parent->of_node;
  440. controller->bits_per_word_mask = SPI_BPW_MASK(8);
  441. controller->setup = at91_usart_spi_setup;
  442. controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
  443. controller->transfer_one = at91_usart_spi_transfer_one;
  444. controller->prepare_message = at91_usart_spi_prepare_message;
  445. controller->unprepare_message = at91_usart_spi_unprepare_message;
  446. controller->can_dma = at91_usart_spi_can_dma;
  447. controller->cleanup = at91_usart_spi_cleanup;
  448. controller->max_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
  449. US_MIN_CLK_DIV);
  450. controller->min_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
  451. US_MAX_CLK_DIV);
  452. platform_set_drvdata(pdev, controller);
  453. aus = spi_master_get_devdata(controller);
  454. aus->dev = &pdev->dev;
  455. aus->regs = devm_ioremap_resource(&pdev->dev, regs);
  456. if (IS_ERR(aus->regs)) {
  457. ret = PTR_ERR(aus->regs);
  458. goto at91_usart_spi_probe_fail;
  459. }
  460. aus->irq = irq;
  461. aus->clk = clk;
  462. ret = devm_request_irq(&pdev->dev, irq, at91_usart_spi_interrupt, 0,
  463. dev_name(&pdev->dev), controller);
  464. if (ret)
  465. goto at91_usart_spi_probe_fail;
  466. ret = clk_prepare_enable(clk);
  467. if (ret)
  468. goto at91_usart_spi_probe_fail;
  469. aus->spi_clk = clk_get_rate(clk);
  470. at91_usart_spi_init(aus);
  471. aus->phybase = regs->start;
  472. aus->mpdev = to_platform_device(pdev->dev.parent);
  473. ret = at91_usart_spi_configure_dma(controller, aus);
  474. if (ret)
  475. goto at91_usart_fail_dma;
  476. spin_lock_init(&aus->lock);
  477. init_completion(&aus->xfer_completion);
  478. ret = devm_spi_register_master(&pdev->dev, controller);
  479. if (ret)
  480. goto at91_usart_fail_register_master;
  481. dev_info(&pdev->dev,
  482. "AT91 USART SPI Controller version 0x%x at %pa (irq %d)\n",
  483. at91_usart_spi_readl(aus, VERSION),
  484. &regs->start, irq);
  485. return 0;
  486. at91_usart_fail_register_master:
  487. at91_usart_spi_release_dma(controller);
  488. at91_usart_fail_dma:
  489. clk_disable_unprepare(clk);
  490. at91_usart_spi_probe_fail:
  491. spi_master_put(controller);
  492. return ret;
  493. }
  494. __maybe_unused static int at91_usart_spi_runtime_suspend(struct device *dev)
  495. {
  496. struct spi_controller *ctlr = dev_get_drvdata(dev);
  497. struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
  498. clk_disable_unprepare(aus->clk);
  499. pinctrl_pm_select_sleep_state(dev);
  500. return 0;
  501. }
  502. __maybe_unused static int at91_usart_spi_runtime_resume(struct device *dev)
  503. {
  504. struct spi_controller *ctrl = dev_get_drvdata(dev);
  505. struct at91_usart_spi *aus = spi_master_get_devdata(ctrl);
  506. pinctrl_pm_select_default_state(dev);
  507. return clk_prepare_enable(aus->clk);
  508. }
  509. __maybe_unused static int at91_usart_spi_suspend(struct device *dev)
  510. {
  511. struct spi_controller *ctrl = dev_get_drvdata(dev);
  512. int ret;
  513. ret = spi_controller_suspend(ctrl);
  514. if (ret)
  515. return ret;
  516. if (!pm_runtime_suspended(dev))
  517. at91_usart_spi_runtime_suspend(dev);
  518. return 0;
  519. }
  520. __maybe_unused static int at91_usart_spi_resume(struct device *dev)
  521. {
  522. struct spi_controller *ctrl = dev_get_drvdata(dev);
  523. struct at91_usart_spi *aus = spi_master_get_devdata(ctrl);
  524. int ret;
  525. if (!pm_runtime_suspended(dev)) {
  526. ret = at91_usart_spi_runtime_resume(dev);
  527. if (ret)
  528. return ret;
  529. }
  530. at91_usart_spi_init(aus);
  531. return spi_controller_resume(ctrl);
  532. }
  533. static int at91_usart_spi_remove(struct platform_device *pdev)
  534. {
  535. struct spi_controller *ctlr = platform_get_drvdata(pdev);
  536. struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
  537. at91_usart_spi_release_dma(ctlr);
  538. clk_disable_unprepare(aus->clk);
  539. return 0;
  540. }
  541. static const struct dev_pm_ops at91_usart_spi_pm_ops = {
  542. SET_SYSTEM_SLEEP_PM_OPS(at91_usart_spi_suspend, at91_usart_spi_resume)
  543. SET_RUNTIME_PM_OPS(at91_usart_spi_runtime_suspend,
  544. at91_usart_spi_runtime_resume, NULL)
  545. };
  546. static struct platform_driver at91_usart_spi_driver = {
  547. .driver = {
  548. .name = "at91_usart_spi",
  549. .pm = &at91_usart_spi_pm_ops,
  550. },
  551. .probe = at91_usart_spi_probe,
  552. .remove = at91_usart_spi_remove,
  553. };
  554. module_platform_driver(at91_usart_spi_driver);
  555. MODULE_DESCRIPTION("Microchip AT91 USART SPI Controller driver");
  556. MODULE_AUTHOR("Radu Pirea <radu.pirea@microchip.com>");
  557. MODULE_LICENSE("GPL v2");
  558. MODULE_ALIAS("platform:at91_usart_spi");