spi-ar934x.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
  4. //
  5. // Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
  6. //
  7. // Based on spi-mt7621.c:
  8. // Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  9. // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  10. // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
  11. #include <linux/clk.h>
  12. #include <linux/io.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/of_device.h>
  17. #include <linux/spi/spi.h>
  18. #define DRIVER_NAME "spi-ar934x"
  19. #define AR934X_SPI_REG_FS 0x00
  20. #define AR934X_SPI_ENABLE BIT(0)
  21. #define AR934X_SPI_REG_IOC 0x08
  22. #define AR934X_SPI_IOC_INITVAL 0x70000
  23. #define AR934X_SPI_REG_CTRL 0x04
  24. #define AR934X_SPI_CLK_MASK GENMASK(5, 0)
  25. #define AR934X_SPI_DATAOUT 0x10
  26. #define AR934X_SPI_REG_SHIFT_CTRL 0x14
  27. #define AR934X_SPI_SHIFT_EN BIT(31)
  28. #define AR934X_SPI_SHIFT_CS(n) BIT(28 + (n))
  29. #define AR934X_SPI_SHIFT_TERM 26
  30. #define AR934X_SPI_SHIFT_VAL(cs, term, count) \
  31. (AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) | \
  32. (term) << AR934X_SPI_SHIFT_TERM | (count))
  33. #define AR934X_SPI_DATAIN 0x18
  34. struct ar934x_spi {
  35. struct spi_controller *ctlr;
  36. void __iomem *base;
  37. struct clk *clk;
  38. unsigned int clk_freq;
  39. };
  40. static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
  41. {
  42. int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
  43. if (div < 0)
  44. return 0;
  45. else if (div > AR934X_SPI_CLK_MASK)
  46. return -EINVAL;
  47. else
  48. return div;
  49. }
  50. static int ar934x_spi_setup(struct spi_device *spi)
  51. {
  52. struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
  53. if ((spi->max_speed_hz == 0) ||
  54. (spi->max_speed_hz > (sp->clk_freq / 2))) {
  55. spi->max_speed_hz = sp->clk_freq / 2;
  56. } else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
  57. dev_err(&spi->dev, "spi clock is too low\n");
  58. return -EINVAL;
  59. }
  60. return 0;
  61. }
  62. static int ar934x_spi_transfer_one_message(struct spi_controller *master,
  63. struct spi_message *m)
  64. {
  65. struct ar934x_spi *sp = spi_controller_get_devdata(master);
  66. struct spi_transfer *t = NULL;
  67. struct spi_device *spi = m->spi;
  68. unsigned long trx_done, trx_cur;
  69. int stat = 0;
  70. u8 term = 0;
  71. int div, i;
  72. u32 reg;
  73. const u8 *tx_buf;
  74. u8 *buf;
  75. m->actual_length = 0;
  76. list_for_each_entry(t, &m->transfers, transfer_list) {
  77. if (t->speed_hz)
  78. div = ar934x_spi_clk_div(sp, t->speed_hz);
  79. else
  80. div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
  81. if (div < 0) {
  82. stat = -EIO;
  83. goto msg_done;
  84. }
  85. reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
  86. reg &= ~AR934X_SPI_CLK_MASK;
  87. reg |= div;
  88. iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
  89. iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
  90. for (trx_done = 0; trx_done < t->len; trx_done += 4) {
  91. trx_cur = t->len - trx_done;
  92. if (trx_cur > 4)
  93. trx_cur = 4;
  94. else if (list_is_last(&t->transfer_list, &m->transfers))
  95. term = 1;
  96. if (t->tx_buf) {
  97. tx_buf = t->tx_buf + trx_done;
  98. reg = tx_buf[0];
  99. for (i = 1; i < trx_cur; i++)
  100. reg = reg << 8 | tx_buf[i];
  101. iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
  102. }
  103. reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
  104. trx_cur * 8);
  105. iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
  106. stat = readl_poll_timeout(
  107. sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
  108. !(reg & AR934X_SPI_SHIFT_EN), 0, 5);
  109. if (stat < 0)
  110. goto msg_done;
  111. if (t->rx_buf) {
  112. reg = ioread32(sp->base + AR934X_SPI_DATAIN);
  113. buf = t->rx_buf + trx_done;
  114. for (i = 0; i < trx_cur; i++) {
  115. buf[trx_cur - i - 1] = reg & 0xff;
  116. reg >>= 8;
  117. }
  118. }
  119. }
  120. m->actual_length += t->len;
  121. }
  122. msg_done:
  123. m->status = stat;
  124. spi_finalize_current_message(master);
  125. return 0;
  126. }
  127. static const struct of_device_id ar934x_spi_match[] = {
  128. { .compatible = "qca,ar934x-spi" },
  129. {},
  130. };
  131. MODULE_DEVICE_TABLE(of, ar934x_spi_match);
  132. static int ar934x_spi_probe(struct platform_device *pdev)
  133. {
  134. struct spi_controller *ctlr;
  135. struct ar934x_spi *sp;
  136. void __iomem *base;
  137. struct clk *clk;
  138. int ret;
  139. base = devm_platform_ioremap_resource(pdev, 0);
  140. if (IS_ERR(base))
  141. return PTR_ERR(base);
  142. clk = devm_clk_get(&pdev->dev, NULL);
  143. if (IS_ERR(clk)) {
  144. dev_err(&pdev->dev, "failed to get clock\n");
  145. return PTR_ERR(clk);
  146. }
  147. ret = clk_prepare_enable(clk);
  148. if (ret)
  149. return ret;
  150. ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
  151. if (!ctlr) {
  152. dev_info(&pdev->dev, "failed to allocate spi controller\n");
  153. ret = -ENOMEM;
  154. goto err_clk_disable;
  155. }
  156. /* disable flash mapping and expose spi controller registers */
  157. iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
  158. /* restore pins to default state: CSn=1 DO=CLK=0 */
  159. iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
  160. ctlr->mode_bits = SPI_LSB_FIRST;
  161. ctlr->setup = ar934x_spi_setup;
  162. ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
  163. ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
  164. ctlr->dev.of_node = pdev->dev.of_node;
  165. ctlr->num_chipselect = 3;
  166. dev_set_drvdata(&pdev->dev, ctlr);
  167. sp = spi_controller_get_devdata(ctlr);
  168. sp->base = base;
  169. sp->clk = clk;
  170. sp->clk_freq = clk_get_rate(clk);
  171. sp->ctlr = ctlr;
  172. ret = spi_register_controller(ctlr);
  173. if (!ret)
  174. return 0;
  175. err_clk_disable:
  176. clk_disable_unprepare(clk);
  177. return ret;
  178. }
  179. static int ar934x_spi_remove(struct platform_device *pdev)
  180. {
  181. struct spi_controller *ctlr;
  182. struct ar934x_spi *sp;
  183. ctlr = dev_get_drvdata(&pdev->dev);
  184. sp = spi_controller_get_devdata(ctlr);
  185. spi_unregister_controller(ctlr);
  186. clk_disable_unprepare(sp->clk);
  187. return 0;
  188. }
  189. static struct platform_driver ar934x_spi_driver = {
  190. .driver = {
  191. .name = DRIVER_NAME,
  192. .of_match_table = ar934x_spi_match,
  193. },
  194. .probe = ar934x_spi_probe,
  195. .remove = ar934x_spi_remove,
  196. };
  197. module_platform_driver(ar934x_spi_driver);
  198. MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
  199. MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
  200. MODULE_LICENSE("GPL v2");
  201. MODULE_ALIAS("platform:" DRIVER_NAME);