atmel-quadspi.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Atmel QSPI Controller
  4. *
  5. * Copyright (C) 2015 Atmel Corporation
  6. * Copyright (C) 2018 Cryptera A/S
  7. *
  8. * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
  9. * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
  10. *
  11. * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/spi/spi-mem.h>
  24. /* QSPI register offsets */
  25. #define QSPI_CR 0x0000 /* Control Register */
  26. #define QSPI_MR 0x0004 /* Mode Register */
  27. #define QSPI_RD 0x0008 /* Receive Data Register */
  28. #define QSPI_TD 0x000c /* Transmit Data Register */
  29. #define QSPI_SR 0x0010 /* Status Register */
  30. #define QSPI_IER 0x0014 /* Interrupt Enable Register */
  31. #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
  32. #define QSPI_IMR 0x001c /* Interrupt Mask Register */
  33. #define QSPI_SCR 0x0020 /* Serial Clock Register */
  34. #define QSPI_IAR 0x0030 /* Instruction Address Register */
  35. #define QSPI_ICR 0x0034 /* Instruction Code Register */
  36. #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
  37. #define QSPI_IFR 0x0038 /* Instruction Frame Register */
  38. #define QSPI_RICR 0x003C /* Read Instruction Code Register */
  39. #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
  40. #define QSPI_SKR 0x0044 /* Scrambling Key Register */
  41. #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
  42. #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
  43. #define QSPI_VERSION 0x00FC /* Version Register */
  44. /* Bitfields in QSPI_CR (Control Register) */
  45. #define QSPI_CR_QSPIEN BIT(0)
  46. #define QSPI_CR_QSPIDIS BIT(1)
  47. #define QSPI_CR_SWRST BIT(7)
  48. #define QSPI_CR_LASTXFER BIT(24)
  49. /* Bitfields in QSPI_MR (Mode Register) */
  50. #define QSPI_MR_SMM BIT(0)
  51. #define QSPI_MR_LLB BIT(1)
  52. #define QSPI_MR_WDRBT BIT(2)
  53. #define QSPI_MR_SMRM BIT(3)
  54. #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
  55. #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
  56. #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
  57. #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
  58. #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
  59. #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
  60. #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
  61. #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
  62. #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
  63. #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
  64. /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
  65. #define QSPI_SR_RDRF BIT(0)
  66. #define QSPI_SR_TDRE BIT(1)
  67. #define QSPI_SR_TXEMPTY BIT(2)
  68. #define QSPI_SR_OVRES BIT(3)
  69. #define QSPI_SR_CSR BIT(8)
  70. #define QSPI_SR_CSS BIT(9)
  71. #define QSPI_SR_INSTRE BIT(10)
  72. #define QSPI_SR_QSPIENS BIT(24)
  73. #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
  74. /* Bitfields in QSPI_SCR (Serial Clock Register) */
  75. #define QSPI_SCR_CPOL BIT(0)
  76. #define QSPI_SCR_CPHA BIT(1)
  77. #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
  78. #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
  79. #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
  80. #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
  81. /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
  82. #define QSPI_ICR_INST_MASK GENMASK(7, 0)
  83. #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
  84. #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
  85. #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
  86. /* Bitfields in QSPI_IFR (Instruction Frame Register) */
  87. #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
  88. #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
  89. #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
  90. #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
  91. #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
  92. #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
  93. #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
  94. #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
  95. #define QSPI_IFR_INSTEN BIT(4)
  96. #define QSPI_IFR_ADDREN BIT(5)
  97. #define QSPI_IFR_OPTEN BIT(6)
  98. #define QSPI_IFR_DATAEN BIT(7)
  99. #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
  100. #define QSPI_IFR_OPTL_1BIT (0 << 8)
  101. #define QSPI_IFR_OPTL_2BIT (1 << 8)
  102. #define QSPI_IFR_OPTL_4BIT (2 << 8)
  103. #define QSPI_IFR_OPTL_8BIT (3 << 8)
  104. #define QSPI_IFR_ADDRL BIT(10)
  105. #define QSPI_IFR_TFRTYP_MEM BIT(12)
  106. #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
  107. #define QSPI_IFR_CRM BIT(14)
  108. #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
  109. #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
  110. #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
  111. /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
  112. #define QSPI_SMR_SCREN BIT(0)
  113. #define QSPI_SMR_RVDIS BIT(1)
  114. /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
  115. #define QSPI_WPMR_WPEN BIT(0)
  116. #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
  117. #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
  118. /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
  119. #define QSPI_WPSR_WPVS BIT(0)
  120. #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
  121. #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
  122. struct atmel_qspi_caps {
  123. bool has_qspick;
  124. bool has_ricr;
  125. };
  126. struct atmel_qspi {
  127. void __iomem *regs;
  128. void __iomem *mem;
  129. struct clk *pclk;
  130. struct clk *qspick;
  131. struct platform_device *pdev;
  132. const struct atmel_qspi_caps *caps;
  133. resource_size_t mmap_size;
  134. u32 pending;
  135. u32 mr;
  136. u32 scr;
  137. struct completion cmd_completion;
  138. };
  139. struct atmel_qspi_mode {
  140. u8 cmd_buswidth;
  141. u8 addr_buswidth;
  142. u8 data_buswidth;
  143. u32 config;
  144. };
  145. static const struct atmel_qspi_mode atmel_qspi_modes[] = {
  146. { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
  147. { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
  148. { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
  149. { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
  150. { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
  151. { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
  152. { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
  153. };
  154. #ifdef VERBOSE_DEBUG
  155. static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
  156. {
  157. switch (offset) {
  158. case QSPI_CR:
  159. return "CR";
  160. case QSPI_MR:
  161. return "MR";
  162. case QSPI_RD:
  163. return "MR";
  164. case QSPI_TD:
  165. return "TD";
  166. case QSPI_SR:
  167. return "SR";
  168. case QSPI_IER:
  169. return "IER";
  170. case QSPI_IDR:
  171. return "IDR";
  172. case QSPI_IMR:
  173. return "IMR";
  174. case QSPI_SCR:
  175. return "SCR";
  176. case QSPI_IAR:
  177. return "IAR";
  178. case QSPI_ICR:
  179. return "ICR/WICR";
  180. case QSPI_IFR:
  181. return "IFR";
  182. case QSPI_RICR:
  183. return "RICR";
  184. case QSPI_SMR:
  185. return "SMR";
  186. case QSPI_SKR:
  187. return "SKR";
  188. case QSPI_WPMR:
  189. return "WPMR";
  190. case QSPI_WPSR:
  191. return "WPSR";
  192. case QSPI_VERSION:
  193. return "VERSION";
  194. default:
  195. snprintf(tmp, sz, "0x%02x", offset);
  196. break;
  197. }
  198. return tmp;
  199. }
  200. #endif /* VERBOSE_DEBUG */
  201. static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
  202. {
  203. u32 value = readl_relaxed(aq->regs + offset);
  204. #ifdef VERBOSE_DEBUG
  205. char tmp[8];
  206. dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,
  207. atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
  208. #endif /* VERBOSE_DEBUG */
  209. return value;
  210. }
  211. static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
  212. {
  213. #ifdef VERBOSE_DEBUG
  214. char tmp[8];
  215. dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,
  216. atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
  217. #endif /* VERBOSE_DEBUG */
  218. writel_relaxed(value, aq->regs + offset);
  219. }
  220. static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
  221. const struct atmel_qspi_mode *mode)
  222. {
  223. if (op->cmd.buswidth != mode->cmd_buswidth)
  224. return false;
  225. if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
  226. return false;
  227. if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
  228. return false;
  229. return true;
  230. }
  231. static int atmel_qspi_find_mode(const struct spi_mem_op *op)
  232. {
  233. u32 i;
  234. for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
  235. if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
  236. return i;
  237. return -ENOTSUPP;
  238. }
  239. static bool atmel_qspi_supports_op(struct spi_mem *mem,
  240. const struct spi_mem_op *op)
  241. {
  242. if (!spi_mem_default_supports_op(mem, op))
  243. return false;
  244. if (atmel_qspi_find_mode(op) < 0)
  245. return false;
  246. /* special case not supported by hardware */
  247. if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
  248. op->dummy.nbytes == 0)
  249. return false;
  250. /* DTR ops not supported. */
  251. if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
  252. return false;
  253. if (op->cmd.nbytes != 1)
  254. return false;
  255. return true;
  256. }
  257. static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
  258. const struct spi_mem_op *op, u32 *offset)
  259. {
  260. u32 iar, icr, ifr;
  261. u32 dummy_cycles = 0;
  262. int mode;
  263. iar = 0;
  264. icr = QSPI_ICR_INST(op->cmd.opcode);
  265. ifr = QSPI_IFR_INSTEN;
  266. mode = atmel_qspi_find_mode(op);
  267. if (mode < 0)
  268. return mode;
  269. ifr |= atmel_qspi_modes[mode].config;
  270. if (op->dummy.buswidth && op->dummy.nbytes)
  271. dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
  272. /*
  273. * The controller allows 24 and 32-bit addressing while NAND-flash
  274. * requires 16-bit long. Handling 8-bit long addresses is done using
  275. * the option field. For the 16-bit addresses, the workaround depends
  276. * of the number of requested dummy bits. If there are 8 or more dummy
  277. * cycles, the address is shifted and sent with the first dummy byte.
  278. * Otherwise opcode is disabled and the first byte of the address
  279. * contains the command opcode (works only if the opcode and address
  280. * use the same buswidth). The limitation is when the 16-bit address is
  281. * used without enough dummy cycles and the opcode is using a different
  282. * buswidth than the address.
  283. */
  284. if (op->addr.buswidth) {
  285. switch (op->addr.nbytes) {
  286. case 0:
  287. break;
  288. case 1:
  289. ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
  290. icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
  291. break;
  292. case 2:
  293. if (dummy_cycles < 8 / op->addr.buswidth) {
  294. ifr &= ~QSPI_IFR_INSTEN;
  295. ifr |= QSPI_IFR_ADDREN;
  296. iar = (op->cmd.opcode << 16) |
  297. (op->addr.val & 0xffff);
  298. } else {
  299. ifr |= QSPI_IFR_ADDREN;
  300. iar = (op->addr.val << 8) & 0xffffff;
  301. dummy_cycles -= 8 / op->addr.buswidth;
  302. }
  303. break;
  304. case 3:
  305. ifr |= QSPI_IFR_ADDREN;
  306. iar = op->addr.val & 0xffffff;
  307. break;
  308. case 4:
  309. ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
  310. iar = op->addr.val & 0x7ffffff;
  311. break;
  312. default:
  313. return -ENOTSUPP;
  314. }
  315. }
  316. /* offset of the data access in the QSPI memory space */
  317. *offset = iar;
  318. /* Set number of dummy cycles */
  319. if (dummy_cycles)
  320. ifr |= QSPI_IFR_NBDUM(dummy_cycles);
  321. /* Set data enable and data transfer type. */
  322. if (op->data.nbytes) {
  323. ifr |= QSPI_IFR_DATAEN;
  324. if (op->addr.nbytes)
  325. ifr |= QSPI_IFR_TFRTYP_MEM;
  326. }
  327. /*
  328. * If the QSPI controller is set in regular SPI mode, set it in
  329. * Serial Memory Mode (SMM).
  330. */
  331. if (aq->mr != QSPI_MR_SMM) {
  332. atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
  333. aq->mr = QSPI_MR_SMM;
  334. }
  335. /* Clear pending interrupts */
  336. (void)atmel_qspi_read(aq, QSPI_SR);
  337. if (aq->caps->has_ricr) {
  338. if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  339. ifr |= QSPI_IFR_APBTFRTYP_READ;
  340. /* Set QSPI Instruction Frame registers */
  341. atmel_qspi_write(iar, aq, QSPI_IAR);
  342. if (op->data.dir == SPI_MEM_DATA_IN)
  343. atmel_qspi_write(icr, aq, QSPI_RICR);
  344. else
  345. atmel_qspi_write(icr, aq, QSPI_WICR);
  346. atmel_qspi_write(ifr, aq, QSPI_IFR);
  347. } else {
  348. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  349. ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
  350. /* Set QSPI Instruction Frame registers */
  351. atmel_qspi_write(iar, aq, QSPI_IAR);
  352. atmel_qspi_write(icr, aq, QSPI_ICR);
  353. atmel_qspi_write(ifr, aq, QSPI_IFR);
  354. }
  355. return 0;
  356. }
  357. static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
  358. {
  359. struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
  360. u32 sr, offset;
  361. int err;
  362. /*
  363. * Check if the address exceeds the MMIO window size. An improvement
  364. * would be to add support for regular SPI mode and fall back to it
  365. * when the flash memories overrun the controller's memory space.
  366. */
  367. if (op->addr.val + op->data.nbytes > aq->mmap_size)
  368. return -ENOTSUPP;
  369. err = atmel_qspi_set_cfg(aq, op, &offset);
  370. if (err)
  371. return err;
  372. /* Skip to the final steps if there is no data */
  373. if (op->data.nbytes) {
  374. /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
  375. (void)atmel_qspi_read(aq, QSPI_IFR);
  376. /* Send/Receive data */
  377. if (op->data.dir == SPI_MEM_DATA_IN)
  378. memcpy_fromio(op->data.buf.in, aq->mem + offset,
  379. op->data.nbytes);
  380. else
  381. memcpy_toio(aq->mem + offset, op->data.buf.out,
  382. op->data.nbytes);
  383. /* Release the chip-select */
  384. atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
  385. }
  386. /* Poll INSTRuction End status */
  387. sr = atmel_qspi_read(aq, QSPI_SR);
  388. if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
  389. return err;
  390. /* Wait for INSTRuction End interrupt */
  391. reinit_completion(&aq->cmd_completion);
  392. aq->pending = sr & QSPI_SR_CMD_COMPLETED;
  393. atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER);
  394. if (!wait_for_completion_timeout(&aq->cmd_completion,
  395. msecs_to_jiffies(1000)))
  396. err = -ETIMEDOUT;
  397. atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR);
  398. return err;
  399. }
  400. static const char *atmel_qspi_get_name(struct spi_mem *spimem)
  401. {
  402. return dev_name(spimem->spi->dev.parent);
  403. }
  404. static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
  405. .supports_op = atmel_qspi_supports_op,
  406. .exec_op = atmel_qspi_exec_op,
  407. .get_name = atmel_qspi_get_name
  408. };
  409. static int atmel_qspi_setup(struct spi_device *spi)
  410. {
  411. struct spi_controller *ctrl = spi->master;
  412. struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
  413. unsigned long src_rate;
  414. u32 scbr;
  415. if (ctrl->busy)
  416. return -EBUSY;
  417. if (!spi->max_speed_hz)
  418. return -EINVAL;
  419. src_rate = clk_get_rate(aq->pclk);
  420. if (!src_rate)
  421. return -EINVAL;
  422. /* Compute the QSPI baudrate */
  423. scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
  424. if (scbr > 0)
  425. scbr--;
  426. aq->scr = QSPI_SCR_SCBR(scbr);
  427. atmel_qspi_write(aq->scr, aq, QSPI_SCR);
  428. return 0;
  429. }
  430. static void atmel_qspi_init(struct atmel_qspi *aq)
  431. {
  432. /* Reset the QSPI controller */
  433. atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
  434. /* Set the QSPI controller by default in Serial Memory Mode */
  435. atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
  436. aq->mr = QSPI_MR_SMM;
  437. /* Enable the QSPI controller */
  438. atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
  439. }
  440. static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
  441. {
  442. struct atmel_qspi *aq = dev_id;
  443. u32 status, mask, pending;
  444. status = atmel_qspi_read(aq, QSPI_SR);
  445. mask = atmel_qspi_read(aq, QSPI_IMR);
  446. pending = status & mask;
  447. if (!pending)
  448. return IRQ_NONE;
  449. aq->pending |= pending;
  450. if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
  451. complete(&aq->cmd_completion);
  452. return IRQ_HANDLED;
  453. }
  454. static int atmel_qspi_probe(struct platform_device *pdev)
  455. {
  456. struct spi_controller *ctrl;
  457. struct atmel_qspi *aq;
  458. struct resource *res;
  459. int irq, err = 0;
  460. ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*aq));
  461. if (!ctrl)
  462. return -ENOMEM;
  463. ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
  464. ctrl->setup = atmel_qspi_setup;
  465. ctrl->bus_num = -1;
  466. ctrl->mem_ops = &atmel_qspi_mem_ops;
  467. ctrl->num_chipselect = 1;
  468. ctrl->dev.of_node = pdev->dev.of_node;
  469. platform_set_drvdata(pdev, ctrl);
  470. aq = spi_controller_get_devdata(ctrl);
  471. init_completion(&aq->cmd_completion);
  472. aq->pdev = pdev;
  473. /* Map the registers */
  474. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
  475. aq->regs = devm_ioremap_resource(&pdev->dev, res);
  476. if (IS_ERR(aq->regs)) {
  477. dev_err(&pdev->dev, "missing registers\n");
  478. return PTR_ERR(aq->regs);
  479. }
  480. /* Map the AHB memory */
  481. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
  482. aq->mem = devm_ioremap_resource(&pdev->dev, res);
  483. if (IS_ERR(aq->mem)) {
  484. dev_err(&pdev->dev, "missing AHB memory\n");
  485. return PTR_ERR(aq->mem);
  486. }
  487. aq->mmap_size = resource_size(res);
  488. /* Get the peripheral clock */
  489. aq->pclk = devm_clk_get(&pdev->dev, "pclk");
  490. if (IS_ERR(aq->pclk))
  491. aq->pclk = devm_clk_get(&pdev->dev, NULL);
  492. if (IS_ERR(aq->pclk)) {
  493. dev_err(&pdev->dev, "missing peripheral clock\n");
  494. return PTR_ERR(aq->pclk);
  495. }
  496. /* Enable the peripheral clock */
  497. err = clk_prepare_enable(aq->pclk);
  498. if (err) {
  499. dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
  500. return err;
  501. }
  502. aq->caps = of_device_get_match_data(&pdev->dev);
  503. if (!aq->caps) {
  504. dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
  505. err = -EINVAL;
  506. goto disable_pclk;
  507. }
  508. if (aq->caps->has_qspick) {
  509. /* Get the QSPI system clock */
  510. aq->qspick = devm_clk_get(&pdev->dev, "qspick");
  511. if (IS_ERR(aq->qspick)) {
  512. dev_err(&pdev->dev, "missing system clock\n");
  513. err = PTR_ERR(aq->qspick);
  514. goto disable_pclk;
  515. }
  516. /* Enable the QSPI system clock */
  517. err = clk_prepare_enable(aq->qspick);
  518. if (err) {
  519. dev_err(&pdev->dev,
  520. "failed to enable the QSPI system clock\n");
  521. goto disable_pclk;
  522. }
  523. }
  524. /* Request the IRQ */
  525. irq = platform_get_irq(pdev, 0);
  526. if (irq < 0) {
  527. err = irq;
  528. goto disable_qspick;
  529. }
  530. err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
  531. 0, dev_name(&pdev->dev), aq);
  532. if (err)
  533. goto disable_qspick;
  534. atmel_qspi_init(aq);
  535. err = spi_register_controller(ctrl);
  536. if (err)
  537. goto disable_qspick;
  538. return 0;
  539. disable_qspick:
  540. clk_disable_unprepare(aq->qspick);
  541. disable_pclk:
  542. clk_disable_unprepare(aq->pclk);
  543. return err;
  544. }
  545. static int atmel_qspi_remove(struct platform_device *pdev)
  546. {
  547. struct spi_controller *ctrl = platform_get_drvdata(pdev);
  548. struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
  549. spi_unregister_controller(ctrl);
  550. atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
  551. clk_disable_unprepare(aq->qspick);
  552. clk_disable_unprepare(aq->pclk);
  553. return 0;
  554. }
  555. static int __maybe_unused atmel_qspi_suspend(struct device *dev)
  556. {
  557. struct spi_controller *ctrl = dev_get_drvdata(dev);
  558. struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
  559. clk_disable_unprepare(aq->qspick);
  560. clk_disable_unprepare(aq->pclk);
  561. return 0;
  562. }
  563. static int __maybe_unused atmel_qspi_resume(struct device *dev)
  564. {
  565. struct spi_controller *ctrl = dev_get_drvdata(dev);
  566. struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
  567. clk_prepare_enable(aq->pclk);
  568. clk_prepare_enable(aq->qspick);
  569. atmel_qspi_init(aq);
  570. atmel_qspi_write(aq->scr, aq, QSPI_SCR);
  571. return 0;
  572. }
  573. static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
  574. atmel_qspi_resume);
  575. static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
  576. static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
  577. .has_qspick = true,
  578. .has_ricr = true,
  579. };
  580. static const struct of_device_id atmel_qspi_dt_ids[] = {
  581. {
  582. .compatible = "atmel,sama5d2-qspi",
  583. .data = &atmel_sama5d2_qspi_caps,
  584. },
  585. {
  586. .compatible = "microchip,sam9x60-qspi",
  587. .data = &atmel_sam9x60_qspi_caps,
  588. },
  589. { /* sentinel */ }
  590. };
  591. MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
  592. static struct platform_driver atmel_qspi_driver = {
  593. .driver = {
  594. .name = "atmel_qspi",
  595. .of_match_table = atmel_qspi_dt_ids,
  596. .pm = &atmel_qspi_pm_ops,
  597. },
  598. .probe = atmel_qspi_probe,
  599. .remove = atmel_qspi_remove,
  600. };
  601. module_platform_driver(atmel_qspi_driver);
  602. MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
  603. MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
  604. MODULE_DESCRIPTION("Atmel QSPI Controller driver");
  605. MODULE_LICENSE("GPL v2");