qcom_aoss.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019, Linaro Ltd
  4. */
  5. #include <dt-bindings/power/qcom-aoss-qmp.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/mailbox_client.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pm_domain.h>
  13. #include <linux/thermal.h>
  14. #include <linux/slab.h>
  15. #define QMP_DESC_MAGIC 0x0
  16. #define QMP_DESC_VERSION 0x4
  17. #define QMP_DESC_FEATURES 0x8
  18. /* AOP-side offsets */
  19. #define QMP_DESC_UCORE_LINK_STATE 0xc
  20. #define QMP_DESC_UCORE_LINK_STATE_ACK 0x10
  21. #define QMP_DESC_UCORE_CH_STATE 0x14
  22. #define QMP_DESC_UCORE_CH_STATE_ACK 0x18
  23. #define QMP_DESC_UCORE_MBOX_SIZE 0x1c
  24. #define QMP_DESC_UCORE_MBOX_OFFSET 0x20
  25. /* Linux-side offsets */
  26. #define QMP_DESC_MCORE_LINK_STATE 0x24
  27. #define QMP_DESC_MCORE_LINK_STATE_ACK 0x28
  28. #define QMP_DESC_MCORE_CH_STATE 0x2c
  29. #define QMP_DESC_MCORE_CH_STATE_ACK 0x30
  30. #define QMP_DESC_MCORE_MBOX_SIZE 0x34
  31. #define QMP_DESC_MCORE_MBOX_OFFSET 0x38
  32. #define QMP_STATE_UP GENMASK(15, 0)
  33. #define QMP_STATE_DOWN GENMASK(31, 16)
  34. #define QMP_MAGIC 0x4d41494c /* mail */
  35. #define QMP_VERSION 1
  36. /* 64 bytes is enough to store the requests and provides padding to 4 bytes */
  37. #define QMP_MSG_LEN 64
  38. #define QMP_NUM_COOLING_RESOURCES 2
  39. static bool qmp_cdev_max_state = 1;
  40. struct qmp_cooling_device {
  41. struct thermal_cooling_device *cdev;
  42. struct qmp *qmp;
  43. char *name;
  44. bool state;
  45. };
  46. /**
  47. * struct qmp - driver state for QMP implementation
  48. * @msgram: iomem referencing the message RAM used for communication
  49. * @dev: reference to QMP device
  50. * @mbox_client: mailbox client used to ring the doorbell on transmit
  51. * @mbox_chan: mailbox channel used to ring the doorbell on transmit
  52. * @offset: offset within @msgram where messages should be written
  53. * @size: maximum size of the messages to be transmitted
  54. * @event: wait_queue for synchronization with the IRQ
  55. * @tx_lock: provides synchronization between multiple callers of qmp_send()
  56. * @qdss_clk: QDSS clock hw struct
  57. * @pd_data: genpd data
  58. */
  59. struct qmp {
  60. void __iomem *msgram;
  61. struct device *dev;
  62. struct mbox_client mbox_client;
  63. struct mbox_chan *mbox_chan;
  64. size_t offset;
  65. size_t size;
  66. wait_queue_head_t event;
  67. struct mutex tx_lock;
  68. struct clk_hw qdss_clk;
  69. struct genpd_onecell_data pd_data;
  70. struct qmp_cooling_device *cooling_devs;
  71. };
  72. struct qmp_pd {
  73. struct qmp *qmp;
  74. struct generic_pm_domain pd;
  75. };
  76. #define to_qmp_pd_resource(res) container_of(res, struct qmp_pd, pd)
  77. static void qmp_kick(struct qmp *qmp)
  78. {
  79. mbox_send_message(qmp->mbox_chan, NULL);
  80. mbox_client_txdone(qmp->mbox_chan, 0);
  81. }
  82. static bool qmp_magic_valid(struct qmp *qmp)
  83. {
  84. return readl(qmp->msgram + QMP_DESC_MAGIC) == QMP_MAGIC;
  85. }
  86. static bool qmp_link_acked(struct qmp *qmp)
  87. {
  88. return readl(qmp->msgram + QMP_DESC_MCORE_LINK_STATE_ACK) == QMP_STATE_UP;
  89. }
  90. static bool qmp_mcore_channel_acked(struct qmp *qmp)
  91. {
  92. return readl(qmp->msgram + QMP_DESC_MCORE_CH_STATE_ACK) == QMP_STATE_UP;
  93. }
  94. static bool qmp_ucore_channel_up(struct qmp *qmp)
  95. {
  96. return readl(qmp->msgram + QMP_DESC_UCORE_CH_STATE) == QMP_STATE_UP;
  97. }
  98. static int qmp_open(struct qmp *qmp)
  99. {
  100. int ret;
  101. u32 val;
  102. if (!qmp_magic_valid(qmp)) {
  103. dev_err(qmp->dev, "QMP magic doesn't match\n");
  104. return -EINVAL;
  105. }
  106. val = readl(qmp->msgram + QMP_DESC_VERSION);
  107. if (val != QMP_VERSION) {
  108. dev_err(qmp->dev, "unsupported QMP version %d\n", val);
  109. return -EINVAL;
  110. }
  111. qmp->offset = readl(qmp->msgram + QMP_DESC_MCORE_MBOX_OFFSET);
  112. qmp->size = readl(qmp->msgram + QMP_DESC_MCORE_MBOX_SIZE);
  113. if (!qmp->size) {
  114. dev_err(qmp->dev, "invalid mailbox size\n");
  115. return -EINVAL;
  116. }
  117. /* Ack remote core's link state */
  118. val = readl(qmp->msgram + QMP_DESC_UCORE_LINK_STATE);
  119. writel(val, qmp->msgram + QMP_DESC_UCORE_LINK_STATE_ACK);
  120. /* Set local core's link state to up */
  121. writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
  122. qmp_kick(qmp);
  123. ret = wait_event_timeout(qmp->event, qmp_link_acked(qmp), HZ);
  124. if (!ret) {
  125. dev_err(qmp->dev, "ucore didn't ack link\n");
  126. goto timeout_close_link;
  127. }
  128. writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
  129. qmp_kick(qmp);
  130. ret = wait_event_timeout(qmp->event, qmp_ucore_channel_up(qmp), HZ);
  131. if (!ret) {
  132. dev_err(qmp->dev, "ucore didn't open channel\n");
  133. goto timeout_close_channel;
  134. }
  135. /* Ack remote core's channel state */
  136. writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_UCORE_CH_STATE_ACK);
  137. qmp_kick(qmp);
  138. ret = wait_event_timeout(qmp->event, qmp_mcore_channel_acked(qmp), HZ);
  139. if (!ret) {
  140. dev_err(qmp->dev, "ucore didn't ack channel\n");
  141. goto timeout_close_channel;
  142. }
  143. return 0;
  144. timeout_close_channel:
  145. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
  146. timeout_close_link:
  147. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
  148. qmp_kick(qmp);
  149. return -ETIMEDOUT;
  150. }
  151. static void qmp_close(struct qmp *qmp)
  152. {
  153. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
  154. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
  155. qmp_kick(qmp);
  156. }
  157. static irqreturn_t qmp_intr(int irq, void *data)
  158. {
  159. struct qmp *qmp = data;
  160. wake_up_all(&qmp->event);
  161. return IRQ_HANDLED;
  162. }
  163. static bool qmp_message_empty(struct qmp *qmp)
  164. {
  165. return readl(qmp->msgram + qmp->offset) == 0;
  166. }
  167. /**
  168. * qmp_send() - send a message to the AOSS
  169. * @qmp: qmp context
  170. * @data: message to be sent
  171. * @len: length of the message
  172. *
  173. * Transmit @data to AOSS and wait for the AOSS to acknowledge the message.
  174. * @len must be a multiple of 4 and not longer than the mailbox size. Access is
  175. * synchronized by this implementation.
  176. *
  177. * Return: 0 on success, negative errno on failure
  178. */
  179. static int qmp_send(struct qmp *qmp, const void *data, size_t len)
  180. {
  181. long time_left;
  182. size_t tlen;
  183. int ret;
  184. if (WARN_ON(len + sizeof(u32) > qmp->size))
  185. return -EINVAL;
  186. if (WARN_ON(len % sizeof(u32)))
  187. return -EINVAL;
  188. mutex_lock(&qmp->tx_lock);
  189. /* The message RAM only implements 32-bit accesses */
  190. __iowrite32_copy(qmp->msgram + qmp->offset + sizeof(u32),
  191. data, len / sizeof(u32));
  192. writel(len, qmp->msgram + qmp->offset);
  193. /* Read back len to confirm data written in message RAM */
  194. tlen = readl(qmp->msgram + qmp->offset);
  195. qmp_kick(qmp);
  196. time_left = wait_event_interruptible_timeout(qmp->event,
  197. qmp_message_empty(qmp), HZ);
  198. if (!time_left) {
  199. dev_err(qmp->dev, "ucore did not ack channel\n");
  200. ret = -ETIMEDOUT;
  201. /* Clear message from buffer */
  202. writel(0, qmp->msgram + qmp->offset);
  203. } else {
  204. ret = 0;
  205. }
  206. mutex_unlock(&qmp->tx_lock);
  207. return ret;
  208. }
  209. static int qmp_qdss_clk_prepare(struct clk_hw *hw)
  210. {
  211. static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 1}";
  212. struct qmp *qmp = container_of(hw, struct qmp, qdss_clk);
  213. return qmp_send(qmp, buf, sizeof(buf));
  214. }
  215. static void qmp_qdss_clk_unprepare(struct clk_hw *hw)
  216. {
  217. static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 0}";
  218. struct qmp *qmp = container_of(hw, struct qmp, qdss_clk);
  219. qmp_send(qmp, buf, sizeof(buf));
  220. }
  221. static const struct clk_ops qmp_qdss_clk_ops = {
  222. .prepare = qmp_qdss_clk_prepare,
  223. .unprepare = qmp_qdss_clk_unprepare,
  224. };
  225. static int qmp_qdss_clk_add(struct qmp *qmp)
  226. {
  227. static const struct clk_init_data qdss_init = {
  228. .ops = &qmp_qdss_clk_ops,
  229. .name = "qdss",
  230. };
  231. int ret;
  232. qmp->qdss_clk.init = &qdss_init;
  233. ret = clk_hw_register(qmp->dev, &qmp->qdss_clk);
  234. if (ret < 0) {
  235. dev_err(qmp->dev, "failed to register qdss clock\n");
  236. return ret;
  237. }
  238. ret = of_clk_add_hw_provider(qmp->dev->of_node, of_clk_hw_simple_get,
  239. &qmp->qdss_clk);
  240. if (ret < 0) {
  241. dev_err(qmp->dev, "unable to register of clk hw provider\n");
  242. clk_hw_unregister(&qmp->qdss_clk);
  243. }
  244. return ret;
  245. }
  246. static void qmp_qdss_clk_remove(struct qmp *qmp)
  247. {
  248. of_clk_del_provider(qmp->dev->of_node);
  249. clk_hw_unregister(&qmp->qdss_clk);
  250. }
  251. static int qmp_pd_power_toggle(struct qmp_pd *res, bool enable)
  252. {
  253. char buf[QMP_MSG_LEN] = {};
  254. snprintf(buf, sizeof(buf),
  255. "{class: image, res: load_state, name: %s, val: %s}",
  256. res->pd.name, enable ? "on" : "off");
  257. return qmp_send(res->qmp, buf, sizeof(buf));
  258. }
  259. static int qmp_pd_power_on(struct generic_pm_domain *domain)
  260. {
  261. return qmp_pd_power_toggle(to_qmp_pd_resource(domain), true);
  262. }
  263. static int qmp_pd_power_off(struct generic_pm_domain *domain)
  264. {
  265. return qmp_pd_power_toggle(to_qmp_pd_resource(domain), false);
  266. }
  267. static const char * const sdm845_resources[] = {
  268. [AOSS_QMP_LS_CDSP] = "cdsp",
  269. [AOSS_QMP_LS_LPASS] = "adsp",
  270. [AOSS_QMP_LS_MODEM] = "modem",
  271. [AOSS_QMP_LS_SLPI] = "slpi",
  272. [AOSS_QMP_LS_SPSS] = "spss",
  273. [AOSS_QMP_LS_VENUS] = "venus",
  274. };
  275. static int qmp_pd_add(struct qmp *qmp)
  276. {
  277. struct genpd_onecell_data *data = &qmp->pd_data;
  278. struct device *dev = qmp->dev;
  279. struct qmp_pd *res;
  280. size_t num = ARRAY_SIZE(sdm845_resources);
  281. int ret;
  282. int i;
  283. res = devm_kcalloc(dev, num, sizeof(*res), GFP_KERNEL);
  284. if (!res)
  285. return -ENOMEM;
  286. data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
  287. GFP_KERNEL);
  288. if (!data->domains)
  289. return -ENOMEM;
  290. for (i = 0; i < num; i++) {
  291. res[i].qmp = qmp;
  292. res[i].pd.name = sdm845_resources[i];
  293. res[i].pd.power_on = qmp_pd_power_on;
  294. res[i].pd.power_off = qmp_pd_power_off;
  295. ret = pm_genpd_init(&res[i].pd, NULL, true);
  296. if (ret < 0) {
  297. dev_err(dev, "failed to init genpd\n");
  298. goto unroll_genpds;
  299. }
  300. data->domains[i] = &res[i].pd;
  301. }
  302. data->num_domains = i;
  303. ret = of_genpd_add_provider_onecell(dev->of_node, data);
  304. if (ret < 0)
  305. goto unroll_genpds;
  306. return 0;
  307. unroll_genpds:
  308. for (i--; i >= 0; i--)
  309. pm_genpd_remove(data->domains[i]);
  310. return ret;
  311. }
  312. static void qmp_pd_remove(struct qmp *qmp)
  313. {
  314. struct genpd_onecell_data *data = &qmp->pd_data;
  315. struct device *dev = qmp->dev;
  316. int i;
  317. of_genpd_del_provider(dev->of_node);
  318. for (i = 0; i < data->num_domains; i++)
  319. pm_genpd_remove(data->domains[i]);
  320. }
  321. static int qmp_cdev_get_max_state(struct thermal_cooling_device *cdev,
  322. unsigned long *state)
  323. {
  324. *state = qmp_cdev_max_state;
  325. return 0;
  326. }
  327. static int qmp_cdev_get_cur_state(struct thermal_cooling_device *cdev,
  328. unsigned long *state)
  329. {
  330. struct qmp_cooling_device *qmp_cdev = cdev->devdata;
  331. *state = qmp_cdev->state;
  332. return 0;
  333. }
  334. static int qmp_cdev_set_cur_state(struct thermal_cooling_device *cdev,
  335. unsigned long state)
  336. {
  337. struct qmp_cooling_device *qmp_cdev = cdev->devdata;
  338. char buf[QMP_MSG_LEN] = {};
  339. bool cdev_state;
  340. int ret;
  341. /* Normalize state */
  342. cdev_state = !!state;
  343. if (qmp_cdev->state == state)
  344. return 0;
  345. snprintf(buf, sizeof(buf),
  346. "{class: volt_flr, event:zero_temp, res:%s, value:%s}",
  347. qmp_cdev->name,
  348. cdev_state ? "on" : "off");
  349. ret = qmp_send(qmp_cdev->qmp, buf, sizeof(buf));
  350. if (!ret)
  351. qmp_cdev->state = cdev_state;
  352. return ret;
  353. }
  354. static struct thermal_cooling_device_ops qmp_cooling_device_ops = {
  355. .get_max_state = qmp_cdev_get_max_state,
  356. .get_cur_state = qmp_cdev_get_cur_state,
  357. .set_cur_state = qmp_cdev_set_cur_state,
  358. };
  359. static int qmp_cooling_device_add(struct qmp *qmp,
  360. struct qmp_cooling_device *qmp_cdev,
  361. struct device_node *node)
  362. {
  363. char *cdev_name = (char *)node->name;
  364. qmp_cdev->qmp = qmp;
  365. qmp_cdev->state = !qmp_cdev_max_state;
  366. qmp_cdev->name = cdev_name;
  367. qmp_cdev->cdev = devm_thermal_of_cooling_device_register
  368. (qmp->dev, node,
  369. cdev_name,
  370. qmp_cdev, &qmp_cooling_device_ops);
  371. if (IS_ERR(qmp_cdev->cdev))
  372. dev_err(qmp->dev, "unable to register %s cooling device\n",
  373. cdev_name);
  374. return PTR_ERR_OR_ZERO(qmp_cdev->cdev);
  375. }
  376. static int qmp_cooling_devices_register(struct qmp *qmp)
  377. {
  378. struct device_node *np, *child;
  379. int count = 0;
  380. int ret;
  381. np = qmp->dev->of_node;
  382. qmp->cooling_devs = devm_kcalloc(qmp->dev, QMP_NUM_COOLING_RESOURCES,
  383. sizeof(*qmp->cooling_devs),
  384. GFP_KERNEL);
  385. if (!qmp->cooling_devs)
  386. return -ENOMEM;
  387. for_each_available_child_of_node(np, child) {
  388. if (!of_find_property(child, "#cooling-cells", NULL))
  389. continue;
  390. ret = qmp_cooling_device_add(qmp, &qmp->cooling_devs[count++],
  391. child);
  392. if (ret)
  393. goto unroll;
  394. }
  395. if (!count)
  396. devm_kfree(qmp->dev, qmp->cooling_devs);
  397. return 0;
  398. unroll:
  399. while (--count >= 0)
  400. thermal_cooling_device_unregister
  401. (qmp->cooling_devs[count].cdev);
  402. devm_kfree(qmp->dev, qmp->cooling_devs);
  403. return ret;
  404. }
  405. static void qmp_cooling_devices_remove(struct qmp *qmp)
  406. {
  407. int i;
  408. for (i = 0; i < QMP_NUM_COOLING_RESOURCES; i++)
  409. thermal_cooling_device_unregister(qmp->cooling_devs[i].cdev);
  410. }
  411. static int qmp_probe(struct platform_device *pdev)
  412. {
  413. struct resource *res;
  414. struct qmp *qmp;
  415. int irq;
  416. int ret;
  417. qmp = devm_kzalloc(&pdev->dev, sizeof(*qmp), GFP_KERNEL);
  418. if (!qmp)
  419. return -ENOMEM;
  420. qmp->dev = &pdev->dev;
  421. init_waitqueue_head(&qmp->event);
  422. mutex_init(&qmp->tx_lock);
  423. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  424. qmp->msgram = devm_ioremap_resource(&pdev->dev, res);
  425. if (IS_ERR(qmp->msgram))
  426. return PTR_ERR(qmp->msgram);
  427. qmp->mbox_client.dev = &pdev->dev;
  428. qmp->mbox_client.knows_txdone = true;
  429. qmp->mbox_chan = mbox_request_channel(&qmp->mbox_client, 0);
  430. if (IS_ERR(qmp->mbox_chan)) {
  431. dev_err(&pdev->dev, "failed to acquire ipc mailbox\n");
  432. return PTR_ERR(qmp->mbox_chan);
  433. }
  434. irq = platform_get_irq(pdev, 0);
  435. ret = devm_request_irq(&pdev->dev, irq, qmp_intr, 0,
  436. "aoss-qmp", qmp);
  437. if (ret < 0) {
  438. dev_err(&pdev->dev, "failed to request interrupt\n");
  439. goto err_free_mbox;
  440. }
  441. ret = qmp_open(qmp);
  442. if (ret < 0)
  443. goto err_free_mbox;
  444. ret = qmp_qdss_clk_add(qmp);
  445. if (ret)
  446. goto err_close_qmp;
  447. ret = qmp_pd_add(qmp);
  448. if (ret)
  449. goto err_remove_qdss_clk;
  450. ret = qmp_cooling_devices_register(qmp);
  451. if (ret)
  452. dev_err(&pdev->dev, "failed to register aoss cooling devices\n");
  453. platform_set_drvdata(pdev, qmp);
  454. return 0;
  455. err_remove_qdss_clk:
  456. qmp_qdss_clk_remove(qmp);
  457. err_close_qmp:
  458. qmp_close(qmp);
  459. err_free_mbox:
  460. mbox_free_channel(qmp->mbox_chan);
  461. return ret;
  462. }
  463. static int qmp_remove(struct platform_device *pdev)
  464. {
  465. struct qmp *qmp = platform_get_drvdata(pdev);
  466. qmp_qdss_clk_remove(qmp);
  467. qmp_pd_remove(qmp);
  468. qmp_cooling_devices_remove(qmp);
  469. qmp_close(qmp);
  470. mbox_free_channel(qmp->mbox_chan);
  471. return 0;
  472. }
  473. static const struct of_device_id qmp_dt_match[] = {
  474. { .compatible = "qcom,sc7180-aoss-qmp", },
  475. { .compatible = "qcom,sdm845-aoss-qmp", },
  476. { .compatible = "qcom,sm8150-aoss-qmp", },
  477. { .compatible = "qcom,sm8250-aoss-qmp", },
  478. {}
  479. };
  480. MODULE_DEVICE_TABLE(of, qmp_dt_match);
  481. static struct platform_driver qmp_driver = {
  482. .driver = {
  483. .name = "qcom_aoss_qmp",
  484. .of_match_table = qmp_dt_match,
  485. },
  486. .probe = qmp_probe,
  487. .remove = qmp_remove,
  488. };
  489. module_platform_driver(qmp_driver);
  490. MODULE_DESCRIPTION("Qualcomm AOSS QMP driver");
  491. MODULE_LICENSE("GPL v2");