qcom-geni-se.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
  3. #include <linux/acpi.h>
  4. #include <linux/clk.h>
  5. #include <linux/slab.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/io.h>
  8. #include <linux/module.h>
  9. #include <linux/of.h>
  10. #include <linux/of_platform.h>
  11. #include <linux/pinctrl/consumer.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/qcom-geni-se.h>
  14. /**
  15. * DOC: Overview
  16. *
  17. * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
  18. * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
  19. * controller. QUP Wrapper is designed to support various serial bus protocols
  20. * like UART, SPI, I2C, I3C, etc.
  21. */
  22. /**
  23. * DOC: Hardware description
  24. *
  25. * GENI based QUP is a highly-flexible and programmable module for supporting
  26. * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
  27. * QUP module can provide upto 8 serial interfaces, using its internal
  28. * serial engines. The actual configuration is determined by the target
  29. * platform configuration. The protocol supported by each interface is
  30. * determined by the firmware loaded to the serial engine. Each SE consists
  31. * of a DMA Engine and GENI sub modules which enable serial engines to
  32. * support FIFO and DMA modes of operation.
  33. *
  34. *
  35. * +-----------------------------------------+
  36. * |QUP Wrapper |
  37. * | +----------------------------+ |
  38. * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
  39. * | | ... | | Interface
  40. * <---Clock Perf.----+ +----+-----------------------+ | |
  41. * State Interface | | Serial Engine 1 | | |
  42. * | | | | |
  43. * | | | | |
  44. * <--------AHB-------> | | | |
  45. * | | +----+ |
  46. * | | | |
  47. * | | | |
  48. * <------SE IRQ------+ +----------------------------+ |
  49. * | |
  50. * +-----------------------------------------+
  51. *
  52. * Figure 1: GENI based QUP Wrapper
  53. *
  54. * The GENI submodules include primary and secondary sequencers which are
  55. * used to drive TX & RX operations. On serial interfaces that operate using
  56. * master-slave model, primary sequencer drives both TX & RX operations. On
  57. * serial interfaces that operate using peer-to-peer model, primary sequencer
  58. * drives TX operation and secondary sequencer drives RX operation.
  59. */
  60. /**
  61. * DOC: Software description
  62. *
  63. * GENI SE Wrapper driver is structured into 2 parts:
  64. *
  65. * geni_wrapper represents QUP Wrapper controller. This part of the driver
  66. * manages QUP Wrapper information such as hardware version, clock
  67. * performance table that is common to all the internal serial engines.
  68. *
  69. * geni_se represents serial engine. This part of the driver manages serial
  70. * engine information such as clocks, containing QUP Wrapper, etc. This part
  71. * of driver also supports operations (eg. initialize the concerned serial
  72. * engine, select between FIFO and DMA mode of operation etc.) that are
  73. * common to all the serial engines and are independent of serial interfaces.
  74. */
  75. #define MAX_CLK_PERF_LEVEL 32
  76. #define NUM_AHB_CLKS 2
  77. /**
  78. * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core
  79. * @dev: Device pointer of the QUP wrapper core
  80. * @base: Base address of this instance of QUP wrapper core
  81. * @ahb_clks: Handle to the primary & secondary AHB clocks
  82. */
  83. struct geni_wrapper {
  84. struct device *dev;
  85. void __iomem *base;
  86. struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
  87. };
  88. static const char * const icc_path_names[] = {"qup-core", "qup-config",
  89. "qup-memory"};
  90. #define QUP_HW_VER_REG 0x4
  91. /* Common SE registers */
  92. #define GENI_INIT_CFG_REVISION 0x0
  93. #define GENI_S_INIT_CFG_REVISION 0x4
  94. #define GENI_OUTPUT_CTRL 0x24
  95. #define GENI_CGC_CTRL 0x28
  96. #define GENI_CLK_CTRL_RO 0x60
  97. #define GENI_IF_DISABLE_RO 0x64
  98. #define GENI_FW_S_REVISION_RO 0x6c
  99. #define SE_GENI_BYTE_GRAN 0x254
  100. #define SE_GENI_TX_PACKING_CFG0 0x260
  101. #define SE_GENI_TX_PACKING_CFG1 0x264
  102. #define SE_GENI_RX_PACKING_CFG0 0x284
  103. #define SE_GENI_RX_PACKING_CFG1 0x288
  104. #define SE_GENI_M_GP_LENGTH 0x910
  105. #define SE_GENI_S_GP_LENGTH 0x914
  106. #define SE_DMA_TX_PTR_L 0xc30
  107. #define SE_DMA_TX_PTR_H 0xc34
  108. #define SE_DMA_TX_ATTR 0xc38
  109. #define SE_DMA_TX_LEN 0xc3c
  110. #define SE_DMA_TX_IRQ_EN 0xc48
  111. #define SE_DMA_TX_IRQ_EN_SET 0xc4c
  112. #define SE_DMA_TX_IRQ_EN_CLR 0xc50
  113. #define SE_DMA_TX_LEN_IN 0xc54
  114. #define SE_DMA_TX_MAX_BURST 0xc5c
  115. #define SE_DMA_RX_PTR_L 0xd30
  116. #define SE_DMA_RX_PTR_H 0xd34
  117. #define SE_DMA_RX_ATTR 0xd38
  118. #define SE_DMA_RX_LEN 0xd3c
  119. #define SE_DMA_RX_IRQ_EN 0xd48
  120. #define SE_DMA_RX_IRQ_EN_SET 0xd4c
  121. #define SE_DMA_RX_IRQ_EN_CLR 0xd50
  122. #define SE_DMA_RX_LEN_IN 0xd54
  123. #define SE_DMA_RX_MAX_BURST 0xd5c
  124. #define SE_DMA_RX_FLUSH 0xd60
  125. #define SE_GSI_EVENT_EN 0xe18
  126. #define SE_IRQ_EN 0xe1c
  127. #define SE_DMA_GENERAL_CFG 0xe30
  128. /* GENI_OUTPUT_CTRL fields */
  129. #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
  130. /* GENI_CGC_CTRL fields */
  131. #define CFG_AHB_CLK_CGC_ON BIT(0)
  132. #define CFG_AHB_WR_ACLK_CGC_ON BIT(1)
  133. #define DATA_AHB_CLK_CGC_ON BIT(2)
  134. #define SCLK_CGC_ON BIT(3)
  135. #define TX_CLK_CGC_ON BIT(4)
  136. #define RX_CLK_CGC_ON BIT(5)
  137. #define EXT_CLK_CGC_ON BIT(6)
  138. #define PROG_RAM_HCLK_OFF BIT(8)
  139. #define PROG_RAM_SCLK_OFF BIT(9)
  140. #define DEFAULT_CGC_EN GENMASK(6, 0)
  141. /* SE_GSI_EVENT_EN fields */
  142. #define DMA_RX_EVENT_EN BIT(0)
  143. #define DMA_TX_EVENT_EN BIT(1)
  144. #define GENI_M_EVENT_EN BIT(2)
  145. #define GENI_S_EVENT_EN BIT(3)
  146. /* SE_IRQ_EN fields */
  147. #define DMA_RX_IRQ_EN BIT(0)
  148. #define DMA_TX_IRQ_EN BIT(1)
  149. #define GENI_M_IRQ_EN BIT(2)
  150. #define GENI_S_IRQ_EN BIT(3)
  151. /* SE_DMA_GENERAL_CFG */
  152. #define DMA_RX_CLK_CGC_ON BIT(0)
  153. #define DMA_TX_CLK_CGC_ON BIT(1)
  154. #define DMA_AHB_SLV_CFG_ON BIT(2)
  155. #define AHB_SEC_SLV_CLK_CGC_ON BIT(3)
  156. #define DUMMY_RX_NON_BUFFERABLE BIT(4)
  157. #define RX_DMA_ZERO_PADDING_EN BIT(5)
  158. #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
  159. #define RX_DMA_IRQ_DELAY_SHFT 6
  160. /**
  161. * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
  162. * @se: Pointer to the corresponding serial engine.
  163. *
  164. * Return: Hardware Version of the wrapper.
  165. */
  166. u32 geni_se_get_qup_hw_version(struct geni_se *se)
  167. {
  168. struct geni_wrapper *wrapper = se->wrapper;
  169. return readl_relaxed(wrapper->base + QUP_HW_VER_REG);
  170. }
  171. EXPORT_SYMBOL(geni_se_get_qup_hw_version);
  172. static void geni_se_io_set_mode(void __iomem *base)
  173. {
  174. u32 val;
  175. val = readl_relaxed(base + SE_IRQ_EN);
  176. val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN;
  177. val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN;
  178. writel_relaxed(val, base + SE_IRQ_EN);
  179. val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
  180. val &= ~GENI_DMA_MODE_EN;
  181. writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
  182. writel_relaxed(0, base + SE_GSI_EVENT_EN);
  183. }
  184. static void geni_se_io_init(void __iomem *base)
  185. {
  186. u32 val;
  187. val = readl_relaxed(base + GENI_CGC_CTRL);
  188. val |= DEFAULT_CGC_EN;
  189. writel_relaxed(val, base + GENI_CGC_CTRL);
  190. val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
  191. val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON;
  192. val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
  193. writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
  194. writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
  195. writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
  196. }
  197. static void geni_se_irq_clear(struct geni_se *se)
  198. {
  199. writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
  200. writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
  201. writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
  202. writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
  203. writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
  204. writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
  205. }
  206. /**
  207. * geni_se_init() - Initialize the GENI serial engine
  208. * @se: Pointer to the concerned serial engine.
  209. * @rx_wm: Receive watermark, in units of FIFO words.
  210. * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words.
  211. *
  212. * This function is used to initialize the GENI serial engine, configure
  213. * receive watermark and ready-for-receive watermarks.
  214. */
  215. void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
  216. {
  217. u32 val;
  218. geni_se_irq_clear(se);
  219. geni_se_io_init(se->base);
  220. geni_se_io_set_mode(se->base);
  221. writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
  222. writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
  223. val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
  224. val |= M_COMMON_GENI_M_IRQ_EN;
  225. writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
  226. val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
  227. val |= S_COMMON_GENI_S_IRQ_EN;
  228. writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
  229. }
  230. EXPORT_SYMBOL(geni_se_init);
  231. static void geni_se_select_fifo_mode(struct geni_se *se)
  232. {
  233. u32 proto = geni_se_read_proto(se);
  234. u32 val;
  235. geni_se_irq_clear(se);
  236. val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
  237. if (proto != GENI_SE_UART) {
  238. val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
  239. val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
  240. }
  241. writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
  242. val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
  243. if (proto != GENI_SE_UART)
  244. val |= S_CMD_DONE_EN;
  245. writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
  246. val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
  247. val &= ~GENI_DMA_MODE_EN;
  248. writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
  249. }
  250. static void geni_se_select_dma_mode(struct geni_se *se)
  251. {
  252. u32 proto = geni_se_read_proto(se);
  253. u32 val;
  254. geni_se_irq_clear(se);
  255. val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
  256. if (proto != GENI_SE_UART) {
  257. val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
  258. val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
  259. }
  260. writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
  261. val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
  262. if (proto != GENI_SE_UART)
  263. val &= ~S_CMD_DONE_EN;
  264. writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
  265. val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
  266. val |= GENI_DMA_MODE_EN;
  267. writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
  268. }
  269. /**
  270. * geni_se_select_mode() - Select the serial engine transfer mode
  271. * @se: Pointer to the concerned serial engine.
  272. * @mode: Transfer mode to be selected.
  273. */
  274. void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
  275. {
  276. WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA);
  277. switch (mode) {
  278. case GENI_SE_FIFO:
  279. geni_se_select_fifo_mode(se);
  280. break;
  281. case GENI_SE_DMA:
  282. geni_se_select_dma_mode(se);
  283. break;
  284. case GENI_SE_INVALID:
  285. default:
  286. break;
  287. }
  288. }
  289. EXPORT_SYMBOL(geni_se_select_mode);
  290. /**
  291. * DOC: Overview
  292. *
  293. * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
  294. * of up to 4 operations, each operation represented by 4 configuration vectors
  295. * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for
  296. * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.
  297. * Refer to below examples for detailed bit-field description.
  298. *
  299. * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1
  300. *
  301. * +-----------+-------+-------+-------+-------+
  302. * | | vec_0 | vec_1 | vec_2 | vec_3 |
  303. * +-----------+-------+-------+-------+-------+
  304. * | start | 0x6 | 0xe | 0x16 | 0x1e |
  305. * | direction | 1 | 1 | 1 | 1 |
  306. * | length | 6 | 6 | 6 | 6 |
  307. * | stop | 0 | 0 | 0 | 1 |
  308. * +-----------+-------+-------+-------+-------+
  309. *
  310. * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0
  311. *
  312. * +-----------+-------+-------+-------+-------+
  313. * | | vec_0 | vec_1 | vec_2 | vec_3 |
  314. * +-----------+-------+-------+-------+-------+
  315. * | start | 0x0 | 0x8 | 0x10 | 0x18 |
  316. * | direction | 0 | 0 | 0 | 0 |
  317. * | length | 7 | 6 | 7 | 6 |
  318. * | stop | 0 | 0 | 0 | 1 |
  319. * +-----------+-------+-------+-------+-------+
  320. *
  321. * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1
  322. *
  323. * +-----------+-------+-------+-------+-------+
  324. * | | vec_0 | vec_1 | vec_2 | vec_3 |
  325. * +-----------+-------+-------+-------+-------+
  326. * | start | 0x16 | 0xe | 0x6 | 0x0 |
  327. * | direction | 1 | 1 | 1 | 1 |
  328. * | length | 7 | 7 | 6 | 0 |
  329. * | stop | 0 | 0 | 1 | 0 |
  330. * +-----------+-------+-------+-------+-------+
  331. *
  332. */
  333. #define NUM_PACKING_VECTORS 4
  334. #define PACKING_START_SHIFT 5
  335. #define PACKING_DIR_SHIFT 4
  336. #define PACKING_LEN_SHIFT 1
  337. #define PACKING_STOP_BIT BIT(0)
  338. #define PACKING_VECTOR_SHIFT 10
  339. /**
  340. * geni_se_config_packing() - Packing configuration of the serial engine
  341. * @se: Pointer to the concerned serial engine
  342. * @bpw: Bits of data per transfer word.
  343. * @pack_words: Number of words per fifo element.
  344. * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
  345. * @tx_cfg: Flag to configure the TX Packing.
  346. * @rx_cfg: Flag to configure the RX Packing.
  347. *
  348. * This function is used to configure the packing rules for the current
  349. * transfer.
  350. */
  351. void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
  352. bool msb_to_lsb, bool tx_cfg, bool rx_cfg)
  353. {
  354. u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0};
  355. int len;
  356. int temp_bpw = bpw;
  357. int idx_start = msb_to_lsb ? bpw - 1 : 0;
  358. int idx = idx_start;
  359. int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE;
  360. int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE);
  361. int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE;
  362. int i;
  363. if (iter <= 0 || iter > NUM_PACKING_VECTORS)
  364. return;
  365. for (i = 0; i < iter; i++) {
  366. len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1;
  367. cfg[i] = idx << PACKING_START_SHIFT;
  368. cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT;
  369. cfg[i] |= len << PACKING_LEN_SHIFT;
  370. if (temp_bpw <= BITS_PER_BYTE) {
  371. idx = ((i + 1) * BITS_PER_BYTE) + idx_start;
  372. temp_bpw = bpw;
  373. } else {
  374. idx = idx + idx_delta;
  375. temp_bpw = temp_bpw - BITS_PER_BYTE;
  376. }
  377. }
  378. cfg[iter - 1] |= PACKING_STOP_BIT;
  379. cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);
  380. cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT);
  381. if (tx_cfg) {
  382. writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
  383. writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
  384. }
  385. if (rx_cfg) {
  386. writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
  387. writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
  388. }
  389. /*
  390. * Number of protocol words in each FIFO entry
  391. * 0 - 4x8, four words in each entry, max word size of 8 bits
  392. * 1 - 2x16, two words in each entry, max word size of 16 bits
  393. * 2 - 1x32, one word in each entry, max word size of 32 bits
  394. * 3 - undefined
  395. */
  396. if (pack_words || bpw == 32)
  397. writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
  398. }
  399. EXPORT_SYMBOL(geni_se_config_packing);
  400. static void geni_se_clks_off(struct geni_se *se)
  401. {
  402. struct geni_wrapper *wrapper = se->wrapper;
  403. clk_disable_unprepare(se->clk);
  404. clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
  405. wrapper->ahb_clks);
  406. }
  407. /**
  408. * geni_se_resources_off() - Turn off resources associated with the serial
  409. * engine
  410. * @se: Pointer to the concerned serial engine.
  411. *
  412. * Return: 0 on success, standard Linux error codes on failure/error.
  413. */
  414. int geni_se_resources_off(struct geni_se *se)
  415. {
  416. int ret;
  417. if (has_acpi_companion(se->dev))
  418. return 0;
  419. ret = pinctrl_pm_select_sleep_state(se->dev);
  420. if (ret)
  421. return ret;
  422. geni_se_clks_off(se);
  423. return 0;
  424. }
  425. EXPORT_SYMBOL(geni_se_resources_off);
  426. static int geni_se_clks_on(struct geni_se *se)
  427. {
  428. int ret;
  429. struct geni_wrapper *wrapper = se->wrapper;
  430. ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks),
  431. wrapper->ahb_clks);
  432. if (ret)
  433. return ret;
  434. ret = clk_prepare_enable(se->clk);
  435. if (ret)
  436. clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
  437. wrapper->ahb_clks);
  438. return ret;
  439. }
  440. /**
  441. * geni_se_resources_on() - Turn on resources associated with the serial
  442. * engine
  443. * @se: Pointer to the concerned serial engine.
  444. *
  445. * Return: 0 on success, standard Linux error codes on failure/error.
  446. */
  447. int geni_se_resources_on(struct geni_se *se)
  448. {
  449. int ret;
  450. if (has_acpi_companion(se->dev))
  451. return 0;
  452. ret = geni_se_clks_on(se);
  453. if (ret)
  454. return ret;
  455. ret = pinctrl_pm_select_default_state(se->dev);
  456. if (ret)
  457. geni_se_clks_off(se);
  458. return ret;
  459. }
  460. EXPORT_SYMBOL(geni_se_resources_on);
  461. /**
  462. * geni_se_clk_tbl_get() - Get the clock table to program DFS
  463. * @se: Pointer to the concerned serial engine.
  464. * @tbl: Table in which the output is returned.
  465. *
  466. * This function is called by the protocol drivers to determine the different
  467. * clock frequencies supported by serial engine core clock. The protocol
  468. * drivers use the output to determine the clock frequency index to be
  469. * programmed into DFS.
  470. *
  471. * Return: number of valid performance levels in the table on success,
  472. * standard Linux error codes on failure.
  473. */
  474. int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)
  475. {
  476. long freq = 0;
  477. int i;
  478. if (se->clk_perf_tbl) {
  479. *tbl = se->clk_perf_tbl;
  480. return se->num_clk_levels;
  481. }
  482. se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,
  483. sizeof(*se->clk_perf_tbl),
  484. GFP_KERNEL);
  485. if (!se->clk_perf_tbl)
  486. return -ENOMEM;
  487. for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {
  488. freq = clk_round_rate(se->clk, freq + 1);
  489. if (freq <= 0 || freq == se->clk_perf_tbl[i - 1])
  490. break;
  491. se->clk_perf_tbl[i] = freq;
  492. }
  493. se->num_clk_levels = i;
  494. *tbl = se->clk_perf_tbl;
  495. return se->num_clk_levels;
  496. }
  497. EXPORT_SYMBOL(geni_se_clk_tbl_get);
  498. /**
  499. * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
  500. * @se: Pointer to the concerned serial engine.
  501. * @req_freq: Requested clock frequency.
  502. * @index: Index of the resultant frequency in the table.
  503. * @res_freq: Resultant frequency of the source clock.
  504. * @exact: Flag to indicate exact multiple requirement of the requested
  505. * frequency.
  506. *
  507. * This function is called by the protocol drivers to determine the best match
  508. * of the requested frequency as provided by the serial engine clock in order
  509. * to meet the performance requirements.
  510. *
  511. * If we return success:
  512. * - if @exact is true then @res_freq / <an_integer> == @req_freq
  513. * - if @exact is false then @res_freq / <an_integer> <= @req_freq
  514. *
  515. * Return: 0 on success, standard Linux error codes on failure.
  516. */
  517. int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
  518. unsigned int *index, unsigned long *res_freq,
  519. bool exact)
  520. {
  521. unsigned long *tbl;
  522. int num_clk_levels;
  523. int i;
  524. unsigned long best_delta;
  525. unsigned long new_delta;
  526. unsigned int divider;
  527. num_clk_levels = geni_se_clk_tbl_get(se, &tbl);
  528. if (num_clk_levels < 0)
  529. return num_clk_levels;
  530. if (num_clk_levels == 0)
  531. return -EINVAL;
  532. best_delta = ULONG_MAX;
  533. for (i = 0; i < num_clk_levels; i++) {
  534. divider = DIV_ROUND_UP(tbl[i], req_freq);
  535. new_delta = req_freq - tbl[i] / divider;
  536. if (new_delta < best_delta) {
  537. /* We have a new best! */
  538. *index = i;
  539. *res_freq = tbl[i];
  540. /* If the new best is exact then we're done */
  541. if (new_delta == 0)
  542. return 0;
  543. /* Record how close we got */
  544. best_delta = new_delta;
  545. }
  546. }
  547. if (exact)
  548. return -EINVAL;
  549. return 0;
  550. }
  551. EXPORT_SYMBOL(geni_se_clk_freq_match);
  552. #define GENI_SE_DMA_DONE_EN BIT(0)
  553. #define GENI_SE_DMA_EOT_EN BIT(1)
  554. #define GENI_SE_DMA_AHB_ERR_EN BIT(2)
  555. #define GENI_SE_DMA_EOT_BUF BIT(0)
  556. /**
  557. * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
  558. * @se: Pointer to the concerned serial engine.
  559. * @buf: Pointer to the TX buffer.
  560. * @len: Length of the TX buffer.
  561. * @iova: Pointer to store the mapped DMA address.
  562. *
  563. * This function is used to prepare the buffers for DMA TX.
  564. *
  565. * Return: 0 on success, standard Linux error codes on failure.
  566. */
  567. int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
  568. dma_addr_t *iova)
  569. {
  570. struct geni_wrapper *wrapper = se->wrapper;
  571. u32 val;
  572. if (!wrapper)
  573. return -EINVAL;
  574. *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE);
  575. if (dma_mapping_error(wrapper->dev, *iova))
  576. return -EIO;
  577. val = GENI_SE_DMA_DONE_EN;
  578. val |= GENI_SE_DMA_EOT_EN;
  579. val |= GENI_SE_DMA_AHB_ERR_EN;
  580. writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
  581. writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L);
  582. writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H);
  583. writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
  584. writel(len, se->base + SE_DMA_TX_LEN);
  585. return 0;
  586. }
  587. EXPORT_SYMBOL(geni_se_tx_dma_prep);
  588. /**
  589. * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
  590. * @se: Pointer to the concerned serial engine.
  591. * @buf: Pointer to the RX buffer.
  592. * @len: Length of the RX buffer.
  593. * @iova: Pointer to store the mapped DMA address.
  594. *
  595. * This function is used to prepare the buffers for DMA RX.
  596. *
  597. * Return: 0 on success, standard Linux error codes on failure.
  598. */
  599. int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
  600. dma_addr_t *iova)
  601. {
  602. struct geni_wrapper *wrapper = se->wrapper;
  603. u32 val;
  604. if (!wrapper)
  605. return -EINVAL;
  606. *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE);
  607. if (dma_mapping_error(wrapper->dev, *iova))
  608. return -EIO;
  609. val = GENI_SE_DMA_DONE_EN;
  610. val |= GENI_SE_DMA_EOT_EN;
  611. val |= GENI_SE_DMA_AHB_ERR_EN;
  612. writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
  613. writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L);
  614. writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H);
  615. /* RX does not have EOT buffer type bit. So just reset RX_ATTR */
  616. writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
  617. writel(len, se->base + SE_DMA_RX_LEN);
  618. return 0;
  619. }
  620. EXPORT_SYMBOL(geni_se_rx_dma_prep);
  621. /**
  622. * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
  623. * @se: Pointer to the concerned serial engine.
  624. * @iova: DMA address of the TX buffer.
  625. * @len: Length of the TX buffer.
  626. *
  627. * This function is used to unprepare the DMA buffers after DMA TX.
  628. */
  629. void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
  630. {
  631. struct geni_wrapper *wrapper = se->wrapper;
  632. if (iova && !dma_mapping_error(wrapper->dev, iova))
  633. dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE);
  634. }
  635. EXPORT_SYMBOL(geni_se_tx_dma_unprep);
  636. /**
  637. * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
  638. * @se: Pointer to the concerned serial engine.
  639. * @iova: DMA address of the RX buffer.
  640. * @len: Length of the RX buffer.
  641. *
  642. * This function is used to unprepare the DMA buffers after DMA RX.
  643. */
  644. void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
  645. {
  646. struct geni_wrapper *wrapper = se->wrapper;
  647. if (iova && !dma_mapping_error(wrapper->dev, iova))
  648. dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE);
  649. }
  650. EXPORT_SYMBOL(geni_se_rx_dma_unprep);
  651. int geni_icc_get(struct geni_se *se, const char *icc_ddr)
  652. {
  653. int i, err;
  654. const char *icc_names[] = {"qup-core", "qup-config", icc_ddr};
  655. if (has_acpi_companion(se->dev))
  656. return 0;
  657. for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
  658. if (!icc_names[i])
  659. continue;
  660. se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);
  661. if (IS_ERR(se->icc_paths[i].path))
  662. goto err;
  663. }
  664. return 0;
  665. err:
  666. err = PTR_ERR(se->icc_paths[i].path);
  667. if (err != -EPROBE_DEFER)
  668. dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n",
  669. icc_names[i], err);
  670. return err;
  671. }
  672. EXPORT_SYMBOL(geni_icc_get);
  673. int geni_icc_set_bw(struct geni_se *se)
  674. {
  675. int i, ret;
  676. for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
  677. ret = icc_set_bw(se->icc_paths[i].path,
  678. se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw);
  679. if (ret) {
  680. dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n",
  681. icc_path_names[i], ret);
  682. return ret;
  683. }
  684. }
  685. return 0;
  686. }
  687. EXPORT_SYMBOL(geni_icc_set_bw);
  688. void geni_icc_set_tag(struct geni_se *se, u32 tag)
  689. {
  690. int i;
  691. for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++)
  692. icc_set_tag(se->icc_paths[i].path, tag);
  693. }
  694. EXPORT_SYMBOL(geni_icc_set_tag);
  695. /* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */
  696. int geni_icc_enable(struct geni_se *se)
  697. {
  698. int i, ret;
  699. for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
  700. ret = icc_enable(se->icc_paths[i].path);
  701. if (ret) {
  702. dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n",
  703. icc_path_names[i], ret);
  704. return ret;
  705. }
  706. }
  707. return 0;
  708. }
  709. EXPORT_SYMBOL(geni_icc_enable);
  710. int geni_icc_disable(struct geni_se *se)
  711. {
  712. int i, ret;
  713. for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
  714. ret = icc_disable(se->icc_paths[i].path);
  715. if (ret) {
  716. dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n",
  717. icc_path_names[i], ret);
  718. return ret;
  719. }
  720. }
  721. return 0;
  722. }
  723. EXPORT_SYMBOL(geni_icc_disable);
  724. static int geni_se_probe(struct platform_device *pdev)
  725. {
  726. struct device *dev = &pdev->dev;
  727. struct resource *res;
  728. struct geni_wrapper *wrapper;
  729. int ret;
  730. wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
  731. if (!wrapper)
  732. return -ENOMEM;
  733. wrapper->dev = dev;
  734. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  735. wrapper->base = devm_ioremap_resource(dev, res);
  736. if (IS_ERR(wrapper->base))
  737. return PTR_ERR(wrapper->base);
  738. if (!has_acpi_companion(&pdev->dev)) {
  739. wrapper->ahb_clks[0].id = "m-ahb";
  740. wrapper->ahb_clks[1].id = "s-ahb";
  741. ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks);
  742. if (ret) {
  743. dev_err(dev, "Err getting AHB clks %d\n", ret);
  744. return ret;
  745. }
  746. }
  747. dev_set_drvdata(dev, wrapper);
  748. dev_dbg(dev, "GENI SE Driver probed\n");
  749. return devm_of_platform_populate(dev);
  750. }
  751. static const struct of_device_id geni_se_dt_match[] = {
  752. { .compatible = "qcom,geni-se-qup", },
  753. {}
  754. };
  755. MODULE_DEVICE_TABLE(of, geni_se_dt_match);
  756. static struct platform_driver geni_se_driver = {
  757. .driver = {
  758. .name = "geni_se_qup",
  759. .of_match_table = geni_se_dt_match,
  760. },
  761. .probe = geni_se_probe,
  762. };
  763. module_platform_driver(geni_se_driver);
  764. MODULE_DESCRIPTION("GENI Serial Engine Driver");
  765. MODULE_LICENSE("GPL v2");