ixp4xx-qmgr.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel IXP4xx Queue Manager driver for Linux
  4. *
  5. * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
  6. */
  7. #include <linux/ioport.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/soc/ixp4xx/qmgr.h>
  14. static struct qmgr_regs __iomem *qmgr_regs;
  15. static int qmgr_irq_1;
  16. static int qmgr_irq_2;
  17. static spinlock_t qmgr_lock;
  18. static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
  19. static void (*irq_handlers[QUEUES])(void *pdev);
  20. static void *irq_pdevs[QUEUES];
  21. #if DEBUG_QMGR
  22. char qmgr_queue_descs[QUEUES][32];
  23. #endif
  24. void qmgr_put_entry(unsigned int queue, u32 val)
  25. {
  26. #if DEBUG_QMGR
  27. BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
  28. printk(KERN_DEBUG "Queue %s(%i) put %X\n",
  29. qmgr_queue_descs[queue], queue, val);
  30. #endif
  31. __raw_writel(val, &qmgr_regs->acc[queue][0]);
  32. }
  33. u32 qmgr_get_entry(unsigned int queue)
  34. {
  35. u32 val;
  36. val = __raw_readl(&qmgr_regs->acc[queue][0]);
  37. #if DEBUG_QMGR
  38. BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
  39. printk(KERN_DEBUG "Queue %s(%i) get %X\n",
  40. qmgr_queue_descs[queue], queue, val);
  41. #endif
  42. return val;
  43. }
  44. static int __qmgr_get_stat1(unsigned int queue)
  45. {
  46. return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
  47. >> ((queue & 7) << 2)) & 0xF;
  48. }
  49. static int __qmgr_get_stat2(unsigned int queue)
  50. {
  51. BUG_ON(queue >= HALF_QUEUES);
  52. return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
  53. >> ((queue & 0xF) << 1)) & 0x3;
  54. }
  55. /**
  56. * qmgr_stat_empty() - checks if a hardware queue is empty
  57. * @queue: queue number
  58. *
  59. * Returns non-zero value if the queue is empty.
  60. */
  61. int qmgr_stat_empty(unsigned int queue)
  62. {
  63. BUG_ON(queue >= HALF_QUEUES);
  64. return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
  65. }
  66. /**
  67. * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
  68. * @queue: queue number
  69. *
  70. * Returns non-zero value if the queue is below low watermark.
  71. */
  72. int qmgr_stat_below_low_watermark(unsigned int queue)
  73. {
  74. if (queue >= HALF_QUEUES)
  75. return (__raw_readl(&qmgr_regs->statne_h) >>
  76. (queue - HALF_QUEUES)) & 0x01;
  77. return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
  78. }
  79. /**
  80. * qmgr_stat_full() - checks if a hardware queue is full
  81. * @queue: queue number
  82. *
  83. * Returns non-zero value if the queue is full.
  84. */
  85. int qmgr_stat_full(unsigned int queue)
  86. {
  87. if (queue >= HALF_QUEUES)
  88. return (__raw_readl(&qmgr_regs->statf_h) >>
  89. (queue - HALF_QUEUES)) & 0x01;
  90. return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
  91. }
  92. /**
  93. * qmgr_stat_overflow() - checks if a hardware queue experienced overflow
  94. * @queue: queue number
  95. *
  96. * Returns non-zero value if the queue experienced overflow.
  97. */
  98. int qmgr_stat_overflow(unsigned int queue)
  99. {
  100. return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
  101. }
  102. void qmgr_set_irq(unsigned int queue, int src,
  103. void (*handler)(void *pdev), void *pdev)
  104. {
  105. unsigned long flags;
  106. spin_lock_irqsave(&qmgr_lock, flags);
  107. if (queue < HALF_QUEUES) {
  108. u32 __iomem *reg;
  109. int bit;
  110. BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL);
  111. reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
  112. bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
  113. __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit),
  114. reg);
  115. } else
  116. /* IRQ source for queues 32-63 is fixed */
  117. BUG_ON(src != QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY);
  118. irq_handlers[queue] = handler;
  119. irq_pdevs[queue] = pdev;
  120. spin_unlock_irqrestore(&qmgr_lock, flags);
  121. }
  122. static irqreturn_t qmgr_irq1_a0(int irq, void *pdev)
  123. {
  124. int i, ret = 0;
  125. u32 en_bitmap, src, stat;
  126. /* ACK - it may clear any bits so don't rely on it */
  127. __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);
  128. en_bitmap = __raw_readl(&qmgr_regs->irqen[0]);
  129. while (en_bitmap) {
  130. i = __fls(en_bitmap); /* number of the last "low" queue */
  131. en_bitmap &= ~BIT(i);
  132. src = __raw_readl(&qmgr_regs->irqsrc[i >> 3]);
  133. stat = __raw_readl(&qmgr_regs->stat1[i >> 3]);
  134. if (src & 4) /* the IRQ condition is inverted */
  135. stat = ~stat;
  136. if (stat & BIT(src & 3)) {
  137. irq_handlers[i](irq_pdevs[i]);
  138. ret = IRQ_HANDLED;
  139. }
  140. }
  141. return ret;
  142. }
  143. static irqreturn_t qmgr_irq2_a0(int irq, void *pdev)
  144. {
  145. int i, ret = 0;
  146. u32 req_bitmap;
  147. /* ACK - it may clear any bits so don't rely on it */
  148. __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]);
  149. req_bitmap = __raw_readl(&qmgr_regs->irqen[1]) &
  150. __raw_readl(&qmgr_regs->statne_h);
  151. while (req_bitmap) {
  152. i = __fls(req_bitmap); /* number of the last "high" queue */
  153. req_bitmap &= ~BIT(i);
  154. irq_handlers[HALF_QUEUES + i](irq_pdevs[HALF_QUEUES + i]);
  155. ret = IRQ_HANDLED;
  156. }
  157. return ret;
  158. }
  159. static irqreturn_t qmgr_irq(int irq, void *pdev)
  160. {
  161. int i, half = (irq == qmgr_irq_1 ? 0 : 1);
  162. u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);
  163. if (!req_bitmap)
  164. return 0;
  165. __raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */
  166. while (req_bitmap) {
  167. i = __fls(req_bitmap); /* number of the last queue */
  168. req_bitmap &= ~BIT(i);
  169. i += half * HALF_QUEUES;
  170. irq_handlers[i](irq_pdevs[i]);
  171. }
  172. return IRQ_HANDLED;
  173. }
  174. void qmgr_enable_irq(unsigned int queue)
  175. {
  176. unsigned long flags;
  177. int half = queue / 32;
  178. u32 mask = 1 << (queue & (HALF_QUEUES - 1));
  179. spin_lock_irqsave(&qmgr_lock, flags);
  180. __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask,
  181. &qmgr_regs->irqen[half]);
  182. spin_unlock_irqrestore(&qmgr_lock, flags);
  183. }
  184. void qmgr_disable_irq(unsigned int queue)
  185. {
  186. unsigned long flags;
  187. int half = queue / 32;
  188. u32 mask = 1 << (queue & (HALF_QUEUES - 1));
  189. spin_lock_irqsave(&qmgr_lock, flags);
  190. __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask,
  191. &qmgr_regs->irqen[half]);
  192. __raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */
  193. spin_unlock_irqrestore(&qmgr_lock, flags);
  194. }
  195. static inline void shift_mask(u32 *mask)
  196. {
  197. mask[3] = mask[3] << 1 | mask[2] >> 31;
  198. mask[2] = mask[2] << 1 | mask[1] >> 31;
  199. mask[1] = mask[1] << 1 | mask[0] >> 31;
  200. mask[0] <<= 1;
  201. }
  202. #if DEBUG_QMGR
  203. int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
  204. unsigned int nearly_empty_watermark,
  205. unsigned int nearly_full_watermark,
  206. const char *desc_format, const char* name)
  207. #else
  208. int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
  209. unsigned int nearly_empty_watermark,
  210. unsigned int nearly_full_watermark)
  211. #endif
  212. {
  213. u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
  214. int err;
  215. BUG_ON(queue >= QUEUES);
  216. if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
  217. return -EINVAL;
  218. switch (len) {
  219. case 16:
  220. cfg = 0 << 24;
  221. mask[0] = 0x1;
  222. break;
  223. case 32:
  224. cfg = 1 << 24;
  225. mask[0] = 0x3;
  226. break;
  227. case 64:
  228. cfg = 2 << 24;
  229. mask[0] = 0xF;
  230. break;
  231. case 128:
  232. cfg = 3 << 24;
  233. mask[0] = 0xFF;
  234. break;
  235. default:
  236. return -EINVAL;
  237. }
  238. cfg |= nearly_empty_watermark << 26;
  239. cfg |= nearly_full_watermark << 29;
  240. len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
  241. mask[1] = mask[2] = mask[3] = 0;
  242. if (!try_module_get(THIS_MODULE))
  243. return -ENODEV;
  244. spin_lock_irq(&qmgr_lock);
  245. if (__raw_readl(&qmgr_regs->sram[queue])) {
  246. err = -EBUSY;
  247. goto err;
  248. }
  249. while (1) {
  250. if (!(used_sram_bitmap[0] & mask[0]) &&
  251. !(used_sram_bitmap[1] & mask[1]) &&
  252. !(used_sram_bitmap[2] & mask[2]) &&
  253. !(used_sram_bitmap[3] & mask[3]))
  254. break; /* found free space */
  255. addr++;
  256. shift_mask(mask);
  257. if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
  258. printk(KERN_ERR "qmgr: no free SRAM space for"
  259. " queue %i\n", queue);
  260. err = -ENOMEM;
  261. goto err;
  262. }
  263. }
  264. used_sram_bitmap[0] |= mask[0];
  265. used_sram_bitmap[1] |= mask[1];
  266. used_sram_bitmap[2] |= mask[2];
  267. used_sram_bitmap[3] |= mask[3];
  268. __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
  269. #if DEBUG_QMGR
  270. snprintf(qmgr_queue_descs[queue], sizeof(qmgr_queue_descs[0]),
  271. desc_format, name);
  272. printk(KERN_DEBUG "qmgr: requested queue %s(%i) addr = 0x%02X\n",
  273. qmgr_queue_descs[queue], queue, addr);
  274. #endif
  275. spin_unlock_irq(&qmgr_lock);
  276. return 0;
  277. err:
  278. spin_unlock_irq(&qmgr_lock);
  279. module_put(THIS_MODULE);
  280. return err;
  281. }
  282. void qmgr_release_queue(unsigned int queue)
  283. {
  284. u32 cfg, addr, mask[4];
  285. BUG_ON(queue >= QUEUES); /* not in valid range */
  286. spin_lock_irq(&qmgr_lock);
  287. cfg = __raw_readl(&qmgr_regs->sram[queue]);
  288. addr = (cfg >> 14) & 0xFF;
  289. BUG_ON(!addr); /* not requested */
  290. switch ((cfg >> 24) & 3) {
  291. case 0: mask[0] = 0x1; break;
  292. case 1: mask[0] = 0x3; break;
  293. case 2: mask[0] = 0xF; break;
  294. case 3: mask[0] = 0xFF; break;
  295. }
  296. mask[1] = mask[2] = mask[3] = 0;
  297. while (addr--)
  298. shift_mask(mask);
  299. #if DEBUG_QMGR
  300. printk(KERN_DEBUG "qmgr: releasing queue %s(%i)\n",
  301. qmgr_queue_descs[queue], queue);
  302. qmgr_queue_descs[queue][0] = '\x0';
  303. #endif
  304. while ((addr = qmgr_get_entry(queue)))
  305. printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
  306. queue, addr);
  307. __raw_writel(0, &qmgr_regs->sram[queue]);
  308. used_sram_bitmap[0] &= ~mask[0];
  309. used_sram_bitmap[1] &= ~mask[1];
  310. used_sram_bitmap[2] &= ~mask[2];
  311. used_sram_bitmap[3] &= ~mask[3];
  312. irq_handlers[queue] = NULL; /* catch IRQ bugs */
  313. spin_unlock_irq(&qmgr_lock);
  314. module_put(THIS_MODULE);
  315. }
  316. static int ixp4xx_qmgr_probe(struct platform_device *pdev)
  317. {
  318. int i, err;
  319. irq_handler_t handler1, handler2;
  320. struct device *dev = &pdev->dev;
  321. struct resource *res;
  322. int irq1, irq2;
  323. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  324. if (!res)
  325. return -ENODEV;
  326. qmgr_regs = devm_ioremap_resource(dev, res);
  327. if (IS_ERR(qmgr_regs))
  328. return PTR_ERR(qmgr_regs);
  329. irq1 = platform_get_irq(pdev, 0);
  330. if (irq1 <= 0)
  331. return irq1 ? irq1 : -EINVAL;
  332. qmgr_irq_1 = irq1;
  333. irq2 = platform_get_irq(pdev, 1);
  334. if (irq2 <= 0)
  335. return irq2 ? irq2 : -EINVAL;
  336. qmgr_irq_2 = irq2;
  337. /* reset qmgr registers */
  338. for (i = 0; i < 4; i++) {
  339. __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
  340. __raw_writel(0, &qmgr_regs->irqsrc[i]);
  341. }
  342. for (i = 0; i < 2; i++) {
  343. __raw_writel(0, &qmgr_regs->stat2[i]);
  344. __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
  345. __raw_writel(0, &qmgr_regs->irqen[i]);
  346. }
  347. __raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h);
  348. __raw_writel(0, &qmgr_regs->statf_h);
  349. for (i = 0; i < QUEUES; i++)
  350. __raw_writel(0, &qmgr_regs->sram[i]);
  351. if (cpu_is_ixp42x_rev_a0()) {
  352. handler1 = qmgr_irq1_a0;
  353. handler2 = qmgr_irq2_a0;
  354. } else
  355. handler1 = handler2 = qmgr_irq;
  356. err = devm_request_irq(dev, irq1, handler1, 0, "IXP4xx Queue Manager",
  357. NULL);
  358. if (err) {
  359. dev_err(dev, "failed to request IRQ%i (%i)\n",
  360. irq1, err);
  361. return err;
  362. }
  363. err = devm_request_irq(dev, irq2, handler2, 0, "IXP4xx Queue Manager",
  364. NULL);
  365. if (err) {
  366. dev_err(dev, "failed to request IRQ%i (%i)\n",
  367. irq2, err);
  368. return err;
  369. }
  370. used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
  371. spin_lock_init(&qmgr_lock);
  372. dev_info(dev, "IXP4xx Queue Manager initialized.\n");
  373. return 0;
  374. }
  375. static int ixp4xx_qmgr_remove(struct platform_device *pdev)
  376. {
  377. synchronize_irq(qmgr_irq_1);
  378. synchronize_irq(qmgr_irq_2);
  379. return 0;
  380. }
  381. static const struct of_device_id ixp4xx_qmgr_of_match[] = {
  382. {
  383. .compatible = "intel,ixp4xx-ahb-queue-manager",
  384. },
  385. {},
  386. };
  387. static struct platform_driver ixp4xx_qmgr_driver = {
  388. .driver = {
  389. .name = "ixp4xx-qmgr",
  390. .of_match_table = of_match_ptr(ixp4xx_qmgr_of_match),
  391. },
  392. .probe = ixp4xx_qmgr_probe,
  393. .remove = ixp4xx_qmgr_remove,
  394. };
  395. module_platform_driver(ixp4xx_qmgr_driver);
  396. MODULE_LICENSE("GPL v2");
  397. MODULE_AUTHOR("Krzysztof Halasa");
  398. EXPORT_SYMBOL(qmgr_put_entry);
  399. EXPORT_SYMBOL(qmgr_get_entry);
  400. EXPORT_SYMBOL(qmgr_stat_empty);
  401. EXPORT_SYMBOL(qmgr_stat_below_low_watermark);
  402. EXPORT_SYMBOL(qmgr_stat_full);
  403. EXPORT_SYMBOL(qmgr_stat_overflow);
  404. EXPORT_SYMBOL(qmgr_set_irq);
  405. EXPORT_SYMBOL(qmgr_enable_irq);
  406. EXPORT_SYMBOL(qmgr_disable_irq);
  407. #if DEBUG_QMGR
  408. EXPORT_SYMBOL(qmgr_queue_descs);
  409. EXPORT_SYMBOL(qmgr_request_queue);
  410. #else
  411. EXPORT_SYMBOL(__qmgr_request_queue);
  412. #endif
  413. EXPORT_SYMBOL(qmgr_release_queue);