reset-zynq.c 3.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015, National Instruments Corp.
  4. *
  5. * Xilinx Zynq Reset controller driver
  6. *
  7. * Author: Moritz Fischer <moritz.fischer@ettus.com>
  8. */
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/init.h>
  12. #include <linux/mfd/syscon.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/reset-controller.h>
  16. #include <linux/regmap.h>
  17. #include <linux/types.h>
  18. struct zynq_reset_data {
  19. struct regmap *slcr;
  20. struct reset_controller_dev rcdev;
  21. u32 offset;
  22. };
  23. #define to_zynq_reset_data(p) \
  24. container_of((p), struct zynq_reset_data, rcdev)
  25. static int zynq_reset_assert(struct reset_controller_dev *rcdev,
  26. unsigned long id)
  27. {
  28. struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
  29. int bank = id / BITS_PER_LONG;
  30. int offset = id % BITS_PER_LONG;
  31. pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
  32. bank, offset);
  33. return regmap_update_bits(priv->slcr,
  34. priv->offset + (bank * 4),
  35. BIT(offset),
  36. BIT(offset));
  37. }
  38. static int zynq_reset_deassert(struct reset_controller_dev *rcdev,
  39. unsigned long id)
  40. {
  41. struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
  42. int bank = id / BITS_PER_LONG;
  43. int offset = id % BITS_PER_LONG;
  44. pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
  45. bank, offset);
  46. return regmap_update_bits(priv->slcr,
  47. priv->offset + (bank * 4),
  48. BIT(offset),
  49. ~BIT(offset));
  50. }
  51. static int zynq_reset_status(struct reset_controller_dev *rcdev,
  52. unsigned long id)
  53. {
  54. struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
  55. int bank = id / BITS_PER_LONG;
  56. int offset = id % BITS_PER_LONG;
  57. int ret;
  58. u32 reg;
  59. pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
  60. bank, offset);
  61. ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg);
  62. if (ret)
  63. return ret;
  64. return !!(reg & BIT(offset));
  65. }
  66. static const struct reset_control_ops zynq_reset_ops = {
  67. .assert = zynq_reset_assert,
  68. .deassert = zynq_reset_deassert,
  69. .status = zynq_reset_status,
  70. };
  71. static int zynq_reset_probe(struct platform_device *pdev)
  72. {
  73. struct resource *res;
  74. struct zynq_reset_data *priv;
  75. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  76. if (!priv)
  77. return -ENOMEM;
  78. platform_set_drvdata(pdev, priv);
  79. priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  80. "syscon");
  81. if (IS_ERR(priv->slcr)) {
  82. dev_err(&pdev->dev, "unable to get zynq-slcr regmap");
  83. return PTR_ERR(priv->slcr);
  84. }
  85. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  86. if (!res) {
  87. dev_err(&pdev->dev, "missing IO resource\n");
  88. return -ENODEV;
  89. }
  90. priv->offset = res->start;
  91. priv->rcdev.owner = THIS_MODULE;
  92. priv->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_LONG;
  93. priv->rcdev.ops = &zynq_reset_ops;
  94. priv->rcdev.of_node = pdev->dev.of_node;
  95. return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
  96. }
  97. static const struct of_device_id zynq_reset_dt_ids[] = {
  98. { .compatible = "xlnx,zynq-reset", },
  99. { /* sentinel */ },
  100. };
  101. static struct platform_driver zynq_reset_driver = {
  102. .probe = zynq_reset_probe,
  103. .driver = {
  104. .name = KBUILD_MODNAME,
  105. .of_match_table = zynq_reset_dt_ids,
  106. },
  107. };
  108. builtin_platform_driver(zynq_reset_driver);