reset-imx7.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017, Impinj, Inc.
  4. *
  5. * i.MX7 System Reset Controller (SRC) driver
  6. *
  7. * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
  8. */
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/reset-controller.h>
  14. #include <linux/regmap.h>
  15. #include <dt-bindings/reset/imx7-reset.h>
  16. #include <dt-bindings/reset/imx8mq-reset.h>
  17. #include <dt-bindings/reset/imx8mp-reset.h>
  18. struct imx7_src_signal {
  19. unsigned int offset, bit;
  20. };
  21. struct imx7_src_variant {
  22. const struct imx7_src_signal *signals;
  23. unsigned int signals_num;
  24. struct reset_control_ops ops;
  25. };
  26. struct imx7_src {
  27. struct reset_controller_dev rcdev;
  28. struct regmap *regmap;
  29. const struct imx7_src_signal *signals;
  30. };
  31. enum imx7_src_registers {
  32. SRC_A7RCR0 = 0x0004,
  33. SRC_M4RCR = 0x000c,
  34. SRC_ERCR = 0x0014,
  35. SRC_HSICPHY_RCR = 0x001c,
  36. SRC_USBOPHY1_RCR = 0x0020,
  37. SRC_USBOPHY2_RCR = 0x0024,
  38. SRC_MIPIPHY_RCR = 0x0028,
  39. SRC_PCIEPHY_RCR = 0x002c,
  40. SRC_DDRC_RCR = 0x1000,
  41. };
  42. static int imx7_reset_update(struct imx7_src *imx7src,
  43. unsigned long id, unsigned int value)
  44. {
  45. const struct imx7_src_signal *signal = &imx7src->signals[id];
  46. return regmap_update_bits(imx7src->regmap,
  47. signal->offset, signal->bit, value);
  48. }
  49. static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
  50. [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
  51. [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
  52. [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
  53. [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
  54. [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
  55. [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
  56. [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
  57. [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
  58. [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
  59. [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
  60. [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
  61. [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
  62. [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) },
  63. [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) },
  64. [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) },
  65. [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) },
  66. [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) },
  67. [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) },
  68. [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) },
  69. [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) },
  70. [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
  71. [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
  72. [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
  73. [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
  74. [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) },
  75. [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
  76. };
  77. static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev)
  78. {
  79. return container_of(rcdev, struct imx7_src, rcdev);
  80. }
  81. static int imx7_reset_set(struct reset_controller_dev *rcdev,
  82. unsigned long id, bool assert)
  83. {
  84. struct imx7_src *imx7src = to_imx7_src(rcdev);
  85. const unsigned int bit = imx7src->signals[id].bit;
  86. unsigned int value = assert ? bit : 0;
  87. switch (id) {
  88. case IMX7_RESET_PCIEPHY:
  89. /*
  90. * wait for more than 10us to release phy g_rst and
  91. * btnrst
  92. */
  93. if (!assert)
  94. udelay(10);
  95. break;
  96. case IMX7_RESET_PCIE_CTRL_APPS_EN:
  97. value = assert ? 0 : bit;
  98. break;
  99. }
  100. return imx7_reset_update(imx7src, id, value);
  101. }
  102. static int imx7_reset_assert(struct reset_controller_dev *rcdev,
  103. unsigned long id)
  104. {
  105. return imx7_reset_set(rcdev, id, true);
  106. }
  107. static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
  108. unsigned long id)
  109. {
  110. return imx7_reset_set(rcdev, id, false);
  111. }
  112. static const struct imx7_src_variant variant_imx7 = {
  113. .signals = imx7_src_signals,
  114. .signals_num = ARRAY_SIZE(imx7_src_signals),
  115. .ops = {
  116. .assert = imx7_reset_assert,
  117. .deassert = imx7_reset_deassert,
  118. },
  119. };
  120. enum imx8mq_src_registers {
  121. SRC_A53RCR0 = 0x0004,
  122. SRC_HDMI_RCR = 0x0030,
  123. SRC_DISP_RCR = 0x0034,
  124. SRC_GPU_RCR = 0x0040,
  125. SRC_VPU_RCR = 0x0044,
  126. SRC_PCIE2_RCR = 0x0048,
  127. SRC_MIPIPHY1_RCR = 0x004c,
  128. SRC_MIPIPHY2_RCR = 0x0050,
  129. SRC_DDRC2_RCR = 0x1004,
  130. };
  131. enum imx8mp_src_registers {
  132. SRC_SUPERMIX_RCR = 0x0018,
  133. SRC_AUDIOMIX_RCR = 0x001c,
  134. SRC_MLMIX_RCR = 0x0028,
  135. SRC_GPU2D_RCR = 0x0038,
  136. SRC_GPU3D_RCR = 0x003c,
  137. SRC_VPU_G1_RCR = 0x0048,
  138. SRC_VPU_G2_RCR = 0x004c,
  139. SRC_VPUVC8KE_RCR = 0x0050,
  140. SRC_NOC_RCR = 0x0054,
  141. };
  142. static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
  143. [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
  144. [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
  145. [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
  146. [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
  147. [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
  148. [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
  149. [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
  150. [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
  151. [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
  152. [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
  153. [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
  154. [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
  155. [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
  156. [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
  157. [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
  158. [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
  159. [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
  160. [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
  161. [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
  162. [IMX8MQ_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
  163. [IMX8MQ_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
  164. [IMX8MQ_RESET_M4_ENABLE] = { SRC_M4RCR, BIT(3) },
  165. [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
  166. [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
  167. [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
  168. [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
  169. [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
  170. [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
  171. [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
  172. [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
  173. BIT(2) | BIT(1) },
  174. [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
  175. [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
  176. [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
  177. [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
  178. [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
  179. [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
  180. [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
  181. [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
  182. BIT(2) | BIT(1) },
  183. [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
  184. [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
  185. [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
  186. [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
  187. [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
  188. [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
  189. [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
  190. [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
  191. [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
  192. [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
  193. [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
  194. [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
  195. [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
  196. [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
  197. [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
  198. };
  199. static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
  200. unsigned long id, bool assert)
  201. {
  202. struct imx7_src *imx7src = to_imx7_src(rcdev);
  203. const unsigned int bit = imx7src->signals[id].bit;
  204. unsigned int value = assert ? bit : 0;
  205. switch (id) {
  206. case IMX8MQ_RESET_PCIEPHY:
  207. case IMX8MQ_RESET_PCIEPHY2:
  208. /*
  209. * wait for more than 10us to release phy g_rst and
  210. * btnrst
  211. */
  212. if (!assert)
  213. udelay(10);
  214. break;
  215. case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
  216. case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:
  217. case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:
  218. case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:
  219. case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N:
  220. case IMX8MQ_RESET_MIPI_DSI_RESET_N:
  221. case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N:
  222. case IMX8MQ_RESET_M4_ENABLE:
  223. value = assert ? 0 : bit;
  224. break;
  225. }
  226. return imx7_reset_update(imx7src, id, value);
  227. }
  228. static int imx8mq_reset_assert(struct reset_controller_dev *rcdev,
  229. unsigned long id)
  230. {
  231. return imx8mq_reset_set(rcdev, id, true);
  232. }
  233. static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev,
  234. unsigned long id)
  235. {
  236. return imx8mq_reset_set(rcdev, id, false);
  237. }
  238. static const struct imx7_src_variant variant_imx8mq = {
  239. .signals = imx8mq_src_signals,
  240. .signals_num = ARRAY_SIZE(imx8mq_src_signals),
  241. .ops = {
  242. .assert = imx8mq_reset_assert,
  243. .deassert = imx8mq_reset_deassert,
  244. },
  245. };
  246. static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
  247. [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
  248. [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
  249. [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
  250. [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
  251. [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
  252. [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
  253. [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
  254. [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
  255. [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
  256. [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
  257. [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
  258. [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
  259. [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
  260. [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
  261. [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
  262. [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
  263. [IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
  264. [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
  265. [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
  266. [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
  267. [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
  268. [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
  269. [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
  270. [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
  271. [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
  272. [IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
  273. [IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
  274. [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
  275. [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
  276. [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
  277. [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
  278. [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
  279. [IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
  280. [IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
  281. [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
  282. [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
  283. [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
  284. [IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) },
  285. };
  286. static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
  287. unsigned long id, bool assert)
  288. {
  289. struct imx7_src *imx7src = to_imx7_src(rcdev);
  290. const unsigned int bit = imx7src->signals[id].bit;
  291. unsigned int value = assert ? bit : 0;
  292. switch (id) {
  293. case IMX8MP_RESET_PCIEPHY:
  294. /*
  295. * wait for more than 10us to release phy g_rst and
  296. * btnrst
  297. */
  298. if (!assert)
  299. udelay(10);
  300. break;
  301. case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
  302. value = assert ? 0 : bit;
  303. break;
  304. }
  305. return imx7_reset_update(imx7src, id, value);
  306. }
  307. static int imx8mp_reset_assert(struct reset_controller_dev *rcdev,
  308. unsigned long id)
  309. {
  310. return imx8mp_reset_set(rcdev, id, true);
  311. }
  312. static int imx8mp_reset_deassert(struct reset_controller_dev *rcdev,
  313. unsigned long id)
  314. {
  315. return imx8mp_reset_set(rcdev, id, false);
  316. }
  317. static const struct imx7_src_variant variant_imx8mp = {
  318. .signals = imx8mp_src_signals,
  319. .signals_num = ARRAY_SIZE(imx8mp_src_signals),
  320. .ops = {
  321. .assert = imx8mp_reset_assert,
  322. .deassert = imx8mp_reset_deassert,
  323. },
  324. };
  325. static int imx7_reset_probe(struct platform_device *pdev)
  326. {
  327. struct imx7_src *imx7src;
  328. struct device *dev = &pdev->dev;
  329. struct regmap_config config = { .name = "src" };
  330. const struct imx7_src_variant *variant = of_device_get_match_data(dev);
  331. imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
  332. if (!imx7src)
  333. return -ENOMEM;
  334. imx7src->signals = variant->signals;
  335. imx7src->regmap = syscon_node_to_regmap(dev->of_node);
  336. if (IS_ERR(imx7src->regmap)) {
  337. dev_err(dev, "Unable to get imx7-src regmap");
  338. return PTR_ERR(imx7src->regmap);
  339. }
  340. regmap_attach_dev(dev, imx7src->regmap, &config);
  341. imx7src->rcdev.owner = THIS_MODULE;
  342. imx7src->rcdev.nr_resets = variant->signals_num;
  343. imx7src->rcdev.ops = &variant->ops;
  344. imx7src->rcdev.of_node = dev->of_node;
  345. return devm_reset_controller_register(dev, &imx7src->rcdev);
  346. }
  347. static const struct of_device_id imx7_reset_dt_ids[] = {
  348. { .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
  349. { .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
  350. { .compatible = "fsl,imx8mp-src", .data = &variant_imx8mp },
  351. { /* sentinel */ },
  352. };
  353. MODULE_DEVICE_TABLE(of, imx7_reset_dt_ids);
  354. static struct platform_driver imx7_reset_driver = {
  355. .probe = imx7_reset_probe,
  356. .driver = {
  357. .name = KBUILD_MODNAME,
  358. .of_match_table = imx7_reset_dt_ids,
  359. },
  360. };
  361. module_platform_driver(imx7_reset_driver);
  362. MODULE_AUTHOR("Andrey Smirnov <andrew.smirnov@gmail.com>");
  363. MODULE_DESCRIPTION("NXP i.MX7 reset driver");
  364. MODULE_LICENSE("GPL v2");