ti_k3_r5_remoteproc.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * TI K3 R5F (MCU) Remote Processor driver
  4. *
  5. * Copyright (C) 2017-2020 Texas Instruments Incorporated - https://www.ti.com/
  6. * Suman Anna <s-anna@ti.com>
  7. */
  8. #include <linux/dma-mapping.h>
  9. #include <linux/err.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/kernel.h>
  12. #include <linux/mailbox_client.h>
  13. #include <linux/module.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_device.h>
  16. #include <linux/of_reserved_mem.h>
  17. #include <linux/omap-mailbox.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/remoteproc.h>
  21. #include <linux/reset.h>
  22. #include <linux/slab.h>
  23. #include "omap_remoteproc.h"
  24. #include "remoteproc_internal.h"
  25. #include "ti_sci_proc.h"
  26. /* This address can either be for ATCM or BTCM with the other at address 0x0 */
  27. #define K3_R5_TCM_DEV_ADDR 0x41010000
  28. /* R5 TI-SCI Processor Configuration Flags */
  29. #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
  30. #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
  31. #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
  32. #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
  33. #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
  34. #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
  35. #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
  36. #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
  37. /* R5 TI-SCI Processor Control Flags */
  38. #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
  39. /* R5 TI-SCI Processor Status Flags */
  40. #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
  41. #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
  42. #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
  43. #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
  44. /**
  45. * struct k3_r5_mem - internal memory structure
  46. * @cpu_addr: MPU virtual address of the memory region
  47. * @bus_addr: Bus address used to access the memory region
  48. * @dev_addr: Device address from remoteproc view
  49. * @size: Size of the memory region
  50. */
  51. struct k3_r5_mem {
  52. void __iomem *cpu_addr;
  53. phys_addr_t bus_addr;
  54. u32 dev_addr;
  55. size_t size;
  56. };
  57. enum cluster_mode {
  58. CLUSTER_MODE_SPLIT = 0,
  59. CLUSTER_MODE_LOCKSTEP,
  60. };
  61. /**
  62. * struct k3_r5_cluster - K3 R5F Cluster structure
  63. * @dev: cached device pointer
  64. * @mode: Mode to configure the Cluster - Split or LockStep
  65. * @cores: list of R5 cores within the cluster
  66. */
  67. struct k3_r5_cluster {
  68. struct device *dev;
  69. enum cluster_mode mode;
  70. struct list_head cores;
  71. };
  72. /**
  73. * struct k3_r5_core - K3 R5 core structure
  74. * @elem: linked list item
  75. * @dev: cached device pointer
  76. * @rproc: rproc handle representing this core
  77. * @mem: internal memory regions data
  78. * @sram: on-chip SRAM memory regions data
  79. * @num_mems: number of internal memory regions
  80. * @num_sram: number of on-chip SRAM memory regions
  81. * @reset: reset control handle
  82. * @tsp: TI-SCI processor control handle
  83. * @ti_sci: TI-SCI handle
  84. * @ti_sci_id: TI-SCI device identifier
  85. * @atcm_enable: flag to control ATCM enablement
  86. * @btcm_enable: flag to control BTCM enablement
  87. * @loczrama: flag to dictate which TCM is at device address 0x0
  88. */
  89. struct k3_r5_core {
  90. struct list_head elem;
  91. struct device *dev;
  92. struct rproc *rproc;
  93. struct k3_r5_mem *mem;
  94. struct k3_r5_mem *sram;
  95. int num_mems;
  96. int num_sram;
  97. struct reset_control *reset;
  98. struct ti_sci_proc *tsp;
  99. const struct ti_sci_handle *ti_sci;
  100. u32 ti_sci_id;
  101. u32 atcm_enable;
  102. u32 btcm_enable;
  103. u32 loczrama;
  104. };
  105. /**
  106. * struct k3_r5_rproc - K3 remote processor state
  107. * @dev: cached device pointer
  108. * @cluster: cached pointer to parent cluster structure
  109. * @mbox: mailbox channel handle
  110. * @client: mailbox client to request the mailbox channel
  111. * @rproc: rproc handle
  112. * @core: cached pointer to r5 core structure being used
  113. * @rmem: reserved memory regions data
  114. * @num_rmems: number of reserved memory regions
  115. */
  116. struct k3_r5_rproc {
  117. struct device *dev;
  118. struct k3_r5_cluster *cluster;
  119. struct mbox_chan *mbox;
  120. struct mbox_client client;
  121. struct rproc *rproc;
  122. struct k3_r5_core *core;
  123. struct k3_r5_mem *rmem;
  124. int num_rmems;
  125. };
  126. /**
  127. * k3_r5_rproc_mbox_callback() - inbound mailbox message handler
  128. * @client: mailbox client pointer used for requesting the mailbox channel
  129. * @data: mailbox payload
  130. *
  131. * This handler is invoked by the OMAP mailbox driver whenever a mailbox
  132. * message is received. Usually, the mailbox payload simply contains
  133. * the index of the virtqueue that is kicked by the remote processor,
  134. * and we let remoteproc core handle it.
  135. *
  136. * In addition to virtqueue indices, we also have some out-of-band values
  137. * that indicate different events. Those values are deliberately very
  138. * large so they don't coincide with virtqueue indices.
  139. */
  140. static void k3_r5_rproc_mbox_callback(struct mbox_client *client, void *data)
  141. {
  142. struct k3_r5_rproc *kproc = container_of(client, struct k3_r5_rproc,
  143. client);
  144. struct device *dev = kproc->rproc->dev.parent;
  145. const char *name = kproc->rproc->name;
  146. u32 msg = omap_mbox_message(data);
  147. dev_dbg(dev, "mbox msg: 0x%x\n", msg);
  148. switch (msg) {
  149. case RP_MBOX_CRASH:
  150. /*
  151. * remoteproc detected an exception, but error recovery is not
  152. * supported. So, just log this for now
  153. */
  154. dev_err(dev, "K3 R5F rproc %s crashed\n", name);
  155. break;
  156. case RP_MBOX_ECHO_REPLY:
  157. dev_info(dev, "received echo reply from %s\n", name);
  158. break;
  159. default:
  160. /* silently handle all other valid messages */
  161. if (msg >= RP_MBOX_READY && msg < RP_MBOX_END_MSG)
  162. return;
  163. if (msg > kproc->rproc->max_notifyid) {
  164. dev_dbg(dev, "dropping unknown message 0x%x", msg);
  165. return;
  166. }
  167. /* msg contains the index of the triggered vring */
  168. if (rproc_vq_interrupt(kproc->rproc, msg) == IRQ_NONE)
  169. dev_dbg(dev, "no message was found in vqid %d\n", msg);
  170. }
  171. }
  172. /* kick a virtqueue */
  173. static void k3_r5_rproc_kick(struct rproc *rproc, int vqid)
  174. {
  175. struct k3_r5_rproc *kproc = rproc->priv;
  176. struct device *dev = rproc->dev.parent;
  177. mbox_msg_t msg = (mbox_msg_t)vqid;
  178. int ret;
  179. /* send the index of the triggered virtqueue in the mailbox payload */
  180. ret = mbox_send_message(kproc->mbox, (void *)msg);
  181. if (ret < 0)
  182. dev_err(dev, "failed to send mailbox message, status = %d\n",
  183. ret);
  184. }
  185. static int k3_r5_split_reset(struct k3_r5_core *core)
  186. {
  187. int ret;
  188. ret = reset_control_assert(core->reset);
  189. if (ret) {
  190. dev_err(core->dev, "local-reset assert failed, ret = %d\n",
  191. ret);
  192. return ret;
  193. }
  194. ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
  195. core->ti_sci_id);
  196. if (ret) {
  197. dev_err(core->dev, "module-reset assert failed, ret = %d\n",
  198. ret);
  199. if (reset_control_deassert(core->reset))
  200. dev_warn(core->dev, "local-reset deassert back failed\n");
  201. }
  202. return ret;
  203. }
  204. static int k3_r5_split_release(struct k3_r5_core *core)
  205. {
  206. int ret;
  207. ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,
  208. core->ti_sci_id);
  209. if (ret) {
  210. dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
  211. ret);
  212. return ret;
  213. }
  214. ret = reset_control_deassert(core->reset);
  215. if (ret) {
  216. dev_err(core->dev, "local-reset deassert failed, ret = %d\n",
  217. ret);
  218. if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
  219. core->ti_sci_id))
  220. dev_warn(core->dev, "module-reset assert back failed\n");
  221. }
  222. return ret;
  223. }
  224. static int k3_r5_lockstep_reset(struct k3_r5_cluster *cluster)
  225. {
  226. struct k3_r5_core *core;
  227. int ret;
  228. /* assert local reset on all applicable cores */
  229. list_for_each_entry(core, &cluster->cores, elem) {
  230. ret = reset_control_assert(core->reset);
  231. if (ret) {
  232. dev_err(core->dev, "local-reset assert failed, ret = %d\n",
  233. ret);
  234. core = list_prev_entry(core, elem);
  235. goto unroll_local_reset;
  236. }
  237. }
  238. /* disable PSC modules on all applicable cores */
  239. list_for_each_entry(core, &cluster->cores, elem) {
  240. ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
  241. core->ti_sci_id);
  242. if (ret) {
  243. dev_err(core->dev, "module-reset assert failed, ret = %d\n",
  244. ret);
  245. goto unroll_module_reset;
  246. }
  247. }
  248. return 0;
  249. unroll_module_reset:
  250. list_for_each_entry_continue_reverse(core, &cluster->cores, elem) {
  251. if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
  252. core->ti_sci_id))
  253. dev_warn(core->dev, "module-reset assert back failed\n");
  254. }
  255. core = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
  256. unroll_local_reset:
  257. list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
  258. if (reset_control_deassert(core->reset))
  259. dev_warn(core->dev, "local-reset deassert back failed\n");
  260. }
  261. return ret;
  262. }
  263. static int k3_r5_lockstep_release(struct k3_r5_cluster *cluster)
  264. {
  265. struct k3_r5_core *core;
  266. int ret;
  267. /* enable PSC modules on all applicable cores */
  268. list_for_each_entry_reverse(core, &cluster->cores, elem) {
  269. ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,
  270. core->ti_sci_id);
  271. if (ret) {
  272. dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
  273. ret);
  274. core = list_next_entry(core, elem);
  275. goto unroll_module_reset;
  276. }
  277. }
  278. /* deassert local reset on all applicable cores */
  279. list_for_each_entry_reverse(core, &cluster->cores, elem) {
  280. ret = reset_control_deassert(core->reset);
  281. if (ret) {
  282. dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
  283. ret);
  284. goto unroll_local_reset;
  285. }
  286. }
  287. return 0;
  288. unroll_local_reset:
  289. list_for_each_entry_continue(core, &cluster->cores, elem) {
  290. if (reset_control_assert(core->reset))
  291. dev_warn(core->dev, "local-reset assert back failed\n");
  292. }
  293. core = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
  294. unroll_module_reset:
  295. list_for_each_entry_from(core, &cluster->cores, elem) {
  296. if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
  297. core->ti_sci_id))
  298. dev_warn(core->dev, "module-reset assert back failed\n");
  299. }
  300. return ret;
  301. }
  302. static inline int k3_r5_core_halt(struct k3_r5_core *core)
  303. {
  304. return ti_sci_proc_set_control(core->tsp,
  305. PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);
  306. }
  307. static inline int k3_r5_core_run(struct k3_r5_core *core)
  308. {
  309. return ti_sci_proc_set_control(core->tsp,
  310. 0, PROC_BOOT_CTRL_FLAG_R5_CORE_HALT);
  311. }
  312. /*
  313. * The R5F cores have controls for both a reset and a halt/run. The code
  314. * execution from DDR requires the initial boot-strapping code to be run
  315. * from the internal TCMs. This function is used to release the resets on
  316. * applicable cores to allow loading into the TCMs. The .prepare() ops is
  317. * invoked by remoteproc core before any firmware loading, and is followed
  318. * by the .start() ops after loading to actually let the R5 cores run.
  319. */
  320. static int k3_r5_rproc_prepare(struct rproc *rproc)
  321. {
  322. struct k3_r5_rproc *kproc = rproc->priv;
  323. struct k3_r5_cluster *cluster = kproc->cluster;
  324. struct k3_r5_core *core = kproc->core;
  325. struct device *dev = kproc->dev;
  326. int ret;
  327. ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP) ?
  328. k3_r5_lockstep_release(cluster) : k3_r5_split_release(core);
  329. if (ret) {
  330. dev_err(dev, "unable to enable cores for TCM loading, ret = %d\n",
  331. ret);
  332. return ret;
  333. }
  334. /*
  335. * Zero out both TCMs unconditionally (access from v8 Arm core is not
  336. * affected by ATCM & BTCM enable configuration values) so that ECC
  337. * can be effective on all TCM addresses.
  338. */
  339. dev_dbg(dev, "zeroing out ATCM memory\n");
  340. memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
  341. dev_dbg(dev, "zeroing out BTCM memory\n");
  342. memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
  343. return 0;
  344. }
  345. /*
  346. * This function implements the .unprepare() ops and performs the complimentary
  347. * operations to that of the .prepare() ops. The function is used to assert the
  348. * resets on all applicable cores for the rproc device (depending on LockStep
  349. * or Split mode). This completes the second portion of powering down the R5F
  350. * cores. The cores themselves are only halted in the .stop() ops, and the
  351. * .unprepare() ops is invoked by the remoteproc core after the remoteproc is
  352. * stopped.
  353. */
  354. static int k3_r5_rproc_unprepare(struct rproc *rproc)
  355. {
  356. struct k3_r5_rproc *kproc = rproc->priv;
  357. struct k3_r5_cluster *cluster = kproc->cluster;
  358. struct k3_r5_core *core = kproc->core;
  359. struct device *dev = kproc->dev;
  360. int ret;
  361. ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP) ?
  362. k3_r5_lockstep_reset(cluster) : k3_r5_split_reset(core);
  363. if (ret)
  364. dev_err(dev, "unable to disable cores, ret = %d\n", ret);
  365. return ret;
  366. }
  367. /*
  368. * The R5F start sequence includes two different operations
  369. * 1. Configure the boot vector for R5F core(s)
  370. * 2. Unhalt/Run the R5F core(s)
  371. *
  372. * The sequence is different between LockStep and Split modes. The LockStep
  373. * mode requires the boot vector to be configured only for Core0, and then
  374. * unhalt both the cores to start the execution - Core1 needs to be unhalted
  375. * first followed by Core0. The Split-mode requires that Core0 to be maintained
  376. * always in a higher power state that Core1 (implying Core1 needs to be started
  377. * always only after Core0 is started).
  378. */
  379. static int k3_r5_rproc_start(struct rproc *rproc)
  380. {
  381. struct k3_r5_rproc *kproc = rproc->priv;
  382. struct k3_r5_cluster *cluster = kproc->cluster;
  383. struct mbox_client *client = &kproc->client;
  384. struct device *dev = kproc->dev;
  385. struct k3_r5_core *core;
  386. u32 boot_addr;
  387. int ret;
  388. client->dev = dev;
  389. client->tx_done = NULL;
  390. client->rx_callback = k3_r5_rproc_mbox_callback;
  391. client->tx_block = false;
  392. client->knows_txdone = false;
  393. kproc->mbox = mbox_request_channel(client, 0);
  394. if (IS_ERR(kproc->mbox)) {
  395. ret = -EBUSY;
  396. dev_err(dev, "mbox_request_channel failed: %ld\n",
  397. PTR_ERR(kproc->mbox));
  398. return ret;
  399. }
  400. /*
  401. * Ping the remote processor, this is only for sanity-sake for now;
  402. * there is no functional effect whatsoever.
  403. *
  404. * Note that the reply will _not_ arrive immediately: this message
  405. * will wait in the mailbox fifo until the remote processor is booted.
  406. */
  407. ret = mbox_send_message(kproc->mbox, (void *)RP_MBOX_ECHO_REQUEST);
  408. if (ret < 0) {
  409. dev_err(dev, "mbox_send_message failed: %d\n", ret);
  410. goto put_mbox;
  411. }
  412. boot_addr = rproc->bootaddr;
  413. /* TODO: add boot_addr sanity checking */
  414. dev_dbg(dev, "booting R5F core using boot addr = 0x%x\n", boot_addr);
  415. /* boot vector need not be programmed for Core1 in LockStep mode */
  416. core = kproc->core;
  417. ret = ti_sci_proc_set_config(core->tsp, boot_addr, 0, 0);
  418. if (ret)
  419. goto put_mbox;
  420. /* unhalt/run all applicable cores */
  421. if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
  422. list_for_each_entry_reverse(core, &cluster->cores, elem) {
  423. ret = k3_r5_core_run(core);
  424. if (ret)
  425. goto unroll_core_run;
  426. }
  427. } else {
  428. ret = k3_r5_core_run(core);
  429. if (ret)
  430. goto put_mbox;
  431. }
  432. return 0;
  433. unroll_core_run:
  434. list_for_each_entry_continue(core, &cluster->cores, elem) {
  435. if (k3_r5_core_halt(core))
  436. dev_warn(core->dev, "core halt back failed\n");
  437. }
  438. put_mbox:
  439. mbox_free_channel(kproc->mbox);
  440. return ret;
  441. }
  442. /*
  443. * The R5F stop function includes the following operations
  444. * 1. Halt R5F core(s)
  445. *
  446. * The sequence is different between LockStep and Split modes, and the order
  447. * of cores the operations are performed are also in general reverse to that
  448. * of the start function. The LockStep mode requires each operation to be
  449. * performed first on Core0 followed by Core1. The Split-mode requires that
  450. * Core0 to be maintained always in a higher power state that Core1 (implying
  451. * Core1 needs to be stopped first before Core0).
  452. *
  453. * Note that the R5F halt operation in general is not effective when the R5F
  454. * core is running, but is needed to make sure the core won't run after
  455. * deasserting the reset the subsequent time. The asserting of reset can
  456. * be done here, but is preferred to be done in the .unprepare() ops - this
  457. * maintains the symmetric behavior between the .start(), .stop(), .prepare()
  458. * and .unprepare() ops, and also balances them well between sysfs 'state'
  459. * flow and device bind/unbind or module removal.
  460. */
  461. static int k3_r5_rproc_stop(struct rproc *rproc)
  462. {
  463. struct k3_r5_rproc *kproc = rproc->priv;
  464. struct k3_r5_cluster *cluster = kproc->cluster;
  465. struct k3_r5_core *core = kproc->core;
  466. int ret;
  467. /* halt all applicable cores */
  468. if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
  469. list_for_each_entry(core, &cluster->cores, elem) {
  470. ret = k3_r5_core_halt(core);
  471. if (ret) {
  472. core = list_prev_entry(core, elem);
  473. goto unroll_core_halt;
  474. }
  475. }
  476. } else {
  477. ret = k3_r5_core_halt(core);
  478. if (ret)
  479. goto out;
  480. }
  481. mbox_free_channel(kproc->mbox);
  482. return 0;
  483. unroll_core_halt:
  484. list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
  485. if (k3_r5_core_run(core))
  486. dev_warn(core->dev, "core run back failed\n");
  487. }
  488. out:
  489. return ret;
  490. }
  491. /*
  492. * Internal Memory translation helper
  493. *
  494. * Custom function implementing the rproc .da_to_va ops to provide address
  495. * translation (device address to kernel virtual address) for internal RAMs
  496. * present in a DSP or IPU device). The translated addresses can be used
  497. * either by the remoteproc core for loading, or by any rpmsg bus drivers.
  498. */
  499. static void *k3_r5_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
  500. {
  501. struct k3_r5_rproc *kproc = rproc->priv;
  502. struct k3_r5_core *core = kproc->core;
  503. void __iomem *va = NULL;
  504. phys_addr_t bus_addr;
  505. u32 dev_addr, offset;
  506. size_t size;
  507. int i;
  508. if (len == 0)
  509. return NULL;
  510. /* handle both R5 and SoC views of ATCM and BTCM */
  511. for (i = 0; i < core->num_mems; i++) {
  512. bus_addr = core->mem[i].bus_addr;
  513. dev_addr = core->mem[i].dev_addr;
  514. size = core->mem[i].size;
  515. /* handle R5-view addresses of TCMs */
  516. if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
  517. offset = da - dev_addr;
  518. va = core->mem[i].cpu_addr + offset;
  519. return (__force void *)va;
  520. }
  521. /* handle SoC-view addresses of TCMs */
  522. if (da >= bus_addr && ((da + len) <= (bus_addr + size))) {
  523. offset = da - bus_addr;
  524. va = core->mem[i].cpu_addr + offset;
  525. return (__force void *)va;
  526. }
  527. }
  528. /* handle any SRAM regions using SoC-view addresses */
  529. for (i = 0; i < core->num_sram; i++) {
  530. dev_addr = core->sram[i].dev_addr;
  531. size = core->sram[i].size;
  532. if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
  533. offset = da - dev_addr;
  534. va = core->sram[i].cpu_addr + offset;
  535. return (__force void *)va;
  536. }
  537. }
  538. /* handle static DDR reserved memory regions */
  539. for (i = 0; i < kproc->num_rmems; i++) {
  540. dev_addr = kproc->rmem[i].dev_addr;
  541. size = kproc->rmem[i].size;
  542. if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
  543. offset = da - dev_addr;
  544. va = kproc->rmem[i].cpu_addr + offset;
  545. return (__force void *)va;
  546. }
  547. }
  548. return NULL;
  549. }
  550. static const struct rproc_ops k3_r5_rproc_ops = {
  551. .prepare = k3_r5_rproc_prepare,
  552. .unprepare = k3_r5_rproc_unprepare,
  553. .start = k3_r5_rproc_start,
  554. .stop = k3_r5_rproc_stop,
  555. .kick = k3_r5_rproc_kick,
  556. .da_to_va = k3_r5_rproc_da_to_va,
  557. };
  558. /*
  559. * Internal R5F Core configuration
  560. *
  561. * Each R5FSS has a cluster-level setting for configuring the processor
  562. * subsystem either in a safety/fault-tolerant LockStep mode or a performance
  563. * oriented Split mode. Each R5F core has a number of settings to either
  564. * enable/disable each of the TCMs, control which TCM appears at the R5F core's
  565. * address 0x0. These settings need to be configured before the resets for the
  566. * corresponding core are released. These settings are all protected and managed
  567. * by the System Processor.
  568. *
  569. * This function is used to pre-configure these settings for each R5F core, and
  570. * the configuration is all done through various ti_sci_proc functions that
  571. * communicate with the System Processor. The function also ensures that both
  572. * the cores are halted before the .prepare() step.
  573. *
  574. * The function is called from k3_r5_cluster_rproc_init() and is invoked either
  575. * once (in LockStep mode) or twice (in Split mode). Support for LockStep-mode
  576. * is dictated by an eFUSE register bit, and the config settings retrieved from
  577. * DT are adjusted accordingly as per the permitted cluster mode. All cluster
  578. * level settings like Cluster mode and TEINIT (exception handling state
  579. * dictating ARM or Thumb mode) can only be set and retrieved using Core0.
  580. *
  581. * The function behavior is different based on the cluster mode. The R5F cores
  582. * are configured independently as per their individual settings in Split mode.
  583. * They are identically configured in LockStep mode using the primary Core0
  584. * settings. However, some individual settings cannot be set in LockStep mode.
  585. * This is overcome by switching to Split-mode initially and then programming
  586. * both the cores with the same settings, before reconfiguing again for
  587. * LockStep mode.
  588. */
  589. static int k3_r5_rproc_configure(struct k3_r5_rproc *kproc)
  590. {
  591. struct k3_r5_cluster *cluster = kproc->cluster;
  592. struct device *dev = kproc->dev;
  593. struct k3_r5_core *core0, *core, *temp;
  594. u32 ctrl = 0, cfg = 0, stat = 0;
  595. u32 set_cfg = 0, clr_cfg = 0;
  596. u64 boot_vec = 0;
  597. bool lockstep_en;
  598. int ret;
  599. core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
  600. core = (cluster->mode == CLUSTER_MODE_LOCKSTEP) ? core0 : kproc->core;
  601. ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,
  602. &stat);
  603. if (ret < 0)
  604. return ret;
  605. dev_dbg(dev, "boot_vector = 0x%llx, cfg = 0x%x ctrl = 0x%x stat = 0x%x\n",
  606. boot_vec, cfg, ctrl, stat);
  607. lockstep_en = !!(stat & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED);
  608. if (!lockstep_en && cluster->mode == CLUSTER_MODE_LOCKSTEP) {
  609. dev_err(cluster->dev, "lockstep mode not permitted, force configuring for split-mode\n");
  610. cluster->mode = CLUSTER_MODE_SPLIT;
  611. }
  612. /* always enable ARM mode and set boot vector to 0 */
  613. boot_vec = 0x0;
  614. if (core == core0) {
  615. clr_cfg = PROC_BOOT_CFG_FLAG_R5_TEINIT;
  616. /*
  617. * LockStep configuration bit is Read-only on Split-mode _only_
  618. * devices and system firmware will NACK any requests with the
  619. * bit configured, so program it only on permitted devices
  620. */
  621. if (lockstep_en)
  622. clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
  623. }
  624. if (core->atcm_enable)
  625. set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
  626. else
  627. clr_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
  628. if (core->btcm_enable)
  629. set_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
  630. else
  631. clr_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
  632. if (core->loczrama)
  633. set_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
  634. else
  635. clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
  636. if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
  637. /*
  638. * work around system firmware limitations to make sure both
  639. * cores are programmed symmetrically in LockStep. LockStep
  640. * and TEINIT config is only allowed with Core0.
  641. */
  642. list_for_each_entry(temp, &cluster->cores, elem) {
  643. ret = k3_r5_core_halt(temp);
  644. if (ret)
  645. goto out;
  646. if (temp != core) {
  647. clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
  648. clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_TEINIT;
  649. }
  650. ret = ti_sci_proc_set_config(temp->tsp, boot_vec,
  651. set_cfg, clr_cfg);
  652. if (ret)
  653. goto out;
  654. }
  655. set_cfg = PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
  656. clr_cfg = 0;
  657. ret = ti_sci_proc_set_config(core->tsp, boot_vec,
  658. set_cfg, clr_cfg);
  659. } else {
  660. ret = k3_r5_core_halt(core);
  661. if (ret)
  662. goto out;
  663. ret = ti_sci_proc_set_config(core->tsp, boot_vec,
  664. set_cfg, clr_cfg);
  665. }
  666. out:
  667. return ret;
  668. }
  669. static int k3_r5_reserved_mem_init(struct k3_r5_rproc *kproc)
  670. {
  671. struct device *dev = kproc->dev;
  672. struct device_node *np = dev_of_node(dev);
  673. struct device_node *rmem_np;
  674. struct reserved_mem *rmem;
  675. int num_rmems;
  676. int ret, i;
  677. num_rmems = of_property_count_elems_of_size(np, "memory-region",
  678. sizeof(phandle));
  679. if (num_rmems <= 0) {
  680. dev_err(dev, "device does not have reserved memory regions, ret = %d\n",
  681. num_rmems);
  682. return -EINVAL;
  683. }
  684. if (num_rmems < 2) {
  685. dev_err(dev, "device needs atleast two memory regions to be defined, num = %d\n",
  686. num_rmems);
  687. return -EINVAL;
  688. }
  689. /* use reserved memory region 0 for vring DMA allocations */
  690. ret = of_reserved_mem_device_init_by_idx(dev, np, 0);
  691. if (ret) {
  692. dev_err(dev, "device cannot initialize DMA pool, ret = %d\n",
  693. ret);
  694. return ret;
  695. }
  696. num_rmems--;
  697. kproc->rmem = kcalloc(num_rmems, sizeof(*kproc->rmem), GFP_KERNEL);
  698. if (!kproc->rmem) {
  699. ret = -ENOMEM;
  700. goto release_rmem;
  701. }
  702. /* use remaining reserved memory regions for static carveouts */
  703. for (i = 0; i < num_rmems; i++) {
  704. rmem_np = of_parse_phandle(np, "memory-region", i + 1);
  705. if (!rmem_np) {
  706. ret = -EINVAL;
  707. goto unmap_rmem;
  708. }
  709. rmem = of_reserved_mem_lookup(rmem_np);
  710. if (!rmem) {
  711. of_node_put(rmem_np);
  712. ret = -EINVAL;
  713. goto unmap_rmem;
  714. }
  715. of_node_put(rmem_np);
  716. kproc->rmem[i].bus_addr = rmem->base;
  717. /*
  718. * R5Fs do not have an MMU, but have a Region Address Translator
  719. * (RAT) module that provides a fixed entry translation between
  720. * the 32-bit processor addresses to 64-bit bus addresses. The
  721. * RAT is programmable only by the R5F cores. Support for RAT
  722. * is currently not supported, so 64-bit address regions are not
  723. * supported. The absence of MMUs implies that the R5F device
  724. * addresses/supported memory regions are restricted to 32-bit
  725. * bus addresses, and are identical
  726. */
  727. kproc->rmem[i].dev_addr = (u32)rmem->base;
  728. kproc->rmem[i].size = rmem->size;
  729. kproc->rmem[i].cpu_addr = ioremap_wc(rmem->base, rmem->size);
  730. if (!kproc->rmem[i].cpu_addr) {
  731. dev_err(dev, "failed to map reserved memory#%d at %pa of size %pa\n",
  732. i + 1, &rmem->base, &rmem->size);
  733. ret = -ENOMEM;
  734. goto unmap_rmem;
  735. }
  736. dev_dbg(dev, "reserved memory%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
  737. i + 1, &kproc->rmem[i].bus_addr,
  738. kproc->rmem[i].size, kproc->rmem[i].cpu_addr,
  739. kproc->rmem[i].dev_addr);
  740. }
  741. kproc->num_rmems = num_rmems;
  742. return 0;
  743. unmap_rmem:
  744. for (i--; i >= 0; i--)
  745. iounmap(kproc->rmem[i].cpu_addr);
  746. kfree(kproc->rmem);
  747. release_rmem:
  748. of_reserved_mem_device_release(dev);
  749. return ret;
  750. }
  751. static void k3_r5_reserved_mem_exit(struct k3_r5_rproc *kproc)
  752. {
  753. int i;
  754. for (i = 0; i < kproc->num_rmems; i++)
  755. iounmap(kproc->rmem[i].cpu_addr);
  756. kfree(kproc->rmem);
  757. of_reserved_mem_device_release(kproc->dev);
  758. }
  759. static int k3_r5_cluster_rproc_init(struct platform_device *pdev)
  760. {
  761. struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
  762. struct device *dev = &pdev->dev;
  763. struct k3_r5_rproc *kproc;
  764. struct k3_r5_core *core, *core1;
  765. struct device *cdev;
  766. const char *fw_name;
  767. struct rproc *rproc;
  768. int ret;
  769. core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
  770. list_for_each_entry(core, &cluster->cores, elem) {
  771. cdev = core->dev;
  772. ret = rproc_of_parse_firmware(cdev, 0, &fw_name);
  773. if (ret) {
  774. dev_err(dev, "failed to parse firmware-name property, ret = %d\n",
  775. ret);
  776. goto out;
  777. }
  778. rproc = rproc_alloc(cdev, dev_name(cdev), &k3_r5_rproc_ops,
  779. fw_name, sizeof(*kproc));
  780. if (!rproc) {
  781. ret = -ENOMEM;
  782. goto out;
  783. }
  784. /* K3 R5s have a Region Address Translator (RAT) but no MMU */
  785. rproc->has_iommu = false;
  786. /* error recovery is not supported at present */
  787. rproc->recovery_disabled = true;
  788. kproc = rproc->priv;
  789. kproc->cluster = cluster;
  790. kproc->core = core;
  791. kproc->dev = cdev;
  792. kproc->rproc = rproc;
  793. core->rproc = rproc;
  794. ret = k3_r5_rproc_configure(kproc);
  795. if (ret) {
  796. dev_err(dev, "initial configure failed, ret = %d\n",
  797. ret);
  798. goto err_config;
  799. }
  800. ret = k3_r5_reserved_mem_init(kproc);
  801. if (ret) {
  802. dev_err(dev, "reserved memory init failed, ret = %d\n",
  803. ret);
  804. goto err_config;
  805. }
  806. ret = rproc_add(rproc);
  807. if (ret) {
  808. dev_err(dev, "rproc_add failed, ret = %d\n", ret);
  809. goto err_add;
  810. }
  811. /* create only one rproc in lockstep mode */
  812. if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
  813. break;
  814. }
  815. return 0;
  816. err_split:
  817. rproc_del(rproc);
  818. err_add:
  819. k3_r5_reserved_mem_exit(kproc);
  820. err_config:
  821. rproc_free(rproc);
  822. core->rproc = NULL;
  823. out:
  824. /* undo core0 upon any failures on core1 in split-mode */
  825. if (cluster->mode == CLUSTER_MODE_SPLIT && core == core1) {
  826. core = list_prev_entry(core, elem);
  827. rproc = core->rproc;
  828. kproc = rproc->priv;
  829. goto err_split;
  830. }
  831. return ret;
  832. }
  833. static int k3_r5_cluster_rproc_exit(struct platform_device *pdev)
  834. {
  835. struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
  836. struct k3_r5_rproc *kproc;
  837. struct k3_r5_core *core;
  838. struct rproc *rproc;
  839. /*
  840. * lockstep mode has only one rproc associated with first core, whereas
  841. * split-mode has two rprocs associated with each core, and requires
  842. * that core1 be powered down first
  843. */
  844. core = (cluster->mode == CLUSTER_MODE_LOCKSTEP) ?
  845. list_first_entry(&cluster->cores, struct k3_r5_core, elem) :
  846. list_last_entry(&cluster->cores, struct k3_r5_core, elem);
  847. list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
  848. rproc = core->rproc;
  849. kproc = rproc->priv;
  850. rproc_del(rproc);
  851. k3_r5_reserved_mem_exit(kproc);
  852. rproc_free(rproc);
  853. core->rproc = NULL;
  854. }
  855. return 0;
  856. }
  857. static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev,
  858. struct k3_r5_core *core)
  859. {
  860. static const char * const mem_names[] = {"atcm", "btcm"};
  861. struct device *dev = &pdev->dev;
  862. struct resource *res;
  863. int num_mems;
  864. int i;
  865. num_mems = ARRAY_SIZE(mem_names);
  866. core->mem = devm_kcalloc(dev, num_mems, sizeof(*core->mem), GFP_KERNEL);
  867. if (!core->mem)
  868. return -ENOMEM;
  869. for (i = 0; i < num_mems; i++) {
  870. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  871. mem_names[i]);
  872. if (!res) {
  873. dev_err(dev, "found no memory resource for %s\n",
  874. mem_names[i]);
  875. return -EINVAL;
  876. }
  877. if (!devm_request_mem_region(dev, res->start,
  878. resource_size(res),
  879. dev_name(dev))) {
  880. dev_err(dev, "could not request %s region for resource\n",
  881. mem_names[i]);
  882. return -EBUSY;
  883. }
  884. /*
  885. * TCMs are designed in general to support RAM-like backing
  886. * memories. So, map these as Normal Non-Cached memories. This
  887. * also avoids/fixes any potential alignment faults due to
  888. * unaligned data accesses when using memcpy() or memset()
  889. * functions (normally seen with device type memory).
  890. */
  891. core->mem[i].cpu_addr = devm_ioremap_wc(dev, res->start,
  892. resource_size(res));
  893. if (!core->mem[i].cpu_addr) {
  894. dev_err(dev, "failed to map %s memory\n", mem_names[i]);
  895. return -ENOMEM;
  896. }
  897. core->mem[i].bus_addr = res->start;
  898. /*
  899. * TODO:
  900. * The R5F cores can place ATCM & BTCM anywhere in its address
  901. * based on the corresponding Region Registers in the System
  902. * Control coprocessor. For now, place ATCM and BTCM at
  903. * addresses 0 and 0x41010000 (same as the bus address on AM65x
  904. * SoCs) based on loczrama setting
  905. */
  906. if (!strcmp(mem_names[i], "atcm")) {
  907. core->mem[i].dev_addr = core->loczrama ?
  908. 0 : K3_R5_TCM_DEV_ADDR;
  909. } else {
  910. core->mem[i].dev_addr = core->loczrama ?
  911. K3_R5_TCM_DEV_ADDR : 0;
  912. }
  913. core->mem[i].size = resource_size(res);
  914. dev_dbg(dev, "memory %5s: bus addr %pa size 0x%zx va %pK da 0x%x\n",
  915. mem_names[i], &core->mem[i].bus_addr,
  916. core->mem[i].size, core->mem[i].cpu_addr,
  917. core->mem[i].dev_addr);
  918. }
  919. core->num_mems = num_mems;
  920. return 0;
  921. }
  922. static int k3_r5_core_of_get_sram_memories(struct platform_device *pdev,
  923. struct k3_r5_core *core)
  924. {
  925. struct device_node *np = pdev->dev.of_node;
  926. struct device *dev = &pdev->dev;
  927. struct device_node *sram_np;
  928. struct resource res;
  929. int num_sram;
  930. int i, ret;
  931. num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle));
  932. if (num_sram <= 0) {
  933. dev_dbg(dev, "device does not use reserved on-chip memories, num_sram = %d\n",
  934. num_sram);
  935. return 0;
  936. }
  937. core->sram = devm_kcalloc(dev, num_sram, sizeof(*core->sram), GFP_KERNEL);
  938. if (!core->sram)
  939. return -ENOMEM;
  940. for (i = 0; i < num_sram; i++) {
  941. sram_np = of_parse_phandle(np, "sram", i);
  942. if (!sram_np)
  943. return -EINVAL;
  944. if (!of_device_is_available(sram_np)) {
  945. of_node_put(sram_np);
  946. return -EINVAL;
  947. }
  948. ret = of_address_to_resource(sram_np, 0, &res);
  949. of_node_put(sram_np);
  950. if (ret)
  951. return -EINVAL;
  952. core->sram[i].bus_addr = res.start;
  953. core->sram[i].dev_addr = res.start;
  954. core->sram[i].size = resource_size(&res);
  955. core->sram[i].cpu_addr = devm_ioremap_wc(dev, res.start,
  956. resource_size(&res));
  957. if (!core->sram[i].cpu_addr) {
  958. dev_err(dev, "failed to parse and map sram%d memory at %pad\n",
  959. i, &res.start);
  960. return -ENOMEM;
  961. }
  962. dev_dbg(dev, "memory sram%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
  963. i, &core->sram[i].bus_addr,
  964. core->sram[i].size, core->sram[i].cpu_addr,
  965. core->sram[i].dev_addr);
  966. }
  967. core->num_sram = num_sram;
  968. return 0;
  969. }
  970. static
  971. struct ti_sci_proc *k3_r5_core_of_get_tsp(struct device *dev,
  972. const struct ti_sci_handle *sci)
  973. {
  974. struct ti_sci_proc *tsp;
  975. u32 temp[2];
  976. int ret;
  977. ret = of_property_read_u32_array(dev_of_node(dev), "ti,sci-proc-ids",
  978. temp, 2);
  979. if (ret < 0)
  980. return ERR_PTR(ret);
  981. tsp = devm_kzalloc(dev, sizeof(*tsp), GFP_KERNEL);
  982. if (!tsp)
  983. return ERR_PTR(-ENOMEM);
  984. tsp->dev = dev;
  985. tsp->sci = sci;
  986. tsp->ops = &sci->ops.proc_ops;
  987. tsp->proc_id = temp[0];
  988. tsp->host_id = temp[1];
  989. return tsp;
  990. }
  991. static int k3_r5_core_of_init(struct platform_device *pdev)
  992. {
  993. struct device *dev = &pdev->dev;
  994. struct device_node *np = dev_of_node(dev);
  995. struct k3_r5_core *core;
  996. int ret;
  997. if (!devres_open_group(dev, k3_r5_core_of_init, GFP_KERNEL))
  998. return -ENOMEM;
  999. core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
  1000. if (!core) {
  1001. ret = -ENOMEM;
  1002. goto err;
  1003. }
  1004. core->dev = dev;
  1005. /*
  1006. * Use SoC Power-on-Reset values as default if no DT properties are
  1007. * used to dictate the TCM configurations
  1008. */
  1009. core->atcm_enable = 0;
  1010. core->btcm_enable = 1;
  1011. core->loczrama = 1;
  1012. ret = of_property_read_u32(np, "ti,atcm-enable", &core->atcm_enable);
  1013. if (ret < 0 && ret != -EINVAL) {
  1014. dev_err(dev, "invalid format for ti,atcm-enable, ret = %d\n",
  1015. ret);
  1016. goto err;
  1017. }
  1018. ret = of_property_read_u32(np, "ti,btcm-enable", &core->btcm_enable);
  1019. if (ret < 0 && ret != -EINVAL) {
  1020. dev_err(dev, "invalid format for ti,btcm-enable, ret = %d\n",
  1021. ret);
  1022. goto err;
  1023. }
  1024. ret = of_property_read_u32(np, "ti,loczrama", &core->loczrama);
  1025. if (ret < 0 && ret != -EINVAL) {
  1026. dev_err(dev, "invalid format for ti,loczrama, ret = %d\n", ret);
  1027. goto err;
  1028. }
  1029. core->ti_sci = devm_ti_sci_get_by_phandle(dev, "ti,sci");
  1030. if (IS_ERR(core->ti_sci)) {
  1031. ret = PTR_ERR(core->ti_sci);
  1032. if (ret != -EPROBE_DEFER) {
  1033. dev_err(dev, "failed to get ti-sci handle, ret = %d\n",
  1034. ret);
  1035. }
  1036. core->ti_sci = NULL;
  1037. goto err;
  1038. }
  1039. ret = of_property_read_u32(np, "ti,sci-dev-id", &core->ti_sci_id);
  1040. if (ret) {
  1041. dev_err(dev, "missing 'ti,sci-dev-id' property\n");
  1042. goto err;
  1043. }
  1044. core->reset = devm_reset_control_get_exclusive(dev, NULL);
  1045. if (IS_ERR_OR_NULL(core->reset)) {
  1046. ret = PTR_ERR_OR_ZERO(core->reset);
  1047. if (!ret)
  1048. ret = -ENODEV;
  1049. if (ret != -EPROBE_DEFER) {
  1050. dev_err(dev, "failed to get reset handle, ret = %d\n",
  1051. ret);
  1052. }
  1053. goto err;
  1054. }
  1055. core->tsp = k3_r5_core_of_get_tsp(dev, core->ti_sci);
  1056. if (IS_ERR(core->tsp)) {
  1057. ret = PTR_ERR(core->tsp);
  1058. dev_err(dev, "failed to construct ti-sci proc control, ret = %d\n",
  1059. ret);
  1060. goto err;
  1061. }
  1062. ret = k3_r5_core_of_get_internal_memories(pdev, core);
  1063. if (ret) {
  1064. dev_err(dev, "failed to get internal memories, ret = %d\n",
  1065. ret);
  1066. goto err;
  1067. }
  1068. ret = k3_r5_core_of_get_sram_memories(pdev, core);
  1069. if (ret) {
  1070. dev_err(dev, "failed to get sram memories, ret = %d\n", ret);
  1071. goto err;
  1072. }
  1073. ret = ti_sci_proc_request(core->tsp);
  1074. if (ret < 0) {
  1075. dev_err(dev, "ti_sci_proc_request failed, ret = %d\n", ret);
  1076. goto err;
  1077. }
  1078. platform_set_drvdata(pdev, core);
  1079. devres_close_group(dev, k3_r5_core_of_init);
  1080. return 0;
  1081. err:
  1082. devres_release_group(dev, k3_r5_core_of_init);
  1083. return ret;
  1084. }
  1085. /*
  1086. * free the resources explicitly since driver model is not being used
  1087. * for the child R5F devices
  1088. */
  1089. static void k3_r5_core_of_exit(struct platform_device *pdev)
  1090. {
  1091. struct k3_r5_core *core = platform_get_drvdata(pdev);
  1092. struct device *dev = &pdev->dev;
  1093. int ret;
  1094. ret = ti_sci_proc_release(core->tsp);
  1095. if (ret)
  1096. dev_err(dev, "failed to release proc, ret = %d\n", ret);
  1097. platform_set_drvdata(pdev, NULL);
  1098. devres_release_group(dev, k3_r5_core_of_init);
  1099. }
  1100. static void k3_r5_cluster_of_exit(struct platform_device *pdev)
  1101. {
  1102. struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
  1103. struct platform_device *cpdev;
  1104. struct k3_r5_core *core, *temp;
  1105. list_for_each_entry_safe_reverse(core, temp, &cluster->cores, elem) {
  1106. list_del(&core->elem);
  1107. cpdev = to_platform_device(core->dev);
  1108. k3_r5_core_of_exit(cpdev);
  1109. }
  1110. }
  1111. static int k3_r5_cluster_of_init(struct platform_device *pdev)
  1112. {
  1113. struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
  1114. struct device *dev = &pdev->dev;
  1115. struct device_node *np = dev_of_node(dev);
  1116. struct platform_device *cpdev;
  1117. struct device_node *child;
  1118. struct k3_r5_core *core;
  1119. int ret;
  1120. for_each_available_child_of_node(np, child) {
  1121. cpdev = of_find_device_by_node(child);
  1122. if (!cpdev) {
  1123. ret = -ENODEV;
  1124. dev_err(dev, "could not get R5 core platform device\n");
  1125. goto fail;
  1126. }
  1127. ret = k3_r5_core_of_init(cpdev);
  1128. if (ret) {
  1129. dev_err(dev, "k3_r5_core_of_init failed, ret = %d\n",
  1130. ret);
  1131. put_device(&cpdev->dev);
  1132. goto fail;
  1133. }
  1134. core = platform_get_drvdata(cpdev);
  1135. put_device(&cpdev->dev);
  1136. list_add_tail(&core->elem, &cluster->cores);
  1137. }
  1138. return 0;
  1139. fail:
  1140. k3_r5_cluster_of_exit(pdev);
  1141. return ret;
  1142. }
  1143. static int k3_r5_probe(struct platform_device *pdev)
  1144. {
  1145. struct device *dev = &pdev->dev;
  1146. struct device_node *np = dev_of_node(dev);
  1147. struct k3_r5_cluster *cluster;
  1148. int ret;
  1149. int num_cores;
  1150. cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL);
  1151. if (!cluster)
  1152. return -ENOMEM;
  1153. cluster->dev = dev;
  1154. cluster->mode = CLUSTER_MODE_LOCKSTEP;
  1155. INIT_LIST_HEAD(&cluster->cores);
  1156. ret = of_property_read_u32(np, "ti,cluster-mode", &cluster->mode);
  1157. if (ret < 0 && ret != -EINVAL) {
  1158. dev_err(dev, "invalid format for ti,cluster-mode, ret = %d\n",
  1159. ret);
  1160. return ret;
  1161. }
  1162. num_cores = of_get_available_child_count(np);
  1163. if (num_cores != 2) {
  1164. dev_err(dev, "MCU cluster requires both R5F cores to be enabled, num_cores = %d\n",
  1165. num_cores);
  1166. return -ENODEV;
  1167. }
  1168. platform_set_drvdata(pdev, cluster);
  1169. ret = devm_of_platform_populate(dev);
  1170. if (ret) {
  1171. dev_err(dev, "devm_of_platform_populate failed, ret = %d\n",
  1172. ret);
  1173. return ret;
  1174. }
  1175. ret = k3_r5_cluster_of_init(pdev);
  1176. if (ret) {
  1177. dev_err(dev, "k3_r5_cluster_of_init failed, ret = %d\n", ret);
  1178. return ret;
  1179. }
  1180. ret = devm_add_action_or_reset(dev,
  1181. (void(*)(void *))k3_r5_cluster_of_exit,
  1182. pdev);
  1183. if (ret)
  1184. return ret;
  1185. ret = k3_r5_cluster_rproc_init(pdev);
  1186. if (ret) {
  1187. dev_err(dev, "k3_r5_cluster_rproc_init failed, ret = %d\n",
  1188. ret);
  1189. return ret;
  1190. }
  1191. ret = devm_add_action_or_reset(dev,
  1192. (void(*)(void *))k3_r5_cluster_rproc_exit,
  1193. pdev);
  1194. if (ret)
  1195. return ret;
  1196. return 0;
  1197. }
  1198. static const struct of_device_id k3_r5_of_match[] = {
  1199. { .compatible = "ti,am654-r5fss", },
  1200. { .compatible = "ti,j721e-r5fss", },
  1201. { /* sentinel */ },
  1202. };
  1203. MODULE_DEVICE_TABLE(of, k3_r5_of_match);
  1204. static struct platform_driver k3_r5_rproc_driver = {
  1205. .probe = k3_r5_probe,
  1206. .driver = {
  1207. .name = "k3_r5_rproc",
  1208. .of_match_table = k3_r5_of_match,
  1209. },
  1210. };
  1211. module_platform_driver(k3_r5_rproc_driver);
  1212. MODULE_LICENSE("GPL v2");
  1213. MODULE_DESCRIPTION("TI K3 R5F remote processor driver");
  1214. MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");