qcom_wcnss.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
  4. *
  5. * Copyright (C) 2016 Linaro Ltd
  6. * Copyright (C) 2014 Sony Mobile Communications AB
  7. * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/firmware.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/io.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_device.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/qcom_scm.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/remoteproc.h>
  22. #include <linux/soc/qcom/mdt_loader.h>
  23. #include <linux/soc/qcom/smem.h>
  24. #include <linux/soc/qcom/smem_state.h>
  25. #include <linux/rpmsg/qcom_smd.h>
  26. #include "qcom_common.h"
  27. #include "remoteproc_internal.h"
  28. #include "qcom_pil_info.h"
  29. #include "qcom_wcnss.h"
  30. #define WCNSS_CRASH_REASON_SMEM 422
  31. #define WCNSS_FIRMWARE_NAME "wcnss.mdt"
  32. #define WCNSS_PAS_ID 6
  33. #define WCNSS_SSCTL_ID 0x13
  34. #define WCNSS_SPARE_NVBIN_DLND BIT(25)
  35. #define WCNSS_PMU_IRIS_XO_CFG BIT(3)
  36. #define WCNSS_PMU_IRIS_XO_EN BIT(4)
  37. #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
  38. #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
  39. #define WCNSS_PMU_IRIS_RESET BIT(7)
  40. #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
  41. #define WCNSS_PMU_IRIS_XO_READ BIT(9)
  42. #define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
  43. #define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
  44. #define WCNSS_PMU_XO_MODE_19p2 0
  45. #define WCNSS_PMU_XO_MODE_48 3
  46. struct wcnss_data {
  47. size_t pmu_offset;
  48. size_t spare_offset;
  49. const struct wcnss_vreg_info *vregs;
  50. size_t num_vregs;
  51. };
  52. struct qcom_wcnss {
  53. struct device *dev;
  54. struct rproc *rproc;
  55. void __iomem *pmu_cfg;
  56. void __iomem *spare_out;
  57. bool use_48mhz_xo;
  58. int wdog_irq;
  59. int fatal_irq;
  60. int ready_irq;
  61. int handover_irq;
  62. int stop_ack_irq;
  63. struct qcom_smem_state *state;
  64. unsigned stop_bit;
  65. struct mutex iris_lock;
  66. struct qcom_iris *iris;
  67. struct regulator_bulk_data *vregs;
  68. size_t num_vregs;
  69. struct completion start_done;
  70. struct completion stop_done;
  71. phys_addr_t mem_phys;
  72. phys_addr_t mem_reloc;
  73. void *mem_region;
  74. size_t mem_size;
  75. struct qcom_rproc_subdev smd_subdev;
  76. struct qcom_sysmon *sysmon;
  77. };
  78. static const struct wcnss_data riva_data = {
  79. .pmu_offset = 0x28,
  80. .spare_offset = 0xb4,
  81. .vregs = (struct wcnss_vreg_info[]) {
  82. { "vddmx", 1050000, 1150000, 0 },
  83. { "vddcx", 1050000, 1150000, 0 },
  84. { "vddpx", 1800000, 1800000, 0 },
  85. },
  86. .num_vregs = 3,
  87. };
  88. static const struct wcnss_data pronto_v1_data = {
  89. .pmu_offset = 0x1004,
  90. .spare_offset = 0x1088,
  91. .vregs = (struct wcnss_vreg_info[]) {
  92. { "vddmx", 950000, 1150000, 0 },
  93. { "vddcx", .super_turbo = true},
  94. { "vddpx", 1800000, 1800000, 0 },
  95. },
  96. .num_vregs = 3,
  97. };
  98. static const struct wcnss_data pronto_v2_data = {
  99. .pmu_offset = 0x1004,
  100. .spare_offset = 0x1088,
  101. .vregs = (struct wcnss_vreg_info[]) {
  102. { "vddmx", 1287500, 1287500, 0 },
  103. { "vddcx", .super_turbo = true },
  104. { "vddpx", 1800000, 1800000, 0 },
  105. },
  106. .num_vregs = 3,
  107. };
  108. void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
  109. struct qcom_iris *iris,
  110. bool use_48mhz_xo)
  111. {
  112. mutex_lock(&wcnss->iris_lock);
  113. wcnss->iris = iris;
  114. wcnss->use_48mhz_xo = use_48mhz_xo;
  115. mutex_unlock(&wcnss->iris_lock);
  116. }
  117. static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
  118. {
  119. struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
  120. int ret;
  121. ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
  122. wcnss->mem_region, wcnss->mem_phys,
  123. wcnss->mem_size, &wcnss->mem_reloc);
  124. if (ret)
  125. return ret;
  126. qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size);
  127. return 0;
  128. }
  129. static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
  130. {
  131. u32 val;
  132. /* Indicate NV download capability */
  133. val = readl(wcnss->spare_out);
  134. val |= WCNSS_SPARE_NVBIN_DLND;
  135. writel(val, wcnss->spare_out);
  136. }
  137. static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
  138. {
  139. u32 val;
  140. /* Clear PMU cfg register */
  141. writel(0, wcnss->pmu_cfg);
  142. val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
  143. writel(val, wcnss->pmu_cfg);
  144. /* Clear XO_MODE */
  145. val &= ~WCNSS_PMU_XO_MODE_MASK;
  146. if (wcnss->use_48mhz_xo)
  147. val |= WCNSS_PMU_XO_MODE_48 << 1;
  148. else
  149. val |= WCNSS_PMU_XO_MODE_19p2 << 1;
  150. writel(val, wcnss->pmu_cfg);
  151. /* Reset IRIS */
  152. val |= WCNSS_PMU_IRIS_RESET;
  153. writel(val, wcnss->pmu_cfg);
  154. /* Wait for PMU.iris_reg_reset_sts */
  155. while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
  156. cpu_relax();
  157. /* Clear IRIS reset */
  158. val &= ~WCNSS_PMU_IRIS_RESET;
  159. writel(val, wcnss->pmu_cfg);
  160. /* Start IRIS XO configuration */
  161. val |= WCNSS_PMU_IRIS_XO_CFG;
  162. writel(val, wcnss->pmu_cfg);
  163. /* Wait for XO configuration to finish */
  164. while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
  165. cpu_relax();
  166. /* Stop IRIS XO configuration */
  167. val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
  168. val &= ~WCNSS_PMU_IRIS_XO_CFG;
  169. writel(val, wcnss->pmu_cfg);
  170. /* Add some delay for XO to settle */
  171. msleep(20);
  172. }
  173. static int wcnss_start(struct rproc *rproc)
  174. {
  175. struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
  176. int ret;
  177. mutex_lock(&wcnss->iris_lock);
  178. if (!wcnss->iris) {
  179. dev_err(wcnss->dev, "no iris registered\n");
  180. ret = -EINVAL;
  181. goto release_iris_lock;
  182. }
  183. ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
  184. if (ret)
  185. goto release_iris_lock;
  186. ret = qcom_iris_enable(wcnss->iris);
  187. if (ret)
  188. goto disable_regulators;
  189. wcnss_indicate_nv_download(wcnss);
  190. wcnss_configure_iris(wcnss);
  191. ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
  192. if (ret) {
  193. dev_err(wcnss->dev,
  194. "failed to authenticate image and release reset\n");
  195. goto disable_iris;
  196. }
  197. ret = wait_for_completion_timeout(&wcnss->start_done,
  198. msecs_to_jiffies(5000));
  199. if (wcnss->ready_irq > 0 && ret == 0) {
  200. /* We have a ready_irq, but it didn't fire in time. */
  201. dev_err(wcnss->dev, "start timed out\n");
  202. qcom_scm_pas_shutdown(WCNSS_PAS_ID);
  203. ret = -ETIMEDOUT;
  204. goto disable_iris;
  205. }
  206. ret = 0;
  207. disable_iris:
  208. qcom_iris_disable(wcnss->iris);
  209. disable_regulators:
  210. regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
  211. release_iris_lock:
  212. mutex_unlock(&wcnss->iris_lock);
  213. return ret;
  214. }
  215. static int wcnss_stop(struct rproc *rproc)
  216. {
  217. struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
  218. int ret;
  219. if (wcnss->state) {
  220. qcom_smem_state_update_bits(wcnss->state,
  221. BIT(wcnss->stop_bit),
  222. BIT(wcnss->stop_bit));
  223. ret = wait_for_completion_timeout(&wcnss->stop_done,
  224. msecs_to_jiffies(5000));
  225. if (ret == 0)
  226. dev_err(wcnss->dev, "timed out on wait\n");
  227. qcom_smem_state_update_bits(wcnss->state,
  228. BIT(wcnss->stop_bit),
  229. 0);
  230. }
  231. ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
  232. if (ret)
  233. dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
  234. return ret;
  235. }
  236. static void *wcnss_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
  237. {
  238. struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
  239. int offset;
  240. offset = da - wcnss->mem_reloc;
  241. if (offset < 0 || offset + len > wcnss->mem_size)
  242. return NULL;
  243. return wcnss->mem_region + offset;
  244. }
  245. static const struct rproc_ops wcnss_ops = {
  246. .start = wcnss_start,
  247. .stop = wcnss_stop,
  248. .da_to_va = wcnss_da_to_va,
  249. .parse_fw = qcom_register_dump_segments,
  250. .load = wcnss_load,
  251. };
  252. static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
  253. {
  254. struct qcom_wcnss *wcnss = dev;
  255. rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
  256. return IRQ_HANDLED;
  257. }
  258. static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
  259. {
  260. struct qcom_wcnss *wcnss = dev;
  261. size_t len;
  262. char *msg;
  263. msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
  264. if (!IS_ERR(msg) && len > 0 && msg[0])
  265. dev_err(wcnss->dev, "fatal error received: %s\n", msg);
  266. rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
  267. return IRQ_HANDLED;
  268. }
  269. static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
  270. {
  271. struct qcom_wcnss *wcnss = dev;
  272. complete(&wcnss->start_done);
  273. return IRQ_HANDLED;
  274. }
  275. static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
  276. {
  277. /*
  278. * XXX: At this point we're supposed to release the resources that we
  279. * have been holding on behalf of the WCNSS. Unfortunately this
  280. * interrupt comes way before the other side seems to be done.
  281. *
  282. * So we're currently relying on the ready interrupt firing later then
  283. * this and we just disable the resources at the end of wcnss_start().
  284. */
  285. return IRQ_HANDLED;
  286. }
  287. static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
  288. {
  289. struct qcom_wcnss *wcnss = dev;
  290. complete(&wcnss->stop_done);
  291. return IRQ_HANDLED;
  292. }
  293. static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
  294. const struct wcnss_vreg_info *info,
  295. int num_vregs)
  296. {
  297. struct regulator_bulk_data *bulk;
  298. int ret;
  299. int i;
  300. bulk = devm_kcalloc(wcnss->dev,
  301. num_vregs, sizeof(struct regulator_bulk_data),
  302. GFP_KERNEL);
  303. if (!bulk)
  304. return -ENOMEM;
  305. for (i = 0; i < num_vregs; i++)
  306. bulk[i].supply = info[i].name;
  307. ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
  308. if (ret)
  309. return ret;
  310. for (i = 0; i < num_vregs; i++) {
  311. if (info[i].max_voltage)
  312. regulator_set_voltage(bulk[i].consumer,
  313. info[i].min_voltage,
  314. info[i].max_voltage);
  315. if (info[i].load_uA)
  316. regulator_set_load(bulk[i].consumer, info[i].load_uA);
  317. }
  318. wcnss->vregs = bulk;
  319. wcnss->num_vregs = num_vregs;
  320. return 0;
  321. }
  322. static int wcnss_request_irq(struct qcom_wcnss *wcnss,
  323. struct platform_device *pdev,
  324. const char *name,
  325. bool optional,
  326. irq_handler_t thread_fn)
  327. {
  328. int ret;
  329. ret = platform_get_irq_byname(pdev, name);
  330. if (ret < 0 && optional) {
  331. dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
  332. return 0;
  333. } else if (ret < 0) {
  334. dev_err(&pdev->dev, "no %s IRQ defined\n", name);
  335. return ret;
  336. }
  337. ret = devm_request_threaded_irq(&pdev->dev, ret,
  338. NULL, thread_fn,
  339. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  340. "wcnss", wcnss);
  341. if (ret)
  342. dev_err(&pdev->dev, "request %s IRQ failed\n", name);
  343. return ret;
  344. }
  345. static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
  346. {
  347. struct device_node *node;
  348. struct resource r;
  349. int ret;
  350. node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
  351. if (!node) {
  352. dev_err(wcnss->dev, "no memory-region specified\n");
  353. return -EINVAL;
  354. }
  355. ret = of_address_to_resource(node, 0, &r);
  356. of_node_put(node);
  357. if (ret)
  358. return ret;
  359. wcnss->mem_phys = wcnss->mem_reloc = r.start;
  360. wcnss->mem_size = resource_size(&r);
  361. wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
  362. if (!wcnss->mem_region) {
  363. dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
  364. &r.start, wcnss->mem_size);
  365. return -EBUSY;
  366. }
  367. return 0;
  368. }
  369. static int wcnss_probe(struct platform_device *pdev)
  370. {
  371. const struct wcnss_data *data;
  372. struct qcom_wcnss *wcnss;
  373. struct resource *res;
  374. struct rproc *rproc;
  375. void __iomem *mmio;
  376. int ret;
  377. data = of_device_get_match_data(&pdev->dev);
  378. if (!qcom_scm_is_available())
  379. return -EPROBE_DEFER;
  380. if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
  381. dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
  382. return -ENXIO;
  383. }
  384. rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
  385. WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
  386. if (!rproc) {
  387. dev_err(&pdev->dev, "unable to allocate remoteproc\n");
  388. return -ENOMEM;
  389. }
  390. rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
  391. wcnss = (struct qcom_wcnss *)rproc->priv;
  392. wcnss->dev = &pdev->dev;
  393. wcnss->rproc = rproc;
  394. platform_set_drvdata(pdev, wcnss);
  395. init_completion(&wcnss->start_done);
  396. init_completion(&wcnss->stop_done);
  397. mutex_init(&wcnss->iris_lock);
  398. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
  399. mmio = devm_ioremap_resource(&pdev->dev, res);
  400. if (IS_ERR(mmio)) {
  401. ret = PTR_ERR(mmio);
  402. goto free_rproc;
  403. };
  404. ret = wcnss_alloc_memory_region(wcnss);
  405. if (ret)
  406. goto free_rproc;
  407. wcnss->pmu_cfg = mmio + data->pmu_offset;
  408. wcnss->spare_out = mmio + data->spare_offset;
  409. ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs);
  410. if (ret)
  411. goto free_rproc;
  412. ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
  413. if (ret < 0)
  414. goto free_rproc;
  415. wcnss->wdog_irq = ret;
  416. ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
  417. if (ret < 0)
  418. goto free_rproc;
  419. wcnss->fatal_irq = ret;
  420. ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
  421. if (ret < 0)
  422. goto free_rproc;
  423. wcnss->ready_irq = ret;
  424. ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
  425. if (ret < 0)
  426. goto free_rproc;
  427. wcnss->handover_irq = ret;
  428. ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
  429. if (ret < 0)
  430. goto free_rproc;
  431. wcnss->stop_ack_irq = ret;
  432. if (wcnss->stop_ack_irq) {
  433. wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
  434. &wcnss->stop_bit);
  435. if (IS_ERR(wcnss->state)) {
  436. ret = PTR_ERR(wcnss->state);
  437. goto free_rproc;
  438. }
  439. }
  440. qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
  441. wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
  442. if (IS_ERR(wcnss->sysmon)) {
  443. ret = PTR_ERR(wcnss->sysmon);
  444. goto free_rproc;
  445. }
  446. ret = rproc_add(rproc);
  447. if (ret)
  448. goto free_rproc;
  449. return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
  450. free_rproc:
  451. rproc_free(rproc);
  452. return ret;
  453. }
  454. static int wcnss_remove(struct platform_device *pdev)
  455. {
  456. struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
  457. of_platform_depopulate(&pdev->dev);
  458. qcom_smem_state_put(wcnss->state);
  459. rproc_del(wcnss->rproc);
  460. qcom_remove_sysmon_subdev(wcnss->sysmon);
  461. qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
  462. rproc_free(wcnss->rproc);
  463. return 0;
  464. }
  465. static const struct of_device_id wcnss_of_match[] = {
  466. { .compatible = "qcom,riva-pil", &riva_data },
  467. { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
  468. { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
  469. { },
  470. };
  471. MODULE_DEVICE_TABLE(of, wcnss_of_match);
  472. static struct platform_driver wcnss_driver = {
  473. .probe = wcnss_probe,
  474. .remove = wcnss_remove,
  475. .driver = {
  476. .name = "qcom-wcnss-pil",
  477. .of_match_table = wcnss_of_match,
  478. },
  479. };
  480. static int __init wcnss_init(void)
  481. {
  482. int ret;
  483. ret = platform_driver_register(&wcnss_driver);
  484. if (ret)
  485. return ret;
  486. ret = platform_driver_register(&qcom_iris_driver);
  487. if (ret)
  488. platform_driver_unregister(&wcnss_driver);
  489. return ret;
  490. }
  491. module_init(wcnss_init);
  492. static void __exit wcnss_exit(void)
  493. {
  494. platform_driver_unregister(&qcom_iris_driver);
  495. platform_driver_unregister(&wcnss_driver);
  496. }
  497. module_exit(wcnss_exit);
  498. MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
  499. MODULE_LICENSE("GPL v2");