imx_rproc.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/err.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/kernel.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/module.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_device.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/regmap.h>
  15. #include <linux/remoteproc.h>
  16. #define IMX7D_SRC_SCR 0x0C
  17. #define IMX7D_ENABLE_M4 BIT(3)
  18. #define IMX7D_SW_M4P_RST BIT(2)
  19. #define IMX7D_SW_M4C_RST BIT(1)
  20. #define IMX7D_SW_M4C_NON_SCLR_RST BIT(0)
  21. #define IMX7D_M4_RST_MASK (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
  22. | IMX7D_SW_M4C_RST \
  23. | IMX7D_SW_M4C_NON_SCLR_RST)
  24. #define IMX7D_M4_START (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
  25. | IMX7D_SW_M4C_RST)
  26. #define IMX7D_M4_STOP IMX7D_SW_M4C_NON_SCLR_RST
  27. /* Address: 0x020D8000 */
  28. #define IMX6SX_SRC_SCR 0x00
  29. #define IMX6SX_ENABLE_M4 BIT(22)
  30. #define IMX6SX_SW_M4P_RST BIT(12)
  31. #define IMX6SX_SW_M4C_NON_SCLR_RST BIT(4)
  32. #define IMX6SX_SW_M4C_RST BIT(3)
  33. #define IMX6SX_M4_START (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
  34. | IMX6SX_SW_M4C_RST)
  35. #define IMX6SX_M4_STOP IMX6SX_SW_M4C_NON_SCLR_RST
  36. #define IMX6SX_M4_RST_MASK (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
  37. | IMX6SX_SW_M4C_NON_SCLR_RST \
  38. | IMX6SX_SW_M4C_RST)
  39. #define IMX7D_RPROC_MEM_MAX 8
  40. /**
  41. * struct imx_rproc_mem - slim internal memory structure
  42. * @cpu_addr: MPU virtual address of the memory region
  43. * @sys_addr: Bus address used to access the memory region
  44. * @size: Size of the memory region
  45. */
  46. struct imx_rproc_mem {
  47. void __iomem *cpu_addr;
  48. phys_addr_t sys_addr;
  49. size_t size;
  50. };
  51. /* att flags */
  52. /* M4 own area. Can be mapped at probe */
  53. #define ATT_OWN BIT(1)
  54. /* address translation table */
  55. struct imx_rproc_att {
  56. u32 da; /* device address (From Cortex M4 view)*/
  57. u32 sa; /* system bus address */
  58. u32 size; /* size of reg range */
  59. int flags;
  60. };
  61. struct imx_rproc_dcfg {
  62. u32 src_reg;
  63. u32 src_mask;
  64. u32 src_start;
  65. u32 src_stop;
  66. const struct imx_rproc_att *att;
  67. size_t att_size;
  68. };
  69. struct imx_rproc {
  70. struct device *dev;
  71. struct regmap *regmap;
  72. struct rproc *rproc;
  73. const struct imx_rproc_dcfg *dcfg;
  74. struct imx_rproc_mem mem[IMX7D_RPROC_MEM_MAX];
  75. struct clk *clk;
  76. };
  77. static const struct imx_rproc_att imx_rproc_att_imx7d[] = {
  78. /* dev addr , sys addr , size , flags */
  79. /* OCRAM_S (M4 Boot code) - alias */
  80. { 0x00000000, 0x00180000, 0x00008000, 0 },
  81. /* OCRAM_S (Code) */
  82. { 0x00180000, 0x00180000, 0x00008000, ATT_OWN },
  83. /* OCRAM (Code) - alias */
  84. { 0x00900000, 0x00900000, 0x00020000, 0 },
  85. /* OCRAM_EPDC (Code) - alias */
  86. { 0x00920000, 0x00920000, 0x00020000, 0 },
  87. /* OCRAM_PXP (Code) - alias */
  88. { 0x00940000, 0x00940000, 0x00008000, 0 },
  89. /* TCML (Code) */
  90. { 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
  91. /* DDR (Code) - alias, first part of DDR (Data) */
  92. { 0x10000000, 0x80000000, 0x0FFF0000, 0 },
  93. /* TCMU (Data) */
  94. { 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
  95. /* OCRAM (Data) */
  96. { 0x20200000, 0x00900000, 0x00020000, 0 },
  97. /* OCRAM_EPDC (Data) */
  98. { 0x20220000, 0x00920000, 0x00020000, 0 },
  99. /* OCRAM_PXP (Data) */
  100. { 0x20240000, 0x00940000, 0x00008000, 0 },
  101. /* DDR (Data) */
  102. { 0x80000000, 0x80000000, 0x60000000, 0 },
  103. };
  104. static const struct imx_rproc_att imx_rproc_att_imx6sx[] = {
  105. /* dev addr , sys addr , size , flags */
  106. /* TCML (M4 Boot Code) - alias */
  107. { 0x00000000, 0x007F8000, 0x00008000, 0 },
  108. /* OCRAM_S (Code) */
  109. { 0x00180000, 0x008F8000, 0x00004000, 0 },
  110. /* OCRAM_S (Code) - alias */
  111. { 0x00180000, 0x008FC000, 0x00004000, 0 },
  112. /* TCML (Code) */
  113. { 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
  114. /* DDR (Code) - alias, first part of DDR (Data) */
  115. { 0x10000000, 0x80000000, 0x0FFF8000, 0 },
  116. /* TCMU (Data) */
  117. { 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
  118. /* OCRAM_S (Data) - alias? */
  119. { 0x208F8000, 0x008F8000, 0x00004000, 0 },
  120. /* DDR (Data) */
  121. { 0x80000000, 0x80000000, 0x60000000, 0 },
  122. };
  123. static const struct imx_rproc_dcfg imx_rproc_cfg_imx7d = {
  124. .src_reg = IMX7D_SRC_SCR,
  125. .src_mask = IMX7D_M4_RST_MASK,
  126. .src_start = IMX7D_M4_START,
  127. .src_stop = IMX7D_M4_STOP,
  128. .att = imx_rproc_att_imx7d,
  129. .att_size = ARRAY_SIZE(imx_rproc_att_imx7d),
  130. };
  131. static const struct imx_rproc_dcfg imx_rproc_cfg_imx6sx = {
  132. .src_reg = IMX6SX_SRC_SCR,
  133. .src_mask = IMX6SX_M4_RST_MASK,
  134. .src_start = IMX6SX_M4_START,
  135. .src_stop = IMX6SX_M4_STOP,
  136. .att = imx_rproc_att_imx6sx,
  137. .att_size = ARRAY_SIZE(imx_rproc_att_imx6sx),
  138. };
  139. static int imx_rproc_start(struct rproc *rproc)
  140. {
  141. struct imx_rproc *priv = rproc->priv;
  142. const struct imx_rproc_dcfg *dcfg = priv->dcfg;
  143. struct device *dev = priv->dev;
  144. int ret;
  145. ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
  146. dcfg->src_mask, dcfg->src_start);
  147. if (ret)
  148. dev_err(dev, "Failed to enable M4!\n");
  149. return ret;
  150. }
  151. static int imx_rproc_stop(struct rproc *rproc)
  152. {
  153. struct imx_rproc *priv = rproc->priv;
  154. const struct imx_rproc_dcfg *dcfg = priv->dcfg;
  155. struct device *dev = priv->dev;
  156. int ret;
  157. ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
  158. dcfg->src_mask, dcfg->src_stop);
  159. if (ret)
  160. dev_err(dev, "Failed to stop M4!\n");
  161. return ret;
  162. }
  163. static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da,
  164. size_t len, u64 *sys)
  165. {
  166. const struct imx_rproc_dcfg *dcfg = priv->dcfg;
  167. int i;
  168. /* parse address translation table */
  169. for (i = 0; i < dcfg->att_size; i++) {
  170. const struct imx_rproc_att *att = &dcfg->att[i];
  171. if (da >= att->da && da + len < att->da + att->size) {
  172. unsigned int offset = da - att->da;
  173. *sys = att->sa + offset;
  174. return 0;
  175. }
  176. }
  177. dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n",
  178. da, len);
  179. return -ENOENT;
  180. }
  181. static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
  182. {
  183. struct imx_rproc *priv = rproc->priv;
  184. void *va = NULL;
  185. u64 sys;
  186. int i;
  187. if (len == 0)
  188. return NULL;
  189. /*
  190. * On device side we have many aliases, so we need to convert device
  191. * address (M4) to system bus address first.
  192. */
  193. if (imx_rproc_da_to_sys(priv, da, len, &sys))
  194. return NULL;
  195. for (i = 0; i < IMX7D_RPROC_MEM_MAX; i++) {
  196. if (sys >= priv->mem[i].sys_addr && sys + len <
  197. priv->mem[i].sys_addr + priv->mem[i].size) {
  198. unsigned int offset = sys - priv->mem[i].sys_addr;
  199. /* __force to make sparse happy with type conversion */
  200. va = (__force void *)(priv->mem[i].cpu_addr + offset);
  201. break;
  202. }
  203. }
  204. dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n",
  205. da, len, va);
  206. return va;
  207. }
  208. static const struct rproc_ops imx_rproc_ops = {
  209. .start = imx_rproc_start,
  210. .stop = imx_rproc_stop,
  211. .da_to_va = imx_rproc_da_to_va,
  212. };
  213. static int imx_rproc_addr_init(struct imx_rproc *priv,
  214. struct platform_device *pdev)
  215. {
  216. const struct imx_rproc_dcfg *dcfg = priv->dcfg;
  217. struct device *dev = &pdev->dev;
  218. struct device_node *np = dev->of_node;
  219. int a, b = 0, err, nph;
  220. /* remap required addresses */
  221. for (a = 0; a < dcfg->att_size; a++) {
  222. const struct imx_rproc_att *att = &dcfg->att[a];
  223. if (!(att->flags & ATT_OWN))
  224. continue;
  225. if (b >= IMX7D_RPROC_MEM_MAX)
  226. break;
  227. priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev,
  228. att->sa, att->size);
  229. if (!priv->mem[b].cpu_addr) {
  230. dev_err(dev, "devm_ioremap_resource failed\n");
  231. return -ENOMEM;
  232. }
  233. priv->mem[b].sys_addr = att->sa;
  234. priv->mem[b].size = att->size;
  235. b++;
  236. }
  237. /* memory-region is optional property */
  238. nph = of_count_phandle_with_args(np, "memory-region", NULL);
  239. if (nph <= 0)
  240. return 0;
  241. /* remap optional addresses */
  242. for (a = 0; a < nph; a++) {
  243. struct device_node *node;
  244. struct resource res;
  245. node = of_parse_phandle(np, "memory-region", a);
  246. err = of_address_to_resource(node, 0, &res);
  247. if (err) {
  248. dev_err(dev, "unable to resolve memory region\n");
  249. return err;
  250. }
  251. if (b >= IMX7D_RPROC_MEM_MAX)
  252. break;
  253. priv->mem[b].cpu_addr = devm_ioremap_resource(&pdev->dev, &res);
  254. if (IS_ERR(priv->mem[b].cpu_addr)) {
  255. dev_err(dev, "devm_ioremap_resource failed\n");
  256. err = PTR_ERR(priv->mem[b].cpu_addr);
  257. return err;
  258. }
  259. priv->mem[b].sys_addr = res.start;
  260. priv->mem[b].size = resource_size(&res);
  261. b++;
  262. }
  263. return 0;
  264. }
  265. static int imx_rproc_probe(struct platform_device *pdev)
  266. {
  267. struct device *dev = &pdev->dev;
  268. struct device_node *np = dev->of_node;
  269. struct imx_rproc *priv;
  270. struct rproc *rproc;
  271. struct regmap_config config = { .name = "imx-rproc" };
  272. const struct imx_rproc_dcfg *dcfg;
  273. struct regmap *regmap;
  274. int ret;
  275. regmap = syscon_regmap_lookup_by_phandle(np, "syscon");
  276. if (IS_ERR(regmap)) {
  277. dev_err(dev, "failed to find syscon\n");
  278. return PTR_ERR(regmap);
  279. }
  280. regmap_attach_dev(dev, regmap, &config);
  281. /* set some other name then imx */
  282. rproc = rproc_alloc(dev, "imx-rproc", &imx_rproc_ops,
  283. NULL, sizeof(*priv));
  284. if (!rproc)
  285. return -ENOMEM;
  286. dcfg = of_device_get_match_data(dev);
  287. if (!dcfg) {
  288. ret = -EINVAL;
  289. goto err_put_rproc;
  290. }
  291. priv = rproc->priv;
  292. priv->rproc = rproc;
  293. priv->regmap = regmap;
  294. priv->dcfg = dcfg;
  295. priv->dev = dev;
  296. dev_set_drvdata(dev, rproc);
  297. ret = imx_rproc_addr_init(priv, pdev);
  298. if (ret) {
  299. dev_err(dev, "failed on imx_rproc_addr_init\n");
  300. goto err_put_rproc;
  301. }
  302. priv->clk = devm_clk_get(dev, NULL);
  303. if (IS_ERR(priv->clk)) {
  304. dev_err(dev, "Failed to get clock\n");
  305. ret = PTR_ERR(priv->clk);
  306. goto err_put_rproc;
  307. }
  308. /*
  309. * clk for M4 block including memory. Should be
  310. * enabled before .start for FW transfer.
  311. */
  312. ret = clk_prepare_enable(priv->clk);
  313. if (ret) {
  314. dev_err(&rproc->dev, "Failed to enable clock\n");
  315. goto err_put_rproc;
  316. }
  317. ret = rproc_add(rproc);
  318. if (ret) {
  319. dev_err(dev, "rproc_add failed\n");
  320. goto err_put_clk;
  321. }
  322. return 0;
  323. err_put_clk:
  324. clk_disable_unprepare(priv->clk);
  325. err_put_rproc:
  326. rproc_free(rproc);
  327. return ret;
  328. }
  329. static int imx_rproc_remove(struct platform_device *pdev)
  330. {
  331. struct rproc *rproc = platform_get_drvdata(pdev);
  332. struct imx_rproc *priv = rproc->priv;
  333. clk_disable_unprepare(priv->clk);
  334. rproc_del(rproc);
  335. rproc_free(rproc);
  336. return 0;
  337. }
  338. static const struct of_device_id imx_rproc_of_match[] = {
  339. { .compatible = "fsl,imx7d-cm4", .data = &imx_rproc_cfg_imx7d },
  340. { .compatible = "fsl,imx6sx-cm4", .data = &imx_rproc_cfg_imx6sx },
  341. {},
  342. };
  343. MODULE_DEVICE_TABLE(of, imx_rproc_of_match);
  344. static struct platform_driver imx_rproc_driver = {
  345. .probe = imx_rproc_probe,
  346. .remove = imx_rproc_remove,
  347. .driver = {
  348. .name = "imx-rproc",
  349. .of_match_table = imx_rproc_of_match,
  350. },
  351. };
  352. module_platform_driver(imx_rproc_driver);
  353. MODULE_LICENSE("GPL v2");
  354. MODULE_DESCRIPTION("IMX6SX/7D remote processor control driver");
  355. MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");