slg51000-regulator.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // SLG51000 High PSRR, Multi-Output Regulators
  4. // Copyright (C) 2019 Dialog Semiconductor
  5. //
  6. // Author: Eric Jeong <eric.jeong.opensource@diasemi.com>
  7. #include <linux/err.h>
  8. #include <linux/gpio/consumer.h>
  9. #include <linux/i2c.h>
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/irq.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/regmap.h>
  16. #include <linux/regulator/driver.h>
  17. #include <linux/regulator/machine.h>
  18. #include <linux/regulator/of_regulator.h>
  19. #include "slg51000-regulator.h"
  20. #define SLG51000_SCTL_EVT 7
  21. #define SLG51000_MAX_EVT_REGISTER 8
  22. #define SLG51000_LDOHP_LV_MIN 1200000
  23. #define SLG51000_LDOHP_HV_MIN 2400000
  24. enum slg51000_regulators {
  25. SLG51000_REGULATOR_LDO1 = 0,
  26. SLG51000_REGULATOR_LDO2,
  27. SLG51000_REGULATOR_LDO3,
  28. SLG51000_REGULATOR_LDO4,
  29. SLG51000_REGULATOR_LDO5,
  30. SLG51000_REGULATOR_LDO6,
  31. SLG51000_REGULATOR_LDO7,
  32. SLG51000_MAX_REGULATORS,
  33. };
  34. struct slg51000 {
  35. struct device *dev;
  36. struct regmap *regmap;
  37. struct regulator_desc *rdesc[SLG51000_MAX_REGULATORS];
  38. struct regulator_dev *rdev[SLG51000_MAX_REGULATORS];
  39. struct gpio_desc *cs_gpiod;
  40. int chip_irq;
  41. };
  42. struct slg51000_evt_sta {
  43. unsigned int ereg;
  44. unsigned int sreg;
  45. };
  46. static const struct slg51000_evt_sta es_reg[SLG51000_MAX_EVT_REGISTER] = {
  47. {SLG51000_LDO1_EVENT, SLG51000_LDO1_STATUS},
  48. {SLG51000_LDO2_EVENT, SLG51000_LDO2_STATUS},
  49. {SLG51000_LDO3_EVENT, SLG51000_LDO3_STATUS},
  50. {SLG51000_LDO4_EVENT, SLG51000_LDO4_STATUS},
  51. {SLG51000_LDO5_EVENT, SLG51000_LDO5_STATUS},
  52. {SLG51000_LDO6_EVENT, SLG51000_LDO6_STATUS},
  53. {SLG51000_LDO7_EVENT, SLG51000_LDO7_STATUS},
  54. {SLG51000_SYSCTL_EVENT, SLG51000_SYSCTL_STATUS},
  55. };
  56. static const struct regmap_range slg51000_writeable_ranges[] = {
  57. regmap_reg_range(SLG51000_SYSCTL_MATRIX_CONF_A,
  58. SLG51000_SYSCTL_MATRIX_CONF_A),
  59. regmap_reg_range(SLG51000_LDO1_VSEL, SLG51000_LDO1_VSEL),
  60. regmap_reg_range(SLG51000_LDO1_MINV, SLG51000_LDO1_MAXV),
  61. regmap_reg_range(SLG51000_LDO1_IRQ_MASK, SLG51000_LDO1_IRQ_MASK),
  62. regmap_reg_range(SLG51000_LDO2_VSEL, SLG51000_LDO2_VSEL),
  63. regmap_reg_range(SLG51000_LDO2_MINV, SLG51000_LDO2_MAXV),
  64. regmap_reg_range(SLG51000_LDO2_IRQ_MASK, SLG51000_LDO2_IRQ_MASK),
  65. regmap_reg_range(SLG51000_LDO3_VSEL, SLG51000_LDO3_VSEL),
  66. regmap_reg_range(SLG51000_LDO3_MINV, SLG51000_LDO3_MAXV),
  67. regmap_reg_range(SLG51000_LDO3_IRQ_MASK, SLG51000_LDO3_IRQ_MASK),
  68. regmap_reg_range(SLG51000_LDO4_VSEL, SLG51000_LDO4_VSEL),
  69. regmap_reg_range(SLG51000_LDO4_MINV, SLG51000_LDO4_MAXV),
  70. regmap_reg_range(SLG51000_LDO4_IRQ_MASK, SLG51000_LDO4_IRQ_MASK),
  71. regmap_reg_range(SLG51000_LDO5_VSEL, SLG51000_LDO5_VSEL),
  72. regmap_reg_range(SLG51000_LDO5_MINV, SLG51000_LDO5_MAXV),
  73. regmap_reg_range(SLG51000_LDO5_IRQ_MASK, SLG51000_LDO5_IRQ_MASK),
  74. regmap_reg_range(SLG51000_LDO6_VSEL, SLG51000_LDO6_VSEL),
  75. regmap_reg_range(SLG51000_LDO6_MINV, SLG51000_LDO6_MAXV),
  76. regmap_reg_range(SLG51000_LDO6_IRQ_MASK, SLG51000_LDO6_IRQ_MASK),
  77. regmap_reg_range(SLG51000_LDO7_VSEL, SLG51000_LDO7_VSEL),
  78. regmap_reg_range(SLG51000_LDO7_MINV, SLG51000_LDO7_MAXV),
  79. regmap_reg_range(SLG51000_LDO7_IRQ_MASK, SLG51000_LDO7_IRQ_MASK),
  80. regmap_reg_range(SLG51000_OTP_IRQ_MASK, SLG51000_OTP_IRQ_MASK),
  81. };
  82. static const struct regmap_range slg51000_readable_ranges[] = {
  83. regmap_reg_range(SLG51000_SYSCTL_PATN_ID_B0,
  84. SLG51000_SYSCTL_PATN_ID_B2),
  85. regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_A,
  86. SLG51000_SYSCTL_SYS_CONF_A),
  87. regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_D,
  88. SLG51000_SYSCTL_MATRIX_CONF_B),
  89. regmap_reg_range(SLG51000_SYSCTL_REFGEN_CONF_C,
  90. SLG51000_SYSCTL_UVLO_CONF_A),
  91. regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1, SLG51000_SYSCTL_IRQ_MASK),
  92. regmap_reg_range(SLG51000_IO_GPIO1_CONF, SLG51000_IO_GPIO_STATUS),
  93. regmap_reg_range(SLG51000_LUTARRAY_LUT_VAL_0,
  94. SLG51000_LUTARRAY_LUT_VAL_11),
  95. regmap_reg_range(SLG51000_MUXARRAY_INPUT_SEL_0,
  96. SLG51000_MUXARRAY_INPUT_SEL_63),
  97. regmap_reg_range(SLG51000_PWRSEQ_RESOURCE_EN_0,
  98. SLG51000_PWRSEQ_INPUT_SENSE_CONF_B),
  99. regmap_reg_range(SLG51000_LDO1_VSEL, SLG51000_LDO1_VSEL),
  100. regmap_reg_range(SLG51000_LDO1_MINV, SLG51000_LDO1_MAXV),
  101. regmap_reg_range(SLG51000_LDO1_MISC1, SLG51000_LDO1_VSEL_ACTUAL),
  102. regmap_reg_range(SLG51000_LDO1_EVENT, SLG51000_LDO1_IRQ_MASK),
  103. regmap_reg_range(SLG51000_LDO2_VSEL, SLG51000_LDO2_VSEL),
  104. regmap_reg_range(SLG51000_LDO2_MINV, SLG51000_LDO2_MAXV),
  105. regmap_reg_range(SLG51000_LDO2_MISC1, SLG51000_LDO2_VSEL_ACTUAL),
  106. regmap_reg_range(SLG51000_LDO2_EVENT, SLG51000_LDO2_IRQ_MASK),
  107. regmap_reg_range(SLG51000_LDO3_VSEL, SLG51000_LDO3_VSEL),
  108. regmap_reg_range(SLG51000_LDO3_MINV, SLG51000_LDO3_MAXV),
  109. regmap_reg_range(SLG51000_LDO3_CONF1, SLG51000_LDO3_VSEL_ACTUAL),
  110. regmap_reg_range(SLG51000_LDO3_EVENT, SLG51000_LDO3_IRQ_MASK),
  111. regmap_reg_range(SLG51000_LDO4_VSEL, SLG51000_LDO4_VSEL),
  112. regmap_reg_range(SLG51000_LDO4_MINV, SLG51000_LDO4_MAXV),
  113. regmap_reg_range(SLG51000_LDO4_CONF1, SLG51000_LDO4_VSEL_ACTUAL),
  114. regmap_reg_range(SLG51000_LDO4_EVENT, SLG51000_LDO4_IRQ_MASK),
  115. regmap_reg_range(SLG51000_LDO5_VSEL, SLG51000_LDO5_VSEL),
  116. regmap_reg_range(SLG51000_LDO5_MINV, SLG51000_LDO5_MAXV),
  117. regmap_reg_range(SLG51000_LDO5_TRIM2, SLG51000_LDO5_TRIM2),
  118. regmap_reg_range(SLG51000_LDO5_CONF1, SLG51000_LDO5_VSEL_ACTUAL),
  119. regmap_reg_range(SLG51000_LDO5_EVENT, SLG51000_LDO5_IRQ_MASK),
  120. regmap_reg_range(SLG51000_LDO6_VSEL, SLG51000_LDO6_VSEL),
  121. regmap_reg_range(SLG51000_LDO6_MINV, SLG51000_LDO6_MAXV),
  122. regmap_reg_range(SLG51000_LDO6_TRIM2, SLG51000_LDO6_TRIM2),
  123. regmap_reg_range(SLG51000_LDO6_CONF1, SLG51000_LDO6_VSEL_ACTUAL),
  124. regmap_reg_range(SLG51000_LDO6_EVENT, SLG51000_LDO6_IRQ_MASK),
  125. regmap_reg_range(SLG51000_LDO7_VSEL, SLG51000_LDO7_VSEL),
  126. regmap_reg_range(SLG51000_LDO7_MINV, SLG51000_LDO7_MAXV),
  127. regmap_reg_range(SLG51000_LDO7_CONF1, SLG51000_LDO7_VSEL_ACTUAL),
  128. regmap_reg_range(SLG51000_LDO7_EVENT, SLG51000_LDO7_IRQ_MASK),
  129. regmap_reg_range(SLG51000_OTP_EVENT, SLG51000_OTP_EVENT),
  130. regmap_reg_range(SLG51000_OTP_IRQ_MASK, SLG51000_OTP_IRQ_MASK),
  131. regmap_reg_range(SLG51000_OTP_LOCK_OTP_PROG, SLG51000_OTP_LOCK_CTRL),
  132. regmap_reg_range(SLG51000_LOCK_GLOBAL_LOCK_CTRL1,
  133. SLG51000_LOCK_GLOBAL_LOCK_CTRL1),
  134. };
  135. static const struct regmap_range slg51000_volatile_ranges[] = {
  136. regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1, SLG51000_SYSCTL_STATUS),
  137. regmap_reg_range(SLG51000_IO_GPIO_STATUS, SLG51000_IO_GPIO_STATUS),
  138. regmap_reg_range(SLG51000_LDO1_EVENT, SLG51000_LDO1_STATUS),
  139. regmap_reg_range(SLG51000_LDO2_EVENT, SLG51000_LDO2_STATUS),
  140. regmap_reg_range(SLG51000_LDO3_EVENT, SLG51000_LDO3_STATUS),
  141. regmap_reg_range(SLG51000_LDO4_EVENT, SLG51000_LDO4_STATUS),
  142. regmap_reg_range(SLG51000_LDO5_EVENT, SLG51000_LDO5_STATUS),
  143. regmap_reg_range(SLG51000_LDO6_EVENT, SLG51000_LDO6_STATUS),
  144. regmap_reg_range(SLG51000_LDO7_EVENT, SLG51000_LDO7_STATUS),
  145. regmap_reg_range(SLG51000_OTP_EVENT, SLG51000_OTP_EVENT),
  146. };
  147. static const struct regmap_access_table slg51000_writeable_table = {
  148. .yes_ranges = slg51000_writeable_ranges,
  149. .n_yes_ranges = ARRAY_SIZE(slg51000_writeable_ranges),
  150. };
  151. static const struct regmap_access_table slg51000_readable_table = {
  152. .yes_ranges = slg51000_readable_ranges,
  153. .n_yes_ranges = ARRAY_SIZE(slg51000_readable_ranges),
  154. };
  155. static const struct regmap_access_table slg51000_volatile_table = {
  156. .yes_ranges = slg51000_volatile_ranges,
  157. .n_yes_ranges = ARRAY_SIZE(slg51000_volatile_ranges),
  158. };
  159. static const struct regmap_config slg51000_regmap_config = {
  160. .reg_bits = 16,
  161. .val_bits = 8,
  162. .max_register = 0x8000,
  163. .wr_table = &slg51000_writeable_table,
  164. .rd_table = &slg51000_readable_table,
  165. .volatile_table = &slg51000_volatile_table,
  166. };
  167. static const struct regulator_ops slg51000_regl_ops = {
  168. .enable = regulator_enable_regmap,
  169. .disable = regulator_disable_regmap,
  170. .is_enabled = regulator_is_enabled_regmap,
  171. .list_voltage = regulator_list_voltage_linear,
  172. .map_voltage = regulator_map_voltage_linear,
  173. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  174. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  175. };
  176. static const struct regulator_ops slg51000_switch_ops = {
  177. .enable = regulator_enable_regmap,
  178. .disable = regulator_disable_regmap,
  179. .is_enabled = regulator_is_enabled_regmap,
  180. };
  181. static int slg51000_of_parse_cb(struct device_node *np,
  182. const struct regulator_desc *desc,
  183. struct regulator_config *config)
  184. {
  185. struct gpio_desc *ena_gpiod;
  186. ena_gpiod = fwnode_gpiod_get_index(of_fwnode_handle(np), "enable", 0,
  187. GPIOD_OUT_LOW |
  188. GPIOD_FLAGS_BIT_NONEXCLUSIVE,
  189. "gpio-en-ldo");
  190. if (!IS_ERR(ena_gpiod))
  191. config->ena_gpiod = ena_gpiod;
  192. return 0;
  193. }
  194. #define SLG51000_REGL_DESC(_id, _name, _s_name, _min, _step) \
  195. [SLG51000_REGULATOR_##_id] = { \
  196. .name = #_name, \
  197. .supply_name = _s_name, \
  198. .id = SLG51000_REGULATOR_##_id, \
  199. .of_match = of_match_ptr(#_name), \
  200. .of_parse_cb = slg51000_of_parse_cb, \
  201. .ops = &slg51000_regl_ops, \
  202. .regulators_node = of_match_ptr("regulators"), \
  203. .n_voltages = 256, \
  204. .min_uV = _min, \
  205. .uV_step = _step, \
  206. .linear_min_sel = 0, \
  207. .vsel_mask = SLG51000_VSEL_MASK, \
  208. .vsel_reg = SLG51000_##_id##_VSEL, \
  209. .enable_reg = SLG51000_SYSCTL_MATRIX_CONF_A, \
  210. .enable_mask = BIT(SLG51000_REGULATOR_##_id), \
  211. .type = REGULATOR_VOLTAGE, \
  212. .owner = THIS_MODULE, \
  213. }
  214. static struct regulator_desc regls_desc[SLG51000_MAX_REGULATORS] = {
  215. SLG51000_REGL_DESC(LDO1, ldo1, NULL, 2400000, 5000),
  216. SLG51000_REGL_DESC(LDO2, ldo2, NULL, 2400000, 5000),
  217. SLG51000_REGL_DESC(LDO3, ldo3, "vin3", 1200000, 10000),
  218. SLG51000_REGL_DESC(LDO4, ldo4, "vin4", 1200000, 10000),
  219. SLG51000_REGL_DESC(LDO5, ldo5, "vin5", 400000, 5000),
  220. SLG51000_REGL_DESC(LDO6, ldo6, "vin6", 400000, 5000),
  221. SLG51000_REGL_DESC(LDO7, ldo7, "vin7", 1200000, 10000),
  222. };
  223. static int slg51000_regulator_init(struct slg51000 *chip)
  224. {
  225. struct regulator_config config = { };
  226. struct regulator_desc *rdesc;
  227. unsigned int reg, val;
  228. u8 vsel_range[2];
  229. int id, ret = 0;
  230. const unsigned int min_regs[SLG51000_MAX_REGULATORS] = {
  231. SLG51000_LDO1_MINV, SLG51000_LDO2_MINV, SLG51000_LDO3_MINV,
  232. SLG51000_LDO4_MINV, SLG51000_LDO5_MINV, SLG51000_LDO6_MINV,
  233. SLG51000_LDO7_MINV,
  234. };
  235. for (id = 0; id < SLG51000_MAX_REGULATORS; id++) {
  236. chip->rdesc[id] = &regls_desc[id];
  237. rdesc = chip->rdesc[id];
  238. config.regmap = chip->regmap;
  239. config.dev = chip->dev;
  240. config.driver_data = chip;
  241. ret = regmap_bulk_read(chip->regmap, min_regs[id],
  242. vsel_range, 2);
  243. if (ret < 0) {
  244. dev_err(chip->dev,
  245. "Failed to read the MIN register\n");
  246. return ret;
  247. }
  248. switch (id) {
  249. case SLG51000_REGULATOR_LDO1:
  250. case SLG51000_REGULATOR_LDO2:
  251. if (id == SLG51000_REGULATOR_LDO1)
  252. reg = SLG51000_LDO1_MISC1;
  253. else
  254. reg = SLG51000_LDO2_MISC1;
  255. ret = regmap_read(chip->regmap, reg, &val);
  256. if (ret < 0) {
  257. dev_err(chip->dev,
  258. "Failed to read voltage range of ldo%d\n",
  259. id + 1);
  260. return ret;
  261. }
  262. rdesc->linear_min_sel = vsel_range[0];
  263. rdesc->n_voltages = vsel_range[1] + 1;
  264. if (val & SLG51000_SEL_VRANGE_MASK)
  265. rdesc->min_uV = SLG51000_LDOHP_HV_MIN
  266. + (vsel_range[0]
  267. * rdesc->uV_step);
  268. else
  269. rdesc->min_uV = SLG51000_LDOHP_LV_MIN
  270. + (vsel_range[0]
  271. * rdesc->uV_step);
  272. break;
  273. case SLG51000_REGULATOR_LDO5:
  274. case SLG51000_REGULATOR_LDO6:
  275. if (id == SLG51000_REGULATOR_LDO5)
  276. reg = SLG51000_LDO5_TRIM2;
  277. else
  278. reg = SLG51000_LDO6_TRIM2;
  279. ret = regmap_read(chip->regmap, reg, &val);
  280. if (ret < 0) {
  281. dev_err(chip->dev,
  282. "Failed to read LDO mode register\n");
  283. return ret;
  284. }
  285. if (val & SLG51000_SEL_BYP_MODE_MASK) {
  286. rdesc->ops = &slg51000_switch_ops;
  287. rdesc->n_voltages = 0;
  288. rdesc->min_uV = 0;
  289. rdesc->uV_step = 0;
  290. rdesc->linear_min_sel = 0;
  291. break;
  292. }
  293. fallthrough; /* to the check below */
  294. default:
  295. rdesc->linear_min_sel = vsel_range[0];
  296. rdesc->n_voltages = vsel_range[1] + 1;
  297. rdesc->min_uV = rdesc->min_uV
  298. + (vsel_range[0] * rdesc->uV_step);
  299. break;
  300. }
  301. chip->rdev[id] = devm_regulator_register(chip->dev, rdesc,
  302. &config);
  303. if (IS_ERR(chip->rdev[id])) {
  304. ret = PTR_ERR(chip->rdev[id]);
  305. dev_err(chip->dev,
  306. "Failed to register regulator(%s):%d\n",
  307. chip->rdesc[id]->name, ret);
  308. return ret;
  309. }
  310. }
  311. return 0;
  312. }
  313. static irqreturn_t slg51000_irq_handler(int irq, void *data)
  314. {
  315. struct slg51000 *chip = data;
  316. struct regmap *regmap = chip->regmap;
  317. enum { R0 = 0, R1, R2, REG_MAX };
  318. u8 evt[SLG51000_MAX_EVT_REGISTER][REG_MAX];
  319. int ret, i, handled = IRQ_NONE;
  320. unsigned int evt_otp, mask_otp;
  321. /* Read event[R0], status[R1] and mask[R2] register */
  322. for (i = 0; i < SLG51000_MAX_EVT_REGISTER; i++) {
  323. ret = regmap_bulk_read(regmap, es_reg[i].ereg, evt[i], REG_MAX);
  324. if (ret < 0) {
  325. dev_err(chip->dev,
  326. "Failed to read event registers(%d)\n", ret);
  327. return IRQ_NONE;
  328. }
  329. }
  330. ret = regmap_read(regmap, SLG51000_OTP_EVENT, &evt_otp);
  331. if (ret < 0) {
  332. dev_err(chip->dev,
  333. "Failed to read otp event registers(%d)\n", ret);
  334. return IRQ_NONE;
  335. }
  336. ret = regmap_read(regmap, SLG51000_OTP_IRQ_MASK, &mask_otp);
  337. if (ret < 0) {
  338. dev_err(chip->dev,
  339. "Failed to read otp mask register(%d)\n", ret);
  340. return IRQ_NONE;
  341. }
  342. if ((evt_otp & SLG51000_EVT_CRC_MASK) &&
  343. !(mask_otp & SLG51000_IRQ_CRC_MASK)) {
  344. dev_info(chip->dev,
  345. "OTP has been read or OTP crc is not zero\n");
  346. handled = IRQ_HANDLED;
  347. }
  348. for (i = 0; i < SLG51000_MAX_REGULATORS; i++) {
  349. if (!(evt[i][R2] & SLG51000_IRQ_ILIM_FLAG_MASK) &&
  350. (evt[i][R0] & SLG51000_EVT_ILIM_FLAG_MASK)) {
  351. regulator_notifier_call_chain(chip->rdev[i],
  352. REGULATOR_EVENT_OVER_CURRENT, NULL);
  353. if (evt[i][R1] & SLG51000_STA_ILIM_FLAG_MASK)
  354. dev_warn(chip->dev,
  355. "Over-current limit(ldo%d)\n", i + 1);
  356. handled = IRQ_HANDLED;
  357. }
  358. }
  359. if (!(evt[SLG51000_SCTL_EVT][R2] & SLG51000_IRQ_HIGH_TEMP_WARN_MASK) &&
  360. (evt[SLG51000_SCTL_EVT][R0] & SLG51000_EVT_HIGH_TEMP_WARN_MASK)) {
  361. for (i = 0; i < SLG51000_MAX_REGULATORS; i++) {
  362. if (!(evt[i][R1] & SLG51000_STA_ILIM_FLAG_MASK) &&
  363. (evt[i][R1] & SLG51000_STA_VOUT_OK_FLAG_MASK)) {
  364. regulator_notifier_call_chain(chip->rdev[i],
  365. REGULATOR_EVENT_OVER_TEMP, NULL);
  366. }
  367. }
  368. handled = IRQ_HANDLED;
  369. if (evt[SLG51000_SCTL_EVT][R1] &
  370. SLG51000_STA_HIGH_TEMP_WARN_MASK)
  371. dev_warn(chip->dev, "High temperature warning!\n");
  372. }
  373. return handled;
  374. }
  375. static void slg51000_clear_fault_log(struct slg51000 *chip)
  376. {
  377. unsigned int val = 0;
  378. int ret = 0;
  379. ret = regmap_read(chip->regmap, SLG51000_SYSCTL_FAULT_LOG1, &val);
  380. if (ret < 0) {
  381. dev_err(chip->dev, "Failed to read Fault log register\n");
  382. return;
  383. }
  384. if (val & SLG51000_FLT_OVER_TEMP_MASK)
  385. dev_dbg(chip->dev, "Fault log: FLT_OVER_TEMP\n");
  386. if (val & SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK)
  387. dev_dbg(chip->dev, "Fault log: FLT_POWER_SEQ_CRASH_REQ\n");
  388. if (val & SLG51000_FLT_RST_MASK)
  389. dev_dbg(chip->dev, "Fault log: FLT_RST\n");
  390. if (val & SLG51000_FLT_POR_MASK)
  391. dev_dbg(chip->dev, "Fault log: FLT_POR\n");
  392. }
  393. static int slg51000_i2c_probe(struct i2c_client *client)
  394. {
  395. struct device *dev = &client->dev;
  396. struct slg51000 *chip;
  397. struct gpio_desc *cs_gpiod;
  398. int error, ret;
  399. chip = devm_kzalloc(dev, sizeof(struct slg51000), GFP_KERNEL);
  400. if (!chip)
  401. return -ENOMEM;
  402. cs_gpiod = devm_gpiod_get_optional(dev, "dlg,cs",
  403. GPIOD_OUT_HIGH |
  404. GPIOD_FLAGS_BIT_NONEXCLUSIVE);
  405. if (IS_ERR(cs_gpiod))
  406. return PTR_ERR(cs_gpiod);
  407. if (cs_gpiod) {
  408. dev_info(dev, "Found chip selector property\n");
  409. chip->cs_gpiod = cs_gpiod;
  410. }
  411. i2c_set_clientdata(client, chip);
  412. chip->chip_irq = client->irq;
  413. chip->dev = dev;
  414. chip->regmap = devm_regmap_init_i2c(client, &slg51000_regmap_config);
  415. if (IS_ERR(chip->regmap)) {
  416. error = PTR_ERR(chip->regmap);
  417. dev_err(dev, "Failed to allocate register map: %d\n",
  418. error);
  419. return error;
  420. }
  421. ret = slg51000_regulator_init(chip);
  422. if (ret < 0) {
  423. dev_err(chip->dev, "Failed to init regulator(%d)\n", ret);
  424. return ret;
  425. }
  426. slg51000_clear_fault_log(chip);
  427. if (chip->chip_irq) {
  428. ret = devm_request_threaded_irq(dev, chip->chip_irq, NULL,
  429. slg51000_irq_handler,
  430. (IRQF_TRIGGER_HIGH |
  431. IRQF_ONESHOT),
  432. "slg51000-irq", chip);
  433. if (ret != 0) {
  434. dev_err(dev, "Failed to request IRQ: %d\n",
  435. chip->chip_irq);
  436. return ret;
  437. }
  438. } else {
  439. dev_info(dev, "No IRQ configured\n");
  440. }
  441. return ret;
  442. }
  443. static const struct i2c_device_id slg51000_i2c_id[] = {
  444. {"slg51000", 0},
  445. {},
  446. };
  447. MODULE_DEVICE_TABLE(i2c, slg51000_i2c_id);
  448. static struct i2c_driver slg51000_regulator_driver = {
  449. .driver = {
  450. .name = "slg51000-regulator",
  451. },
  452. .probe_new = slg51000_i2c_probe,
  453. .id_table = slg51000_i2c_id,
  454. };
  455. module_i2c_driver(slg51000_regulator_driver);
  456. MODULE_AUTHOR("Eric Jeong <eric.jeong.opensource@diasemi.com>");
  457. MODULE_DESCRIPTION("SLG51000 regulator driver");
  458. MODULE_LICENSE("GPL");