rtmv20-regulator.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <linux/delay.h>
  3. #include <linux/gpio/consumer.h>
  4. #include <linux/i2c.h>
  5. #include <linux/interrupt.h>
  6. #include <linux/kernel.h>
  7. #include <linux/module.h>
  8. #include <linux/property.h>
  9. #include <linux/regmap.h>
  10. #include <linux/regulator/driver.h>
  11. #define RTMV20_REG_DEVINFO 0x00
  12. #define RTMV20_REG_PULSEDELAY 0x01
  13. #define RTMV20_REG_PULSEWIDTH 0x03
  14. #define RTMV20_REG_LDCTRL1 0x05
  15. #define RTMV20_REG_ESPULSEWIDTH 0x06
  16. #define RTMV20_REG_ESLDCTRL1 0x08
  17. #define RTMV20_REG_LBP 0x0A
  18. #define RTMV20_REG_LDCTRL2 0x0B
  19. #define RTMV20_REG_FSIN1CTRL1 0x0D
  20. #define RTMV20_REG_FSIN1CTRL3 0x0F
  21. #define RTMV20_REG_FSIN2CTRL1 0x10
  22. #define RTMV20_REG_FSIN2CTRL3 0x12
  23. #define RTMV20_REG_ENCTRL 0x13
  24. #define RTMV20_REG_STRBVSYNDLYL 0x29
  25. #define RTMV20_REG_LDIRQ 0x30
  26. #define RTMV20_REG_LDSTAT 0x40
  27. #define RTMV20_REG_LDMASK 0x50
  28. #define RTMV20_MAX_REGS (RTMV20_REG_LDMASK + 1)
  29. #define RTMV20_VID_MASK GENMASK(7, 4)
  30. #define RICHTEK_VID 0x80
  31. #define RTMV20_LDCURR_MASK GENMASK(7, 0)
  32. #define RTMV20_DELAY_MASK GENMASK(9, 0)
  33. #define RTMV20_WIDTH_MASK GENMASK(13, 0)
  34. #define RTMV20_WIDTH2_MASK GENMASK(7, 0)
  35. #define RTMV20_LBPLVL_MASK GENMASK(3, 0)
  36. #define RTMV20_LBPEN_MASK BIT(7)
  37. #define RTMV20_STROBEPOL_MASK BIT(0)
  38. #define RTMV20_VSYNPOL_MASK BIT(1)
  39. #define RTMV20_FSINEN_MASK BIT(7)
  40. #define RTMV20_ESEN_MASK BIT(6)
  41. #define RTMV20_FSINOUT_MASK BIT(2)
  42. #define LDENABLE_MASK (BIT(3) | BIT(0))
  43. #define OTPEVT_MASK BIT(4)
  44. #define SHORTEVT_MASK BIT(3)
  45. #define OPENEVT_MASK BIT(2)
  46. #define LBPEVT_MASK BIT(1)
  47. #define OCPEVT_MASK BIT(0)
  48. #define FAILEVT_MASK (SHORTEVT_MASK | OPENEVT_MASK | LBPEVT_MASK)
  49. #define RTMV20_LSW_MINUA 0
  50. #define RTMV20_LSW_MAXUA 6000000
  51. #define RTMV20_LSW_STEPUA 30000
  52. #define RTMV20_LSW_DEFAULTUA 3000000
  53. #define RTMV20_I2CRDY_TIMEUS 200
  54. #define RTMV20_CSRDY_TIMEUS 2000
  55. struct rtmv20_priv {
  56. struct device *dev;
  57. struct regmap *regmap;
  58. struct gpio_desc *enable_gpio;
  59. struct regulator_dev *rdev;
  60. };
  61. static int rtmv20_lsw_enable(struct regulator_dev *rdev)
  62. {
  63. struct rtmv20_priv *priv = rdev_get_drvdata(rdev);
  64. int ret;
  65. gpiod_set_value(priv->enable_gpio, 1);
  66. /* Wait for I2C can be accessed */
  67. usleep_range(RTMV20_I2CRDY_TIMEUS, RTMV20_I2CRDY_TIMEUS + 100);
  68. /* HW re-enable, disable cache only and sync regcache here */
  69. regcache_cache_only(priv->regmap, false);
  70. ret = regcache_sync(priv->regmap);
  71. if (ret)
  72. return ret;
  73. return regulator_enable_regmap(rdev);
  74. }
  75. static int rtmv20_lsw_disable(struct regulator_dev *rdev)
  76. {
  77. struct rtmv20_priv *priv = rdev_get_drvdata(rdev);
  78. int ret;
  79. ret = regulator_disable_regmap(rdev);
  80. if (ret)
  81. return ret;
  82. /* Mark the regcache as dirty and cache only before HW disabled */
  83. regcache_cache_only(priv->regmap, true);
  84. regcache_mark_dirty(priv->regmap);
  85. gpiod_set_value(priv->enable_gpio, 0);
  86. return 0;
  87. }
  88. static int rtmv20_lsw_set_current_limit(struct regulator_dev *rdev, int min_uA,
  89. int max_uA)
  90. {
  91. int sel;
  92. if (min_uA > RTMV20_LSW_MAXUA || max_uA < RTMV20_LSW_MINUA)
  93. return -EINVAL;
  94. if (max_uA > RTMV20_LSW_MAXUA)
  95. max_uA = RTMV20_LSW_MAXUA;
  96. sel = (max_uA - RTMV20_LSW_MINUA) / RTMV20_LSW_STEPUA;
  97. /* Ensure the selected setting is still in range */
  98. if ((sel * RTMV20_LSW_STEPUA + RTMV20_LSW_MINUA) < min_uA)
  99. return -EINVAL;
  100. sel <<= ffs(rdev->desc->csel_mask) - 1;
  101. return regmap_update_bits(rdev->regmap, rdev->desc->csel_reg,
  102. rdev->desc->csel_mask, sel);
  103. }
  104. static int rtmv20_lsw_get_current_limit(struct regulator_dev *rdev)
  105. {
  106. unsigned int val;
  107. int ret;
  108. ret = regmap_read(rdev->regmap, rdev->desc->csel_reg, &val);
  109. if (ret)
  110. return ret;
  111. val &= rdev->desc->csel_mask;
  112. val >>= ffs(rdev->desc->csel_mask) - 1;
  113. return val * RTMV20_LSW_STEPUA + RTMV20_LSW_MINUA;
  114. }
  115. static const struct regulator_ops rtmv20_regulator_ops = {
  116. .set_current_limit = rtmv20_lsw_set_current_limit,
  117. .get_current_limit = rtmv20_lsw_get_current_limit,
  118. .enable = rtmv20_lsw_enable,
  119. .disable = rtmv20_lsw_disable,
  120. .is_enabled = regulator_is_enabled_regmap,
  121. };
  122. static const struct regulator_desc rtmv20_lsw_desc = {
  123. .name = "rtmv20,lsw",
  124. .of_match = of_match_ptr("lsw"),
  125. .type = REGULATOR_CURRENT,
  126. .owner = THIS_MODULE,
  127. .ops = &rtmv20_regulator_ops,
  128. .csel_reg = RTMV20_REG_LDCTRL1,
  129. .csel_mask = RTMV20_LDCURR_MASK,
  130. .enable_reg = RTMV20_REG_ENCTRL,
  131. .enable_mask = LDENABLE_MASK,
  132. .enable_time = RTMV20_CSRDY_TIMEUS,
  133. };
  134. static irqreturn_t rtmv20_irq_handler(int irq, void *data)
  135. {
  136. struct rtmv20_priv *priv = data;
  137. unsigned int val;
  138. int ret;
  139. ret = regmap_read(priv->regmap, RTMV20_REG_LDIRQ, &val);
  140. if (ret) {
  141. dev_err(priv->dev, "Failed to get irq flags\n");
  142. return IRQ_NONE;
  143. }
  144. if (val & OTPEVT_MASK)
  145. regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_OVER_TEMP, NULL);
  146. if (val & OCPEVT_MASK)
  147. regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_OVER_CURRENT, NULL);
  148. if (val & FAILEVT_MASK)
  149. regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_FAIL, NULL);
  150. return IRQ_HANDLED;
  151. }
  152. static u32 clamp_to_selector(u32 val, u32 min, u32 max, u32 step)
  153. {
  154. u32 retval = clamp_val(val, min, max);
  155. return (retval - min) / step;
  156. }
  157. static int rtmv20_properties_init(struct rtmv20_priv *priv)
  158. {
  159. const struct {
  160. const char *name;
  161. u32 def;
  162. u32 min;
  163. u32 max;
  164. u32 step;
  165. u32 addr;
  166. u32 mask;
  167. } props[] = {
  168. { "richtek,ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY,
  169. RTMV20_DELAY_MASK },
  170. { "richtek,ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH,
  171. RTMV20_WIDTH_MASK },
  172. { "richtek,fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1,
  173. RTMV20_DELAY_MASK },
  174. { "richtek,fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3,
  175. RTMV20_WIDTH2_MASK },
  176. { "richtek,fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1,
  177. RTMV20_DELAY_MASK },
  178. { "richtek,fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3,
  179. RTMV20_WIDTH2_MASK },
  180. { "richtek,es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH,
  181. RTMV20_WIDTH_MASK },
  182. { "richtek,es-ld-current-microamp", 3000000, 0, 6000000, 30000,
  183. RTMV20_REG_ESLDCTRL1, RTMV20_LDCURR_MASK },
  184. { "richtek,lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP,
  185. RTMV20_LBPLVL_MASK },
  186. { "richtek,lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK },
  187. { "richtek,strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2,
  188. RTMV20_STROBEPOL_MASK },
  189. { "richtek,vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2,
  190. RTMV20_VSYNPOL_MASK },
  191. { "richtek,fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK },
  192. { "richtek,fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK },
  193. { "richtek,es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK },
  194. };
  195. int i, ret;
  196. for (i = 0; i < ARRAY_SIZE(props); i++) {
  197. __be16 bval16;
  198. u16 val16;
  199. u32 temp;
  200. int significant_bit = fls(props[i].mask);
  201. int shift = ffs(props[i].mask) - 1;
  202. if (props[i].max > 1) {
  203. ret = device_property_read_u32(priv->dev, props[i].name, &temp);
  204. if (ret)
  205. temp = props[i].def;
  206. } else
  207. temp = device_property_read_bool(priv->dev, props[i].name);
  208. temp = clamp_to_selector(temp, props[i].min, props[i].max, props[i].step);
  209. /* If significant bit is over 8, two byte access, others one */
  210. if (significant_bit > 8) {
  211. ret = regmap_raw_read(priv->regmap, props[i].addr, &bval16, sizeof(bval16));
  212. if (ret)
  213. return ret;
  214. val16 = be16_to_cpu(bval16);
  215. val16 &= ~props[i].mask;
  216. val16 |= (temp << shift);
  217. bval16 = cpu_to_be16(val16);
  218. ret = regmap_raw_write(priv->regmap, props[i].addr, &bval16,
  219. sizeof(bval16));
  220. } else {
  221. ret = regmap_update_bits(priv->regmap, props[i].addr, props[i].mask,
  222. temp << shift);
  223. }
  224. if (ret)
  225. return ret;
  226. }
  227. return 0;
  228. }
  229. static int rtmv20_check_chip_exist(struct rtmv20_priv *priv)
  230. {
  231. unsigned int val;
  232. int ret;
  233. ret = regmap_read(priv->regmap, RTMV20_REG_DEVINFO, &val);
  234. if (ret)
  235. return ret;
  236. if ((val & RTMV20_VID_MASK) != RICHTEK_VID)
  237. return -ENODEV;
  238. return 0;
  239. }
  240. static bool rtmv20_is_accessible_reg(struct device *dev, unsigned int reg)
  241. {
  242. switch (reg) {
  243. case RTMV20_REG_DEVINFO ... RTMV20_REG_STRBVSYNDLYL:
  244. case RTMV20_REG_LDIRQ:
  245. case RTMV20_REG_LDSTAT:
  246. case RTMV20_REG_LDMASK:
  247. return true;
  248. }
  249. return false;
  250. }
  251. static bool rtmv20_is_volatile_reg(struct device *dev, unsigned int reg)
  252. {
  253. if (reg == RTMV20_REG_LDIRQ || reg == RTMV20_REG_LDSTAT)
  254. return true;
  255. return false;
  256. }
  257. static const struct regmap_config rtmv20_regmap_config = {
  258. .reg_bits = 8,
  259. .val_bits = 8,
  260. .cache_type = REGCACHE_RBTREE,
  261. .max_register = RTMV20_REG_LDMASK,
  262. .num_reg_defaults_raw = RTMV20_MAX_REGS,
  263. .writeable_reg = rtmv20_is_accessible_reg,
  264. .readable_reg = rtmv20_is_accessible_reg,
  265. .volatile_reg = rtmv20_is_volatile_reg,
  266. };
  267. static int rtmv20_probe(struct i2c_client *i2c)
  268. {
  269. struct rtmv20_priv *priv;
  270. struct regulator_config config = {};
  271. int ret;
  272. priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
  273. if (!priv)
  274. return -ENOMEM;
  275. priv->dev = &i2c->dev;
  276. /* Before regmap register, configure HW enable to make I2C accessible */
  277. priv->enable_gpio = devm_gpiod_get(&i2c->dev, "enable", GPIOD_OUT_HIGH);
  278. if (IS_ERR(priv->enable_gpio)) {
  279. dev_err(&i2c->dev, "Failed to get enable gpio\n");
  280. return PTR_ERR(priv->enable_gpio);
  281. }
  282. /* Wait for I2C can be accessed */
  283. usleep_range(RTMV20_I2CRDY_TIMEUS, RTMV20_I2CRDY_TIMEUS + 100);
  284. priv->regmap = devm_regmap_init_i2c(i2c, &rtmv20_regmap_config);
  285. if (IS_ERR(priv->regmap)) {
  286. dev_err(&i2c->dev, "Failed to allocate register map\n");
  287. return PTR_ERR(priv->regmap);
  288. }
  289. ret = rtmv20_check_chip_exist(priv);
  290. if (ret) {
  291. dev_err(&i2c->dev, "Chip vendor info is not matched\n");
  292. return ret;
  293. }
  294. ret = rtmv20_properties_init(priv);
  295. if (ret) {
  296. dev_err(&i2c->dev, "Failed to init properties\n");
  297. return ret;
  298. }
  299. /*
  300. * keep in shutdown mode to minimize the current consumption
  301. * and also mark regcache as dirty
  302. */
  303. regcache_cache_only(priv->regmap, true);
  304. regcache_mark_dirty(priv->regmap);
  305. gpiod_set_value(priv->enable_gpio, 0);
  306. config.dev = &i2c->dev;
  307. config.regmap = priv->regmap;
  308. config.driver_data = priv;
  309. priv->rdev = devm_regulator_register(&i2c->dev, &rtmv20_lsw_desc, &config);
  310. if (IS_ERR(priv->rdev)) {
  311. dev_err(&i2c->dev, "Failed to register regulator\n");
  312. return PTR_ERR(priv->rdev);
  313. }
  314. /* Unmask all events before IRQ registered */
  315. ret = regmap_write(priv->regmap, RTMV20_REG_LDMASK, 0);
  316. if (ret)
  317. return ret;
  318. return devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rtmv20_irq_handler,
  319. IRQF_ONESHOT, dev_name(&i2c->dev), priv);
  320. }
  321. static int __maybe_unused rtmv20_suspend(struct device *dev)
  322. {
  323. struct i2c_client *i2c = to_i2c_client(dev);
  324. /*
  325. * When system suspend, disable irq to prevent interrupt trigger
  326. * during I2C bus suspend
  327. */
  328. disable_irq(i2c->irq);
  329. if (device_may_wakeup(dev))
  330. enable_irq_wake(i2c->irq);
  331. return 0;
  332. }
  333. static int __maybe_unused rtmv20_resume(struct device *dev)
  334. {
  335. struct i2c_client *i2c = to_i2c_client(dev);
  336. /* Enable irq after I2C bus already resume */
  337. enable_irq(i2c->irq);
  338. if (device_may_wakeup(dev))
  339. disable_irq_wake(i2c->irq);
  340. return 0;
  341. }
  342. static SIMPLE_DEV_PM_OPS(rtmv20_pm, rtmv20_suspend, rtmv20_resume);
  343. static const struct of_device_id __maybe_unused rtmv20_of_id[] = {
  344. { .compatible = "richtek,rtmv20", },
  345. {}
  346. };
  347. MODULE_DEVICE_TABLE(of, rtmv20_of_id);
  348. static struct i2c_driver rtmv20_driver = {
  349. .driver = {
  350. .name = "rtmv20",
  351. .of_match_table = of_match_ptr(rtmv20_of_id),
  352. .pm = &rtmv20_pm,
  353. },
  354. .probe_new = rtmv20_probe,
  355. };
  356. module_i2c_driver(rtmv20_driver);
  357. MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
  358. MODULE_DESCRIPTION("Richtek RTMV20 Regulator Driver");
  359. MODULE_LICENSE("GPL v2");