qcom_rpm-regulator.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014, Sony Mobile Communications AB.
  4. * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/of.h>
  9. #include <linux/of_device.h>
  10. #include <linux/regulator/driver.h>
  11. #include <linux/regulator/machine.h>
  12. #include <linux/regulator/of_regulator.h>
  13. #include <linux/mfd/qcom_rpm.h>
  14. #include <dt-bindings/mfd/qcom-rpm.h>
  15. #define MAX_REQUEST_LEN 2
  16. struct request_member {
  17. int word;
  18. unsigned int mask;
  19. int shift;
  20. };
  21. struct rpm_reg_parts {
  22. struct request_member mV; /* used if voltage is in mV */
  23. struct request_member uV; /* used if voltage is in uV */
  24. struct request_member ip; /* peak current in mA */
  25. struct request_member pd; /* pull down enable */
  26. struct request_member ia; /* average current in mA */
  27. struct request_member fm; /* force mode */
  28. struct request_member pm; /* power mode */
  29. struct request_member pc; /* pin control */
  30. struct request_member pf; /* pin function */
  31. struct request_member enable_state; /* NCP and switch */
  32. struct request_member comp_mode; /* NCP */
  33. struct request_member freq; /* frequency: NCP and SMPS */
  34. struct request_member freq_clk_src; /* clock source: SMPS */
  35. struct request_member hpm; /* switch: control OCP and SS */
  36. int request_len;
  37. };
  38. #define FORCE_MODE_IS_2_BITS(reg) \
  39. (((reg)->parts->fm.mask >> (reg)->parts->fm.shift) == 3)
  40. struct qcom_rpm_reg {
  41. struct qcom_rpm *rpm;
  42. struct mutex lock;
  43. struct device *dev;
  44. struct regulator_desc desc;
  45. const struct rpm_reg_parts *parts;
  46. int resource;
  47. u32 val[MAX_REQUEST_LEN];
  48. int uV;
  49. int is_enabled;
  50. bool supports_force_mode_auto;
  51. bool supports_force_mode_bypass;
  52. };
  53. static const struct rpm_reg_parts rpm8660_ldo_parts = {
  54. .request_len = 2,
  55. .mV = { 0, 0x00000FFF, 0 },
  56. .ip = { 0, 0x00FFF000, 12 },
  57. .fm = { 0, 0x03000000, 24 },
  58. .pc = { 0, 0x3C000000, 26 },
  59. .pf = { 0, 0xC0000000, 30 },
  60. .pd = { 1, 0x00000001, 0 },
  61. .ia = { 1, 0x00001FFE, 1 },
  62. };
  63. static const struct rpm_reg_parts rpm8660_smps_parts = {
  64. .request_len = 2,
  65. .mV = { 0, 0x00000FFF, 0 },
  66. .ip = { 0, 0x00FFF000, 12 },
  67. .fm = { 0, 0x03000000, 24 },
  68. .pc = { 0, 0x3C000000, 26 },
  69. .pf = { 0, 0xC0000000, 30 },
  70. .pd = { 1, 0x00000001, 0 },
  71. .ia = { 1, 0x00001FFE, 1 },
  72. .freq = { 1, 0x001FE000, 13 },
  73. .freq_clk_src = { 1, 0x00600000, 21 },
  74. };
  75. static const struct rpm_reg_parts rpm8660_switch_parts = {
  76. .request_len = 1,
  77. .enable_state = { 0, 0x00000001, 0 },
  78. .pd = { 0, 0x00000002, 1 },
  79. .pc = { 0, 0x0000003C, 2 },
  80. .pf = { 0, 0x000000C0, 6 },
  81. .hpm = { 0, 0x00000300, 8 },
  82. };
  83. static const struct rpm_reg_parts rpm8660_ncp_parts = {
  84. .request_len = 1,
  85. .mV = { 0, 0x00000FFF, 0 },
  86. .enable_state = { 0, 0x00001000, 12 },
  87. .comp_mode = { 0, 0x00002000, 13 },
  88. .freq = { 0, 0x003FC000, 14 },
  89. };
  90. static const struct rpm_reg_parts rpm8960_ldo_parts = {
  91. .request_len = 2,
  92. .uV = { 0, 0x007FFFFF, 0 },
  93. .pd = { 0, 0x00800000, 23 },
  94. .pc = { 0, 0x0F000000, 24 },
  95. .pf = { 0, 0xF0000000, 28 },
  96. .ip = { 1, 0x000003FF, 0 },
  97. .ia = { 1, 0x000FFC00, 10 },
  98. .fm = { 1, 0x00700000, 20 },
  99. };
  100. static const struct rpm_reg_parts rpm8960_smps_parts = {
  101. .request_len = 2,
  102. .uV = { 0, 0x007FFFFF, 0 },
  103. .pd = { 0, 0x00800000, 23 },
  104. .pc = { 0, 0x0F000000, 24 },
  105. .pf = { 0, 0xF0000000, 28 },
  106. .ip = { 1, 0x000003FF, 0 },
  107. .ia = { 1, 0x000FFC00, 10 },
  108. .fm = { 1, 0x00700000, 20 },
  109. .pm = { 1, 0x00800000, 23 },
  110. .freq = { 1, 0x1F000000, 24 },
  111. .freq_clk_src = { 1, 0x60000000, 29 },
  112. };
  113. static const struct rpm_reg_parts rpm8960_switch_parts = {
  114. .request_len = 1,
  115. .enable_state = { 0, 0x00000001, 0 },
  116. .pd = { 0, 0x00000002, 1 },
  117. .pc = { 0, 0x0000003C, 2 },
  118. .pf = { 0, 0x000003C0, 6 },
  119. .hpm = { 0, 0x00000C00, 10 },
  120. };
  121. static const struct rpm_reg_parts rpm8960_ncp_parts = {
  122. .request_len = 1,
  123. .uV = { 0, 0x007FFFFF, 0 },
  124. .enable_state = { 0, 0x00800000, 23 },
  125. .comp_mode = { 0, 0x01000000, 24 },
  126. .freq = { 0, 0x3E000000, 25 },
  127. };
  128. /*
  129. * Physically available PMIC regulator voltage ranges
  130. */
  131. static const struct linear_range pldo_ranges[] = {
  132. REGULATOR_LINEAR_RANGE( 750000, 0, 59, 12500),
  133. REGULATOR_LINEAR_RANGE(1500000, 60, 123, 25000),
  134. REGULATOR_LINEAR_RANGE(3100000, 124, 160, 50000),
  135. };
  136. static const struct linear_range nldo_ranges[] = {
  137. REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
  138. };
  139. static const struct linear_range nldo1200_ranges[] = {
  140. REGULATOR_LINEAR_RANGE( 375000, 0, 59, 6250),
  141. REGULATOR_LINEAR_RANGE( 750000, 60, 123, 12500),
  142. };
  143. static const struct linear_range smps_ranges[] = {
  144. REGULATOR_LINEAR_RANGE( 375000, 0, 29, 12500),
  145. REGULATOR_LINEAR_RANGE( 750000, 30, 89, 12500),
  146. REGULATOR_LINEAR_RANGE(1500000, 90, 153, 25000),
  147. };
  148. static const struct linear_range ftsmps_ranges[] = {
  149. REGULATOR_LINEAR_RANGE( 350000, 0, 6, 50000),
  150. REGULATOR_LINEAR_RANGE( 700000, 7, 63, 12500),
  151. REGULATOR_LINEAR_RANGE(1500000, 64, 100, 50000),
  152. };
  153. static const struct linear_range smb208_ranges[] = {
  154. REGULATOR_LINEAR_RANGE( 375000, 0, 29, 12500),
  155. REGULATOR_LINEAR_RANGE( 750000, 30, 89, 12500),
  156. REGULATOR_LINEAR_RANGE(1500000, 90, 153, 25000),
  157. REGULATOR_LINEAR_RANGE(3100000, 154, 234, 25000),
  158. };
  159. static const struct linear_range ncp_ranges[] = {
  160. REGULATOR_LINEAR_RANGE(1500000, 0, 31, 50000),
  161. };
  162. static int rpm_reg_write(struct qcom_rpm_reg *vreg,
  163. const struct request_member *req,
  164. const int value)
  165. {
  166. if (WARN_ON((value << req->shift) & ~req->mask))
  167. return -EINVAL;
  168. vreg->val[req->word] &= ~req->mask;
  169. vreg->val[req->word] |= value << req->shift;
  170. return qcom_rpm_write(vreg->rpm,
  171. QCOM_RPM_ACTIVE_STATE,
  172. vreg->resource,
  173. vreg->val,
  174. vreg->parts->request_len);
  175. }
  176. static int rpm_reg_set_mV_sel(struct regulator_dev *rdev,
  177. unsigned selector)
  178. {
  179. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  180. const struct rpm_reg_parts *parts = vreg->parts;
  181. const struct request_member *req = &parts->mV;
  182. int ret = 0;
  183. int uV;
  184. if (req->mask == 0)
  185. return -EINVAL;
  186. uV = regulator_list_voltage_linear_range(rdev, selector);
  187. if (uV < 0)
  188. return uV;
  189. mutex_lock(&vreg->lock);
  190. if (vreg->is_enabled)
  191. ret = rpm_reg_write(vreg, req, uV / 1000);
  192. if (!ret)
  193. vreg->uV = uV;
  194. mutex_unlock(&vreg->lock);
  195. return ret;
  196. }
  197. static int rpm_reg_set_uV_sel(struct regulator_dev *rdev,
  198. unsigned selector)
  199. {
  200. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  201. const struct rpm_reg_parts *parts = vreg->parts;
  202. const struct request_member *req = &parts->uV;
  203. int ret = 0;
  204. int uV;
  205. if (req->mask == 0)
  206. return -EINVAL;
  207. uV = regulator_list_voltage_linear_range(rdev, selector);
  208. if (uV < 0)
  209. return uV;
  210. mutex_lock(&vreg->lock);
  211. if (vreg->is_enabled)
  212. ret = rpm_reg_write(vreg, req, uV);
  213. if (!ret)
  214. vreg->uV = uV;
  215. mutex_unlock(&vreg->lock);
  216. return ret;
  217. }
  218. static int rpm_reg_get_voltage(struct regulator_dev *rdev)
  219. {
  220. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  221. return vreg->uV;
  222. }
  223. static int rpm_reg_mV_enable(struct regulator_dev *rdev)
  224. {
  225. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  226. const struct rpm_reg_parts *parts = vreg->parts;
  227. const struct request_member *req = &parts->mV;
  228. int ret;
  229. if (req->mask == 0)
  230. return -EINVAL;
  231. mutex_lock(&vreg->lock);
  232. ret = rpm_reg_write(vreg, req, vreg->uV / 1000);
  233. if (!ret)
  234. vreg->is_enabled = 1;
  235. mutex_unlock(&vreg->lock);
  236. return ret;
  237. }
  238. static int rpm_reg_uV_enable(struct regulator_dev *rdev)
  239. {
  240. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  241. const struct rpm_reg_parts *parts = vreg->parts;
  242. const struct request_member *req = &parts->uV;
  243. int ret;
  244. if (req->mask == 0)
  245. return -EINVAL;
  246. mutex_lock(&vreg->lock);
  247. ret = rpm_reg_write(vreg, req, vreg->uV);
  248. if (!ret)
  249. vreg->is_enabled = 1;
  250. mutex_unlock(&vreg->lock);
  251. return ret;
  252. }
  253. static int rpm_reg_switch_enable(struct regulator_dev *rdev)
  254. {
  255. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  256. const struct rpm_reg_parts *parts = vreg->parts;
  257. const struct request_member *req = &parts->enable_state;
  258. int ret;
  259. if (req->mask == 0)
  260. return -EINVAL;
  261. mutex_lock(&vreg->lock);
  262. ret = rpm_reg_write(vreg, req, 1);
  263. if (!ret)
  264. vreg->is_enabled = 1;
  265. mutex_unlock(&vreg->lock);
  266. return ret;
  267. }
  268. static int rpm_reg_mV_disable(struct regulator_dev *rdev)
  269. {
  270. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  271. const struct rpm_reg_parts *parts = vreg->parts;
  272. const struct request_member *req = &parts->mV;
  273. int ret;
  274. if (req->mask == 0)
  275. return -EINVAL;
  276. mutex_lock(&vreg->lock);
  277. ret = rpm_reg_write(vreg, req, 0);
  278. if (!ret)
  279. vreg->is_enabled = 0;
  280. mutex_unlock(&vreg->lock);
  281. return ret;
  282. }
  283. static int rpm_reg_uV_disable(struct regulator_dev *rdev)
  284. {
  285. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  286. const struct rpm_reg_parts *parts = vreg->parts;
  287. const struct request_member *req = &parts->uV;
  288. int ret;
  289. if (req->mask == 0)
  290. return -EINVAL;
  291. mutex_lock(&vreg->lock);
  292. ret = rpm_reg_write(vreg, req, 0);
  293. if (!ret)
  294. vreg->is_enabled = 0;
  295. mutex_unlock(&vreg->lock);
  296. return ret;
  297. }
  298. static int rpm_reg_switch_disable(struct regulator_dev *rdev)
  299. {
  300. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  301. const struct rpm_reg_parts *parts = vreg->parts;
  302. const struct request_member *req = &parts->enable_state;
  303. int ret;
  304. if (req->mask == 0)
  305. return -EINVAL;
  306. mutex_lock(&vreg->lock);
  307. ret = rpm_reg_write(vreg, req, 0);
  308. if (!ret)
  309. vreg->is_enabled = 0;
  310. mutex_unlock(&vreg->lock);
  311. return ret;
  312. }
  313. static int rpm_reg_is_enabled(struct regulator_dev *rdev)
  314. {
  315. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  316. return vreg->is_enabled;
  317. }
  318. static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
  319. {
  320. struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
  321. const struct rpm_reg_parts *parts = vreg->parts;
  322. const struct request_member *req = &parts->ia;
  323. int load_mA = load_uA / 1000;
  324. int max_mA = req->mask >> req->shift;
  325. int ret;
  326. if (req->mask == 0)
  327. return -EINVAL;
  328. if (load_mA > max_mA)
  329. load_mA = max_mA;
  330. mutex_lock(&vreg->lock);
  331. ret = rpm_reg_write(vreg, req, load_mA);
  332. mutex_unlock(&vreg->lock);
  333. return ret;
  334. }
  335. static const struct regulator_ops uV_ops = {
  336. .list_voltage = regulator_list_voltage_linear_range,
  337. .set_voltage_sel = rpm_reg_set_uV_sel,
  338. .get_voltage = rpm_reg_get_voltage,
  339. .enable = rpm_reg_uV_enable,
  340. .disable = rpm_reg_uV_disable,
  341. .is_enabled = rpm_reg_is_enabled,
  342. .set_load = rpm_reg_set_load,
  343. };
  344. static const struct regulator_ops mV_ops = {
  345. .list_voltage = regulator_list_voltage_linear_range,
  346. .set_voltage_sel = rpm_reg_set_mV_sel,
  347. .get_voltage = rpm_reg_get_voltage,
  348. .enable = rpm_reg_mV_enable,
  349. .disable = rpm_reg_mV_disable,
  350. .is_enabled = rpm_reg_is_enabled,
  351. .set_load = rpm_reg_set_load,
  352. };
  353. static const struct regulator_ops switch_ops = {
  354. .enable = rpm_reg_switch_enable,
  355. .disable = rpm_reg_switch_disable,
  356. .is_enabled = rpm_reg_is_enabled,
  357. };
  358. /*
  359. * PM8018 regulators
  360. */
  361. static const struct qcom_rpm_reg pm8018_pldo = {
  362. .desc.linear_ranges = pldo_ranges,
  363. .desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
  364. .desc.n_voltages = 161,
  365. .desc.ops = &uV_ops,
  366. .parts = &rpm8960_ldo_parts,
  367. .supports_force_mode_auto = false,
  368. .supports_force_mode_bypass = false,
  369. };
  370. static const struct qcom_rpm_reg pm8018_nldo = {
  371. .desc.linear_ranges = nldo_ranges,
  372. .desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
  373. .desc.n_voltages = 64,
  374. .desc.ops = &uV_ops,
  375. .parts = &rpm8960_ldo_parts,
  376. .supports_force_mode_auto = false,
  377. .supports_force_mode_bypass = false,
  378. };
  379. static const struct qcom_rpm_reg pm8018_smps = {
  380. .desc.linear_ranges = smps_ranges,
  381. .desc.n_linear_ranges = ARRAY_SIZE(smps_ranges),
  382. .desc.n_voltages = 154,
  383. .desc.ops = &uV_ops,
  384. .parts = &rpm8960_smps_parts,
  385. .supports_force_mode_auto = false,
  386. .supports_force_mode_bypass = false,
  387. };
  388. static const struct qcom_rpm_reg pm8018_switch = {
  389. .desc.ops = &switch_ops,
  390. .parts = &rpm8960_switch_parts,
  391. };
  392. /*
  393. * PM8058 regulators
  394. */
  395. static const struct qcom_rpm_reg pm8058_pldo = {
  396. .desc.linear_ranges = pldo_ranges,
  397. .desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
  398. .desc.n_voltages = 161,
  399. .desc.ops = &mV_ops,
  400. .parts = &rpm8660_ldo_parts,
  401. .supports_force_mode_auto = false,
  402. .supports_force_mode_bypass = false,
  403. };
  404. static const struct qcom_rpm_reg pm8058_nldo = {
  405. .desc.linear_ranges = nldo_ranges,
  406. .desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
  407. .desc.n_voltages = 64,
  408. .desc.ops = &mV_ops,
  409. .parts = &rpm8660_ldo_parts,
  410. .supports_force_mode_auto = false,
  411. .supports_force_mode_bypass = false,
  412. };
  413. static const struct qcom_rpm_reg pm8058_smps = {
  414. .desc.linear_ranges = smps_ranges,
  415. .desc.n_linear_ranges = ARRAY_SIZE(smps_ranges),
  416. .desc.n_voltages = 154,
  417. .desc.ops = &mV_ops,
  418. .parts = &rpm8660_smps_parts,
  419. .supports_force_mode_auto = false,
  420. .supports_force_mode_bypass = false,
  421. };
  422. static const struct qcom_rpm_reg pm8058_ncp = {
  423. .desc.linear_ranges = ncp_ranges,
  424. .desc.n_linear_ranges = ARRAY_SIZE(ncp_ranges),
  425. .desc.n_voltages = 32,
  426. .desc.ops = &mV_ops,
  427. .parts = &rpm8660_ncp_parts,
  428. };
  429. static const struct qcom_rpm_reg pm8058_switch = {
  430. .desc.ops = &switch_ops,
  431. .parts = &rpm8660_switch_parts,
  432. };
  433. /*
  434. * PM8901 regulators
  435. */
  436. static const struct qcom_rpm_reg pm8901_pldo = {
  437. .desc.linear_ranges = pldo_ranges,
  438. .desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
  439. .desc.n_voltages = 161,
  440. .desc.ops = &mV_ops,
  441. .parts = &rpm8660_ldo_parts,
  442. .supports_force_mode_auto = false,
  443. .supports_force_mode_bypass = true,
  444. };
  445. static const struct qcom_rpm_reg pm8901_nldo = {
  446. .desc.linear_ranges = nldo_ranges,
  447. .desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
  448. .desc.n_voltages = 64,
  449. .desc.ops = &mV_ops,
  450. .parts = &rpm8660_ldo_parts,
  451. .supports_force_mode_auto = false,
  452. .supports_force_mode_bypass = true,
  453. };
  454. static const struct qcom_rpm_reg pm8901_ftsmps = {
  455. .desc.linear_ranges = ftsmps_ranges,
  456. .desc.n_linear_ranges = ARRAY_SIZE(ftsmps_ranges),
  457. .desc.n_voltages = 101,
  458. .desc.ops = &mV_ops,
  459. .parts = &rpm8660_smps_parts,
  460. .supports_force_mode_auto = true,
  461. .supports_force_mode_bypass = false,
  462. };
  463. static const struct qcom_rpm_reg pm8901_switch = {
  464. .desc.ops = &switch_ops,
  465. .parts = &rpm8660_switch_parts,
  466. };
  467. /*
  468. * PM8921 regulators
  469. */
  470. static const struct qcom_rpm_reg pm8921_pldo = {
  471. .desc.linear_ranges = pldo_ranges,
  472. .desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
  473. .desc.n_voltages = 161,
  474. .desc.ops = &uV_ops,
  475. .parts = &rpm8960_ldo_parts,
  476. .supports_force_mode_auto = false,
  477. .supports_force_mode_bypass = true,
  478. };
  479. static const struct qcom_rpm_reg pm8921_nldo = {
  480. .desc.linear_ranges = nldo_ranges,
  481. .desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
  482. .desc.n_voltages = 64,
  483. .desc.ops = &uV_ops,
  484. .parts = &rpm8960_ldo_parts,
  485. .supports_force_mode_auto = false,
  486. .supports_force_mode_bypass = true,
  487. };
  488. static const struct qcom_rpm_reg pm8921_nldo1200 = {
  489. .desc.linear_ranges = nldo1200_ranges,
  490. .desc.n_linear_ranges = ARRAY_SIZE(nldo1200_ranges),
  491. .desc.n_voltages = 124,
  492. .desc.ops = &uV_ops,
  493. .parts = &rpm8960_ldo_parts,
  494. .supports_force_mode_auto = false,
  495. .supports_force_mode_bypass = true,
  496. };
  497. static const struct qcom_rpm_reg pm8921_smps = {
  498. .desc.linear_ranges = smps_ranges,
  499. .desc.n_linear_ranges = ARRAY_SIZE(smps_ranges),
  500. .desc.n_voltages = 154,
  501. .desc.ops = &uV_ops,
  502. .parts = &rpm8960_smps_parts,
  503. .supports_force_mode_auto = true,
  504. .supports_force_mode_bypass = false,
  505. };
  506. static const struct qcom_rpm_reg pm8921_ncp = {
  507. .desc.linear_ranges = ncp_ranges,
  508. .desc.n_linear_ranges = ARRAY_SIZE(ncp_ranges),
  509. .desc.n_voltages = 32,
  510. .desc.ops = &uV_ops,
  511. .parts = &rpm8960_ncp_parts,
  512. };
  513. static const struct qcom_rpm_reg pm8921_switch = {
  514. .desc.ops = &switch_ops,
  515. .parts = &rpm8960_switch_parts,
  516. };
  517. static const struct qcom_rpm_reg smb208_smps = {
  518. .desc.linear_ranges = smb208_ranges,
  519. .desc.n_linear_ranges = ARRAY_SIZE(smb208_ranges),
  520. .desc.n_voltages = 235,
  521. .desc.ops = &uV_ops,
  522. .parts = &rpm8960_smps_parts,
  523. .supports_force_mode_auto = false,
  524. .supports_force_mode_bypass = false,
  525. };
  526. static int rpm_reg_set(struct qcom_rpm_reg *vreg,
  527. const struct request_member *req,
  528. const int value)
  529. {
  530. if (req->mask == 0 || (value << req->shift) & ~req->mask)
  531. return -EINVAL;
  532. vreg->val[req->word] &= ~req->mask;
  533. vreg->val[req->word] |= value << req->shift;
  534. return 0;
  535. }
  536. static int rpm_reg_of_parse_freq(struct device *dev,
  537. struct device_node *node,
  538. struct qcom_rpm_reg *vreg)
  539. {
  540. static const int freq_table[] = {
  541. 19200000, 9600000, 6400000, 4800000, 3840000, 3200000, 2740000,
  542. 2400000, 2130000, 1920000, 1750000, 1600000, 1480000, 1370000,
  543. 1280000, 1200000,
  544. };
  545. const char *key;
  546. u32 freq;
  547. int ret;
  548. int i;
  549. key = "qcom,switch-mode-frequency";
  550. ret = of_property_read_u32(node, key, &freq);
  551. if (ret) {
  552. dev_err(dev, "regulator requires %s property\n", key);
  553. return -EINVAL;
  554. }
  555. for (i = 0; i < ARRAY_SIZE(freq_table); i++) {
  556. if (freq == freq_table[i]) {
  557. rpm_reg_set(vreg, &vreg->parts->freq, i + 1);
  558. return 0;
  559. }
  560. }
  561. dev_err(dev, "invalid frequency %d\n", freq);
  562. return -EINVAL;
  563. }
  564. static int rpm_reg_of_parse(struct device_node *node,
  565. const struct regulator_desc *desc,
  566. struct regulator_config *config)
  567. {
  568. struct qcom_rpm_reg *vreg = config->driver_data;
  569. struct device *dev = config->dev;
  570. const char *key;
  571. u32 force_mode;
  572. bool pwm;
  573. u32 val;
  574. int ret;
  575. key = "bias-pull-down";
  576. if (of_property_read_bool(node, key)) {
  577. ret = rpm_reg_set(vreg, &vreg->parts->pd, 1);
  578. if (ret) {
  579. dev_err(dev, "%s is invalid", key);
  580. return ret;
  581. }
  582. }
  583. if (vreg->parts->freq.mask) {
  584. ret = rpm_reg_of_parse_freq(dev, node, vreg);
  585. if (ret < 0)
  586. return ret;
  587. }
  588. if (vreg->parts->pm.mask) {
  589. key = "qcom,power-mode-hysteretic";
  590. pwm = !of_property_read_bool(node, key);
  591. ret = rpm_reg_set(vreg, &vreg->parts->pm, pwm);
  592. if (ret) {
  593. dev_err(dev, "failed to set power mode\n");
  594. return ret;
  595. }
  596. }
  597. if (vreg->parts->fm.mask) {
  598. force_mode = -1;
  599. key = "qcom,force-mode";
  600. ret = of_property_read_u32(node, key, &val);
  601. if (ret == -EINVAL) {
  602. val = QCOM_RPM_FORCE_MODE_NONE;
  603. } else if (ret < 0) {
  604. dev_err(dev, "failed to read %s\n", key);
  605. return ret;
  606. }
  607. /*
  608. * If force-mode is encoded as 2 bits then the
  609. * possible register values are:
  610. * NONE, LPM, HPM
  611. * otherwise:
  612. * NONE, LPM, AUTO, HPM, BYPASS
  613. */
  614. switch (val) {
  615. case QCOM_RPM_FORCE_MODE_NONE:
  616. force_mode = 0;
  617. break;
  618. case QCOM_RPM_FORCE_MODE_LPM:
  619. force_mode = 1;
  620. break;
  621. case QCOM_RPM_FORCE_MODE_HPM:
  622. if (FORCE_MODE_IS_2_BITS(vreg))
  623. force_mode = 2;
  624. else
  625. force_mode = 3;
  626. break;
  627. case QCOM_RPM_FORCE_MODE_AUTO:
  628. if (vreg->supports_force_mode_auto)
  629. force_mode = 2;
  630. break;
  631. case QCOM_RPM_FORCE_MODE_BYPASS:
  632. if (vreg->supports_force_mode_bypass)
  633. force_mode = 4;
  634. break;
  635. }
  636. if (force_mode == -1) {
  637. dev_err(dev, "invalid force mode\n");
  638. return -EINVAL;
  639. }
  640. ret = rpm_reg_set(vreg, &vreg->parts->fm, force_mode);
  641. if (ret) {
  642. dev_err(dev, "failed to set force mode\n");
  643. return ret;
  644. }
  645. }
  646. return 0;
  647. }
  648. struct rpm_regulator_data {
  649. const char *name;
  650. int resource;
  651. const struct qcom_rpm_reg *template;
  652. const char *supply;
  653. };
  654. static const struct rpm_regulator_data rpm_pm8018_regulators[] = {
  655. { "s1", QCOM_RPM_PM8018_SMPS1, &pm8018_smps, "vdd_s1" },
  656. { "s2", QCOM_RPM_PM8018_SMPS2, &pm8018_smps, "vdd_s2" },
  657. { "s3", QCOM_RPM_PM8018_SMPS3, &pm8018_smps, "vdd_s3" },
  658. { "s4", QCOM_RPM_PM8018_SMPS4, &pm8018_smps, "vdd_s4" },
  659. { "s5", QCOM_RPM_PM8018_SMPS5, &pm8018_smps, "vdd_s5" },
  660. { "l2", QCOM_RPM_PM8018_LDO2, &pm8018_pldo, "vdd_l2" },
  661. { "l3", QCOM_RPM_PM8018_LDO3, &pm8018_pldo, "vdd_l3" },
  662. { "l4", QCOM_RPM_PM8018_LDO4, &pm8018_pldo, "vdd_l4" },
  663. { "l5", QCOM_RPM_PM8018_LDO5, &pm8018_pldo, "vdd_l5" },
  664. { "l6", QCOM_RPM_PM8018_LDO6, &pm8018_pldo, "vdd_l7" },
  665. { "l7", QCOM_RPM_PM8018_LDO7, &pm8018_pldo, "vdd_l7" },
  666. { "l8", QCOM_RPM_PM8018_LDO8, &pm8018_nldo, "vdd_l8" },
  667. { "l9", QCOM_RPM_PM8018_LDO9, &pm8921_nldo1200,
  668. "vdd_l9_l10_l11_l12" },
  669. { "l10", QCOM_RPM_PM8018_LDO10, &pm8018_nldo, "vdd_l9_l10_l11_l12" },
  670. { "l11", QCOM_RPM_PM8018_LDO11, &pm8018_nldo, "vdd_l9_l10_l11_l12" },
  671. { "l12", QCOM_RPM_PM8018_LDO12, &pm8018_nldo, "vdd_l9_l10_l11_l12" },
  672. { "l14", QCOM_RPM_PM8018_LDO14, &pm8018_pldo, "vdd_l14" },
  673. { "lvs1", QCOM_RPM_PM8018_LVS1, &pm8018_switch, "lvs1_in" },
  674. { }
  675. };
  676. static const struct rpm_regulator_data rpm_pm8058_regulators[] = {
  677. { "l0", QCOM_RPM_PM8058_LDO0, &pm8058_nldo, "vdd_l0_l1_lvs" },
  678. { "l1", QCOM_RPM_PM8058_LDO1, &pm8058_nldo, "vdd_l0_l1_lvs" },
  679. { "l2", QCOM_RPM_PM8058_LDO2, &pm8058_pldo, "vdd_l2_l11_l12" },
  680. { "l3", QCOM_RPM_PM8058_LDO3, &pm8058_pldo, "vdd_l3_l4_l5" },
  681. { "l4", QCOM_RPM_PM8058_LDO4, &pm8058_pldo, "vdd_l3_l4_l5" },
  682. { "l5", QCOM_RPM_PM8058_LDO5, &pm8058_pldo, "vdd_l3_l4_l5" },
  683. { "l6", QCOM_RPM_PM8058_LDO6, &pm8058_pldo, "vdd_l6_l7" },
  684. { "l7", QCOM_RPM_PM8058_LDO7, &pm8058_pldo, "vdd_l6_l7" },
  685. { "l8", QCOM_RPM_PM8058_LDO8, &pm8058_pldo, "vdd_l8" },
  686. { "l9", QCOM_RPM_PM8058_LDO9, &pm8058_pldo, "vdd_l9" },
  687. { "l10", QCOM_RPM_PM8058_LDO10, &pm8058_pldo, "vdd_l10" },
  688. { "l11", QCOM_RPM_PM8058_LDO11, &pm8058_pldo, "vdd_l2_l11_l12" },
  689. { "l12", QCOM_RPM_PM8058_LDO12, &pm8058_pldo, "vdd_l2_l11_l12" },
  690. { "l13", QCOM_RPM_PM8058_LDO13, &pm8058_pldo, "vdd_l13_l16" },
  691. { "l14", QCOM_RPM_PM8058_LDO14, &pm8058_pldo, "vdd_l14_l15" },
  692. { "l15", QCOM_RPM_PM8058_LDO15, &pm8058_pldo, "vdd_l14_l15" },
  693. { "l16", QCOM_RPM_PM8058_LDO16, &pm8058_pldo, "vdd_l13_l16" },
  694. { "l17", QCOM_RPM_PM8058_LDO17, &pm8058_pldo, "vdd_l17_l18" },
  695. { "l18", QCOM_RPM_PM8058_LDO18, &pm8058_pldo, "vdd_l17_l18" },
  696. { "l19", QCOM_RPM_PM8058_LDO19, &pm8058_pldo, "vdd_l19_l20" },
  697. { "l20", QCOM_RPM_PM8058_LDO20, &pm8058_pldo, "vdd_l19_l20" },
  698. { "l21", QCOM_RPM_PM8058_LDO21, &pm8058_nldo, "vdd_l21" },
  699. { "l22", QCOM_RPM_PM8058_LDO22, &pm8058_nldo, "vdd_l22" },
  700. { "l23", QCOM_RPM_PM8058_LDO23, &pm8058_nldo, "vdd_l23_l24_l25" },
  701. { "l24", QCOM_RPM_PM8058_LDO24, &pm8058_nldo, "vdd_l23_l24_l25" },
  702. { "l25", QCOM_RPM_PM8058_LDO25, &pm8058_nldo, "vdd_l23_l24_l25" },
  703. { "s0", QCOM_RPM_PM8058_SMPS0, &pm8058_smps, "vdd_s0" },
  704. { "s1", QCOM_RPM_PM8058_SMPS1, &pm8058_smps, "vdd_s1" },
  705. { "s2", QCOM_RPM_PM8058_SMPS2, &pm8058_smps, "vdd_s2" },
  706. { "s3", QCOM_RPM_PM8058_SMPS3, &pm8058_smps, "vdd_s3" },
  707. { "s4", QCOM_RPM_PM8058_SMPS4, &pm8058_smps, "vdd_s4" },
  708. { "lvs0", QCOM_RPM_PM8058_LVS0, &pm8058_switch, "vdd_l0_l1_lvs" },
  709. { "lvs1", QCOM_RPM_PM8058_LVS1, &pm8058_switch, "vdd_l0_l1_lvs" },
  710. { "ncp", QCOM_RPM_PM8058_NCP, &pm8058_ncp, "vdd_ncp" },
  711. { }
  712. };
  713. static const struct rpm_regulator_data rpm_pm8901_regulators[] = {
  714. { "l0", QCOM_RPM_PM8901_LDO0, &pm8901_nldo, "vdd_l0" },
  715. { "l1", QCOM_RPM_PM8901_LDO1, &pm8901_pldo, "vdd_l1" },
  716. { "l2", QCOM_RPM_PM8901_LDO2, &pm8901_pldo, "vdd_l2" },
  717. { "l3", QCOM_RPM_PM8901_LDO3, &pm8901_pldo, "vdd_l3" },
  718. { "l4", QCOM_RPM_PM8901_LDO4, &pm8901_pldo, "vdd_l4" },
  719. { "l5", QCOM_RPM_PM8901_LDO5, &pm8901_pldo, "vdd_l5" },
  720. { "l6", QCOM_RPM_PM8901_LDO6, &pm8901_pldo, "vdd_l6" },
  721. { "s0", QCOM_RPM_PM8901_SMPS0, &pm8901_ftsmps, "vdd_s0" },
  722. { "s1", QCOM_RPM_PM8901_SMPS1, &pm8901_ftsmps, "vdd_s1" },
  723. { "s2", QCOM_RPM_PM8901_SMPS2, &pm8901_ftsmps, "vdd_s2" },
  724. { "s3", QCOM_RPM_PM8901_SMPS3, &pm8901_ftsmps, "vdd_s3" },
  725. { "s4", QCOM_RPM_PM8901_SMPS4, &pm8901_ftsmps, "vdd_s4" },
  726. { "lvs0", QCOM_RPM_PM8901_LVS0, &pm8901_switch, "lvs0_in" },
  727. { "lvs1", QCOM_RPM_PM8901_LVS1, &pm8901_switch, "lvs1_in" },
  728. { "lvs2", QCOM_RPM_PM8901_LVS2, &pm8901_switch, "lvs2_in" },
  729. { "lvs3", QCOM_RPM_PM8901_LVS3, &pm8901_switch, "lvs3_in" },
  730. { "mvs", QCOM_RPM_PM8901_MVS, &pm8901_switch, "mvs_in" },
  731. { }
  732. };
  733. static const struct rpm_regulator_data rpm_pm8921_regulators[] = {
  734. { "s1", QCOM_RPM_PM8921_SMPS1, &pm8921_smps, "vdd_s1" },
  735. { "s2", QCOM_RPM_PM8921_SMPS2, &pm8921_smps, "vdd_s2" },
  736. { "s3", QCOM_RPM_PM8921_SMPS3, &pm8921_smps },
  737. { "s4", QCOM_RPM_PM8921_SMPS4, &pm8921_smps, "vdd_s4" },
  738. { "s7", QCOM_RPM_PM8921_SMPS7, &pm8921_smps, "vdd_s7" },
  739. { "s8", QCOM_RPM_PM8921_SMPS8, &pm8921_smps, "vdd_s8" },
  740. { "l1", QCOM_RPM_PM8921_LDO1, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
  741. { "l2", QCOM_RPM_PM8921_LDO2, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
  742. { "l3", QCOM_RPM_PM8921_LDO3, &pm8921_pldo, "vdd_l3_l15_l17" },
  743. { "l4", QCOM_RPM_PM8921_LDO4, &pm8921_pldo, "vdd_l4_l14" },
  744. { "l5", QCOM_RPM_PM8921_LDO5, &pm8921_pldo, "vdd_l5_l8_l16" },
  745. { "l6", QCOM_RPM_PM8921_LDO6, &pm8921_pldo, "vdd_l6_l7" },
  746. { "l7", QCOM_RPM_PM8921_LDO7, &pm8921_pldo, "vdd_l6_l7" },
  747. { "l8", QCOM_RPM_PM8921_LDO8, &pm8921_pldo, "vdd_l5_l8_l16" },
  748. { "l9", QCOM_RPM_PM8921_LDO9, &pm8921_pldo, "vdd_l9_l11" },
  749. { "l10", QCOM_RPM_PM8921_LDO10, &pm8921_pldo, "vdd_l10_l22" },
  750. { "l11", QCOM_RPM_PM8921_LDO11, &pm8921_pldo, "vdd_l9_l11" },
  751. { "l12", QCOM_RPM_PM8921_LDO12, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
  752. { "l14", QCOM_RPM_PM8921_LDO14, &pm8921_pldo, "vdd_l4_l14" },
  753. { "l15", QCOM_RPM_PM8921_LDO15, &pm8921_pldo, "vdd_l3_l15_l17" },
  754. { "l16", QCOM_RPM_PM8921_LDO16, &pm8921_pldo, "vdd_l5_l8_l16" },
  755. { "l17", QCOM_RPM_PM8921_LDO17, &pm8921_pldo, "vdd_l3_l15_l17" },
  756. { "l18", QCOM_RPM_PM8921_LDO18, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
  757. { "l21", QCOM_RPM_PM8921_LDO21, &pm8921_pldo, "vdd_l21_l23_l29" },
  758. { "l22", QCOM_RPM_PM8921_LDO22, &pm8921_pldo, "vdd_l10_l22" },
  759. { "l23", QCOM_RPM_PM8921_LDO23, &pm8921_pldo, "vdd_l21_l23_l29" },
  760. { "l24", QCOM_RPM_PM8921_LDO24, &pm8921_nldo1200, "vdd_l24" },
  761. { "l25", QCOM_RPM_PM8921_LDO25, &pm8921_nldo1200, "vdd_l25" },
  762. { "l26", QCOM_RPM_PM8921_LDO26, &pm8921_nldo1200, "vdd_l26" },
  763. { "l27", QCOM_RPM_PM8921_LDO27, &pm8921_nldo1200, "vdd_l27" },
  764. { "l28", QCOM_RPM_PM8921_LDO28, &pm8921_nldo1200, "vdd_l28" },
  765. { "l29", QCOM_RPM_PM8921_LDO29, &pm8921_pldo, "vdd_l21_l23_l29" },
  766. { "lvs1", QCOM_RPM_PM8921_LVS1, &pm8921_switch, "vin_lvs1_3_6" },
  767. { "lvs2", QCOM_RPM_PM8921_LVS2, &pm8921_switch, "vin_lvs2" },
  768. { "lvs3", QCOM_RPM_PM8921_LVS3, &pm8921_switch, "vin_lvs1_3_6" },
  769. { "lvs4", QCOM_RPM_PM8921_LVS4, &pm8921_switch, "vin_lvs4_5_7" },
  770. { "lvs5", QCOM_RPM_PM8921_LVS5, &pm8921_switch, "vin_lvs4_5_7" },
  771. { "lvs6", QCOM_RPM_PM8921_LVS6, &pm8921_switch, "vin_lvs1_3_6" },
  772. { "lvs7", QCOM_RPM_PM8921_LVS7, &pm8921_switch, "vin_lvs4_5_7" },
  773. { "usb-switch", QCOM_RPM_USB_OTG_SWITCH, &pm8921_switch, "vin_5vs" },
  774. { "hdmi-switch", QCOM_RPM_HDMI_SWITCH, &pm8921_switch, "vin_5vs" },
  775. { "ncp", QCOM_RPM_PM8921_NCP, &pm8921_ncp, "vdd_ncp" },
  776. { }
  777. };
  778. static const struct rpm_regulator_data rpm_smb208_regulators[] = {
  779. { "s1a", QCOM_RPM_SMB208_S1a, &smb208_smps, "vin_s1a" },
  780. { "s1b", QCOM_RPM_SMB208_S1b, &smb208_smps, "vin_s1b" },
  781. { "s2a", QCOM_RPM_SMB208_S2a, &smb208_smps, "vin_s2a" },
  782. { "s2b", QCOM_RPM_SMB208_S2b, &smb208_smps, "vin_s2b" },
  783. { }
  784. };
  785. static const struct of_device_id rpm_of_match[] = {
  786. { .compatible = "qcom,rpm-pm8018-regulators",
  787. .data = &rpm_pm8018_regulators },
  788. { .compatible = "qcom,rpm-pm8058-regulators", .data = &rpm_pm8058_regulators },
  789. { .compatible = "qcom,rpm-pm8901-regulators", .data = &rpm_pm8901_regulators },
  790. { .compatible = "qcom,rpm-pm8921-regulators", .data = &rpm_pm8921_regulators },
  791. { .compatible = "qcom,rpm-smb208-regulators", .data = &rpm_smb208_regulators },
  792. { }
  793. };
  794. MODULE_DEVICE_TABLE(of, rpm_of_match);
  795. static int rpm_reg_probe(struct platform_device *pdev)
  796. {
  797. const struct rpm_regulator_data *reg;
  798. const struct of_device_id *match;
  799. struct regulator_config config = { };
  800. struct regulator_dev *rdev;
  801. struct qcom_rpm_reg *vreg;
  802. struct qcom_rpm *rpm;
  803. rpm = dev_get_drvdata(pdev->dev.parent);
  804. if (!rpm) {
  805. dev_err(&pdev->dev, "unable to retrieve handle to rpm\n");
  806. return -ENODEV;
  807. }
  808. match = of_match_device(rpm_of_match, &pdev->dev);
  809. if (!match) {
  810. dev_err(&pdev->dev, "failed to match device\n");
  811. return -ENODEV;
  812. }
  813. for (reg = match->data; reg->name; reg++) {
  814. vreg = devm_kmalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
  815. if (!vreg)
  816. return -ENOMEM;
  817. memcpy(vreg, reg->template, sizeof(*vreg));
  818. mutex_init(&vreg->lock);
  819. vreg->dev = &pdev->dev;
  820. vreg->resource = reg->resource;
  821. vreg->rpm = rpm;
  822. vreg->desc.id = -1;
  823. vreg->desc.owner = THIS_MODULE;
  824. vreg->desc.type = REGULATOR_VOLTAGE;
  825. vreg->desc.name = reg->name;
  826. vreg->desc.supply_name = reg->supply;
  827. vreg->desc.of_match = reg->name;
  828. vreg->desc.of_parse_cb = rpm_reg_of_parse;
  829. config.dev = &pdev->dev;
  830. config.driver_data = vreg;
  831. rdev = devm_regulator_register(&pdev->dev, &vreg->desc, &config);
  832. if (IS_ERR(rdev)) {
  833. dev_err(&pdev->dev, "failed to register %s\n", reg->name);
  834. return PTR_ERR(rdev);
  835. }
  836. }
  837. return 0;
  838. }
  839. static struct platform_driver rpm_reg_driver = {
  840. .probe = rpm_reg_probe,
  841. .driver = {
  842. .name = "qcom_rpm_reg",
  843. .of_match_table = of_match_ptr(rpm_of_match),
  844. },
  845. };
  846. static int __init rpm_reg_init(void)
  847. {
  848. return platform_driver_register(&rpm_reg_driver);
  849. }
  850. subsys_initcall(rpm_reg_init);
  851. static void __exit rpm_reg_exit(void)
  852. {
  853. platform_driver_unregister(&rpm_reg_driver);
  854. }
  855. module_exit(rpm_reg_exit)
  856. MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
  857. MODULE_LICENSE("GPL v2");