mt6311-regulator.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2015 MediaTek Inc.
  4. * Author: Henry Chen <henryc.chen@mediatek.com>
  5. */
  6. #ifndef __MT6311_REGULATOR_H__
  7. #define __MT6311_REGULATOR_H__
  8. #define MT6311_SWCID 0x01
  9. #define MT6311_TOP_INT_CON 0x18
  10. #define MT6311_TOP_INT_MON 0x19
  11. #define MT6311_VDVFS11_CON0 0x87
  12. #define MT6311_VDVFS11_CON7 0x88
  13. #define MT6311_VDVFS11_CON8 0x89
  14. #define MT6311_VDVFS11_CON9 0x8A
  15. #define MT6311_VDVFS11_CON10 0x8B
  16. #define MT6311_VDVFS11_CON11 0x8C
  17. #define MT6311_VDVFS11_CON12 0x8D
  18. #define MT6311_VDVFS11_CON13 0x8E
  19. #define MT6311_VDVFS11_CON14 0x8F
  20. #define MT6311_VDVFS11_CON15 0x90
  21. #define MT6311_VDVFS11_CON16 0x91
  22. #define MT6311_VDVFS11_CON17 0x92
  23. #define MT6311_VDVFS11_CON18 0x93
  24. #define MT6311_VDVFS11_CON19 0x94
  25. #define MT6311_LDO_CON0 0xCC
  26. #define MT6311_LDO_OCFB0 0xCD
  27. #define MT6311_LDO_CON2 0xCE
  28. #define MT6311_LDO_CON3 0xCF
  29. #define MT6311_LDO_CON4 0xD0
  30. #define MT6311_FQMTR_CON0 0xD1
  31. #define MT6311_FQMTR_CON1 0xD2
  32. #define MT6311_FQMTR_CON2 0xD3
  33. #define MT6311_FQMTR_CON3 0xD4
  34. #define MT6311_FQMTR_CON4 0xD5
  35. #define MT6311_PMIC_RG_INT_POL_MASK 0x1
  36. #define MT6311_PMIC_RG_INT_EN_MASK 0x2
  37. #define MT6311_PMIC_RG_BUCK_OC_INT_STATUS_MASK 0x10
  38. #define MT6311_PMIC_VDVFS11_EN_CTRL_MASK 0x1
  39. #define MT6311_PMIC_VDVFS11_VOSEL_CTRL_MASK 0x2
  40. #define MT6311_PMIC_VDVFS11_EN_SEL_MASK 0x3
  41. #define MT6311_PMIC_VDVFS11_VOSEL_SEL_MASK 0xc
  42. #define MT6311_PMIC_VDVFS11_EN_MASK 0x1
  43. #define MT6311_PMIC_VDVFS11_VOSEL_MASK 0x7F
  44. #define MT6311_PMIC_VDVFS11_VOSEL_ON_MASK 0x7F
  45. #define MT6311_PMIC_VDVFS11_VOSEL_SLEEP_MASK 0x7F
  46. #define MT6311_PMIC_NI_VDVFS11_VOSEL_MASK 0x7F
  47. #define MT6311_PMIC_RG_VBIASN_EN_MASK 0x1
  48. #endif