lp8788-ldo.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * TI LP8788 MFD - ldo regulator driver
  4. *
  5. * Copyright 2012 Texas Instruments
  6. *
  7. * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/slab.h>
  11. #include <linux/err.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regulator/driver.h>
  14. #include <linux/gpio/consumer.h>
  15. #include <linux/mfd/lp8788.h>
  16. /* register address */
  17. #define LP8788_EN_LDO_A 0x0D /* DLDO 1 ~ 8 */
  18. #define LP8788_EN_LDO_B 0x0E /* DLDO 9 ~ 12, ALDO 1 ~ 4 */
  19. #define LP8788_EN_LDO_C 0x0F /* ALDO 5 ~ 10 */
  20. #define LP8788_EN_SEL 0x10
  21. #define LP8788_DLDO1_VOUT 0x2E
  22. #define LP8788_DLDO2_VOUT 0x2F
  23. #define LP8788_DLDO3_VOUT 0x30
  24. #define LP8788_DLDO4_VOUT 0x31
  25. #define LP8788_DLDO5_VOUT 0x32
  26. #define LP8788_DLDO6_VOUT 0x33
  27. #define LP8788_DLDO7_VOUT 0x34
  28. #define LP8788_DLDO8_VOUT 0x35
  29. #define LP8788_DLDO9_VOUT 0x36
  30. #define LP8788_DLDO10_VOUT 0x37
  31. #define LP8788_DLDO11_VOUT 0x38
  32. #define LP8788_DLDO12_VOUT 0x39
  33. #define LP8788_ALDO1_VOUT 0x3A
  34. #define LP8788_ALDO2_VOUT 0x3B
  35. #define LP8788_ALDO3_VOUT 0x3C
  36. #define LP8788_ALDO4_VOUT 0x3D
  37. #define LP8788_ALDO5_VOUT 0x3E
  38. #define LP8788_ALDO6_VOUT 0x3F
  39. #define LP8788_ALDO7_VOUT 0x40
  40. #define LP8788_ALDO8_VOUT 0x41
  41. #define LP8788_ALDO9_VOUT 0x42
  42. #define LP8788_ALDO10_VOUT 0x43
  43. #define LP8788_DLDO1_TIMESTEP 0x44
  44. /* mask/shift bits */
  45. #define LP8788_EN_DLDO1_M BIT(0) /* Addr 0Dh ~ 0Fh */
  46. #define LP8788_EN_DLDO2_M BIT(1)
  47. #define LP8788_EN_DLDO3_M BIT(2)
  48. #define LP8788_EN_DLDO4_M BIT(3)
  49. #define LP8788_EN_DLDO5_M BIT(4)
  50. #define LP8788_EN_DLDO6_M BIT(5)
  51. #define LP8788_EN_DLDO7_M BIT(6)
  52. #define LP8788_EN_DLDO8_M BIT(7)
  53. #define LP8788_EN_DLDO9_M BIT(0)
  54. #define LP8788_EN_DLDO10_M BIT(1)
  55. #define LP8788_EN_DLDO11_M BIT(2)
  56. #define LP8788_EN_DLDO12_M BIT(3)
  57. #define LP8788_EN_ALDO1_M BIT(4)
  58. #define LP8788_EN_ALDO2_M BIT(5)
  59. #define LP8788_EN_ALDO3_M BIT(6)
  60. #define LP8788_EN_ALDO4_M BIT(7)
  61. #define LP8788_EN_ALDO5_M BIT(0)
  62. #define LP8788_EN_ALDO6_M BIT(1)
  63. #define LP8788_EN_ALDO7_M BIT(2)
  64. #define LP8788_EN_ALDO8_M BIT(3)
  65. #define LP8788_EN_ALDO9_M BIT(4)
  66. #define LP8788_EN_ALDO10_M BIT(5)
  67. #define LP8788_EN_SEL_DLDO911_M BIT(0) /* Addr 10h */
  68. #define LP8788_EN_SEL_DLDO7_M BIT(1)
  69. #define LP8788_EN_SEL_ALDO7_M BIT(2)
  70. #define LP8788_EN_SEL_ALDO5_M BIT(3)
  71. #define LP8788_EN_SEL_ALDO234_M BIT(4)
  72. #define LP8788_EN_SEL_ALDO1_M BIT(5)
  73. #define LP8788_VOUT_5BIT_M 0x1F /* Addr 2Eh ~ 43h */
  74. #define LP8788_VOUT_4BIT_M 0x0F
  75. #define LP8788_VOUT_3BIT_M 0x07
  76. #define LP8788_VOUT_1BIT_M 0x01
  77. #define LP8788_STARTUP_TIME_M 0xF8 /* Addr 44h ~ 59h */
  78. #define LP8788_STARTUP_TIME_S 3
  79. #define ENABLE_TIME_USEC 32
  80. enum lp8788_ldo_id {
  81. DLDO1,
  82. DLDO2,
  83. DLDO3,
  84. DLDO4,
  85. DLDO5,
  86. DLDO6,
  87. DLDO7,
  88. DLDO8,
  89. DLDO9,
  90. DLDO10,
  91. DLDO11,
  92. DLDO12,
  93. ALDO1,
  94. ALDO2,
  95. ALDO3,
  96. ALDO4,
  97. ALDO5,
  98. ALDO6,
  99. ALDO7,
  100. ALDO8,
  101. ALDO9,
  102. ALDO10,
  103. };
  104. struct lp8788_ldo {
  105. struct lp8788 *lp;
  106. struct regulator_desc *desc;
  107. struct regulator_dev *regulator;
  108. struct gpio_desc *ena_gpiod;
  109. };
  110. /* DLDO 1, 2, 3, 9 voltage table */
  111. static const int lp8788_dldo1239_vtbl[] = {
  112. 1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
  113. 2600000, 2700000, 2800000, 2900000, 3000000, 2850000, 2850000, 2850000,
  114. 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
  115. 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
  116. };
  117. /* DLDO 4 voltage table */
  118. static const int lp8788_dldo4_vtbl[] = { 1800000, 3000000 };
  119. /* DLDO 5, 7, 8 and ALDO 6 voltage table */
  120. static const int lp8788_dldo578_aldo6_vtbl[] = {
  121. 1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
  122. 2600000, 2700000, 2800000, 2900000, 3000000, 3000000, 3000000, 3000000,
  123. };
  124. /* DLDO 6 voltage table */
  125. static const int lp8788_dldo6_vtbl[] = {
  126. 3000000, 3100000, 3200000, 3300000, 3400000, 3500000, 3600000, 3600000,
  127. };
  128. /* DLDO 10, 11 voltage table */
  129. static const int lp8788_dldo1011_vtbl[] = {
  130. 1100000, 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000,
  131. 1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000,
  132. };
  133. /* ALDO 1 voltage table */
  134. static const int lp8788_aldo1_vtbl[] = { 1800000, 2850000 };
  135. /* ALDO 7 voltage table */
  136. static const int lp8788_aldo7_vtbl[] = {
  137. 1200000, 1300000, 1400000, 1500000, 1600000, 1700000, 1800000, 1800000,
  138. };
  139. static int lp8788_ldo_enable_time(struct regulator_dev *rdev)
  140. {
  141. struct lp8788_ldo *ldo = rdev_get_drvdata(rdev);
  142. enum lp8788_ldo_id id = rdev_get_id(rdev);
  143. u8 val, addr = LP8788_DLDO1_TIMESTEP + id;
  144. if (lp8788_read_byte(ldo->lp, addr, &val))
  145. return -EINVAL;
  146. val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S;
  147. return ENABLE_TIME_USEC * val;
  148. }
  149. static const struct regulator_ops lp8788_ldo_voltage_table_ops = {
  150. .list_voltage = regulator_list_voltage_table,
  151. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  152. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  153. .enable = regulator_enable_regmap,
  154. .disable = regulator_disable_regmap,
  155. .is_enabled = regulator_is_enabled_regmap,
  156. .enable_time = lp8788_ldo_enable_time,
  157. };
  158. static const struct regulator_ops lp8788_ldo_voltage_fixed_ops = {
  159. .list_voltage = regulator_list_voltage_linear,
  160. .enable = regulator_enable_regmap,
  161. .disable = regulator_disable_regmap,
  162. .is_enabled = regulator_is_enabled_regmap,
  163. .enable_time = lp8788_ldo_enable_time,
  164. };
  165. static const struct regulator_desc lp8788_dldo_desc[] = {
  166. {
  167. .name = "dldo1",
  168. .id = DLDO1,
  169. .ops = &lp8788_ldo_voltage_table_ops,
  170. .n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
  171. .volt_table = lp8788_dldo1239_vtbl,
  172. .type = REGULATOR_VOLTAGE,
  173. .owner = THIS_MODULE,
  174. .vsel_reg = LP8788_DLDO1_VOUT,
  175. .vsel_mask = LP8788_VOUT_5BIT_M,
  176. .enable_reg = LP8788_EN_LDO_A,
  177. .enable_mask = LP8788_EN_DLDO1_M,
  178. },
  179. {
  180. .name = "dldo2",
  181. .id = DLDO2,
  182. .ops = &lp8788_ldo_voltage_table_ops,
  183. .n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
  184. .volt_table = lp8788_dldo1239_vtbl,
  185. .type = REGULATOR_VOLTAGE,
  186. .owner = THIS_MODULE,
  187. .vsel_reg = LP8788_DLDO2_VOUT,
  188. .vsel_mask = LP8788_VOUT_5BIT_M,
  189. .enable_reg = LP8788_EN_LDO_A,
  190. .enable_mask = LP8788_EN_DLDO2_M,
  191. },
  192. {
  193. .name = "dldo3",
  194. .id = DLDO3,
  195. .ops = &lp8788_ldo_voltage_table_ops,
  196. .n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
  197. .volt_table = lp8788_dldo1239_vtbl,
  198. .type = REGULATOR_VOLTAGE,
  199. .owner = THIS_MODULE,
  200. .vsel_reg = LP8788_DLDO3_VOUT,
  201. .vsel_mask = LP8788_VOUT_5BIT_M,
  202. .enable_reg = LP8788_EN_LDO_A,
  203. .enable_mask = LP8788_EN_DLDO3_M,
  204. },
  205. {
  206. .name = "dldo4",
  207. .id = DLDO4,
  208. .ops = &lp8788_ldo_voltage_table_ops,
  209. .n_voltages = ARRAY_SIZE(lp8788_dldo4_vtbl),
  210. .volt_table = lp8788_dldo4_vtbl,
  211. .type = REGULATOR_VOLTAGE,
  212. .owner = THIS_MODULE,
  213. .vsel_reg = LP8788_DLDO4_VOUT,
  214. .vsel_mask = LP8788_VOUT_1BIT_M,
  215. .enable_reg = LP8788_EN_LDO_A,
  216. .enable_mask = LP8788_EN_DLDO4_M,
  217. },
  218. {
  219. .name = "dldo5",
  220. .id = DLDO5,
  221. .ops = &lp8788_ldo_voltage_table_ops,
  222. .n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
  223. .volt_table = lp8788_dldo578_aldo6_vtbl,
  224. .type = REGULATOR_VOLTAGE,
  225. .owner = THIS_MODULE,
  226. .vsel_reg = LP8788_DLDO5_VOUT,
  227. .vsel_mask = LP8788_VOUT_4BIT_M,
  228. .enable_reg = LP8788_EN_LDO_A,
  229. .enable_mask = LP8788_EN_DLDO5_M,
  230. },
  231. {
  232. .name = "dldo6",
  233. .id = DLDO6,
  234. .ops = &lp8788_ldo_voltage_table_ops,
  235. .n_voltages = ARRAY_SIZE(lp8788_dldo6_vtbl),
  236. .volt_table = lp8788_dldo6_vtbl,
  237. .type = REGULATOR_VOLTAGE,
  238. .owner = THIS_MODULE,
  239. .vsel_reg = LP8788_DLDO6_VOUT,
  240. .vsel_mask = LP8788_VOUT_3BIT_M,
  241. .enable_reg = LP8788_EN_LDO_A,
  242. .enable_mask = LP8788_EN_DLDO6_M,
  243. },
  244. {
  245. .name = "dldo7",
  246. .id = DLDO7,
  247. .ops = &lp8788_ldo_voltage_table_ops,
  248. .n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
  249. .volt_table = lp8788_dldo578_aldo6_vtbl,
  250. .type = REGULATOR_VOLTAGE,
  251. .owner = THIS_MODULE,
  252. .vsel_reg = LP8788_DLDO7_VOUT,
  253. .vsel_mask = LP8788_VOUT_4BIT_M,
  254. .enable_reg = LP8788_EN_LDO_A,
  255. .enable_mask = LP8788_EN_DLDO7_M,
  256. },
  257. {
  258. .name = "dldo8",
  259. .id = DLDO8,
  260. .ops = &lp8788_ldo_voltage_table_ops,
  261. .n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
  262. .volt_table = lp8788_dldo578_aldo6_vtbl,
  263. .type = REGULATOR_VOLTAGE,
  264. .owner = THIS_MODULE,
  265. .vsel_reg = LP8788_DLDO8_VOUT,
  266. .vsel_mask = LP8788_VOUT_4BIT_M,
  267. .enable_reg = LP8788_EN_LDO_A,
  268. .enable_mask = LP8788_EN_DLDO8_M,
  269. },
  270. {
  271. .name = "dldo9",
  272. .id = DLDO9,
  273. .ops = &lp8788_ldo_voltage_table_ops,
  274. .n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
  275. .volt_table = lp8788_dldo1239_vtbl,
  276. .type = REGULATOR_VOLTAGE,
  277. .owner = THIS_MODULE,
  278. .vsel_reg = LP8788_DLDO9_VOUT,
  279. .vsel_mask = LP8788_VOUT_5BIT_M,
  280. .enable_reg = LP8788_EN_LDO_B,
  281. .enable_mask = LP8788_EN_DLDO9_M,
  282. },
  283. {
  284. .name = "dldo10",
  285. .id = DLDO10,
  286. .ops = &lp8788_ldo_voltage_table_ops,
  287. .n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
  288. .volt_table = lp8788_dldo1011_vtbl,
  289. .type = REGULATOR_VOLTAGE,
  290. .owner = THIS_MODULE,
  291. .vsel_reg = LP8788_DLDO10_VOUT,
  292. .vsel_mask = LP8788_VOUT_4BIT_M,
  293. .enable_reg = LP8788_EN_LDO_B,
  294. .enable_mask = LP8788_EN_DLDO10_M,
  295. },
  296. {
  297. .name = "dldo11",
  298. .id = DLDO11,
  299. .ops = &lp8788_ldo_voltage_table_ops,
  300. .n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
  301. .volt_table = lp8788_dldo1011_vtbl,
  302. .type = REGULATOR_VOLTAGE,
  303. .owner = THIS_MODULE,
  304. .vsel_reg = LP8788_DLDO11_VOUT,
  305. .vsel_mask = LP8788_VOUT_4BIT_M,
  306. .enable_reg = LP8788_EN_LDO_B,
  307. .enable_mask = LP8788_EN_DLDO11_M,
  308. },
  309. {
  310. .name = "dldo12",
  311. .id = DLDO12,
  312. .ops = &lp8788_ldo_voltage_fixed_ops,
  313. .n_voltages = 1,
  314. .type = REGULATOR_VOLTAGE,
  315. .owner = THIS_MODULE,
  316. .enable_reg = LP8788_EN_LDO_B,
  317. .enable_mask = LP8788_EN_DLDO12_M,
  318. .min_uV = 2500000,
  319. },
  320. };
  321. static const struct regulator_desc lp8788_aldo_desc[] = {
  322. {
  323. .name = "aldo1",
  324. .id = ALDO1,
  325. .ops = &lp8788_ldo_voltage_table_ops,
  326. .n_voltages = ARRAY_SIZE(lp8788_aldo1_vtbl),
  327. .volt_table = lp8788_aldo1_vtbl,
  328. .type = REGULATOR_VOLTAGE,
  329. .owner = THIS_MODULE,
  330. .vsel_reg = LP8788_ALDO1_VOUT,
  331. .vsel_mask = LP8788_VOUT_1BIT_M,
  332. .enable_reg = LP8788_EN_LDO_B,
  333. .enable_mask = LP8788_EN_ALDO1_M,
  334. },
  335. {
  336. .name = "aldo2",
  337. .id = ALDO2,
  338. .ops = &lp8788_ldo_voltage_fixed_ops,
  339. .n_voltages = 1,
  340. .type = REGULATOR_VOLTAGE,
  341. .owner = THIS_MODULE,
  342. .enable_reg = LP8788_EN_LDO_B,
  343. .enable_mask = LP8788_EN_ALDO2_M,
  344. .min_uV = 2850000,
  345. },
  346. {
  347. .name = "aldo3",
  348. .id = ALDO3,
  349. .ops = &lp8788_ldo_voltage_fixed_ops,
  350. .n_voltages = 1,
  351. .type = REGULATOR_VOLTAGE,
  352. .owner = THIS_MODULE,
  353. .enable_reg = LP8788_EN_LDO_B,
  354. .enable_mask = LP8788_EN_ALDO3_M,
  355. .min_uV = 2850000,
  356. },
  357. {
  358. .name = "aldo4",
  359. .id = ALDO4,
  360. .ops = &lp8788_ldo_voltage_fixed_ops,
  361. .n_voltages = 1,
  362. .type = REGULATOR_VOLTAGE,
  363. .owner = THIS_MODULE,
  364. .enable_reg = LP8788_EN_LDO_B,
  365. .enable_mask = LP8788_EN_ALDO4_M,
  366. .min_uV = 2850000,
  367. },
  368. {
  369. .name = "aldo5",
  370. .id = ALDO5,
  371. .ops = &lp8788_ldo_voltage_fixed_ops,
  372. .n_voltages = 1,
  373. .type = REGULATOR_VOLTAGE,
  374. .owner = THIS_MODULE,
  375. .enable_reg = LP8788_EN_LDO_C,
  376. .enable_mask = LP8788_EN_ALDO5_M,
  377. .min_uV = 2850000,
  378. },
  379. {
  380. .name = "aldo6",
  381. .id = ALDO6,
  382. .ops = &lp8788_ldo_voltage_table_ops,
  383. .n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
  384. .volt_table = lp8788_dldo578_aldo6_vtbl,
  385. .type = REGULATOR_VOLTAGE,
  386. .owner = THIS_MODULE,
  387. .vsel_reg = LP8788_ALDO6_VOUT,
  388. .vsel_mask = LP8788_VOUT_4BIT_M,
  389. .enable_reg = LP8788_EN_LDO_C,
  390. .enable_mask = LP8788_EN_ALDO6_M,
  391. },
  392. {
  393. .name = "aldo7",
  394. .id = ALDO7,
  395. .ops = &lp8788_ldo_voltage_table_ops,
  396. .n_voltages = ARRAY_SIZE(lp8788_aldo7_vtbl),
  397. .volt_table = lp8788_aldo7_vtbl,
  398. .type = REGULATOR_VOLTAGE,
  399. .owner = THIS_MODULE,
  400. .vsel_reg = LP8788_ALDO7_VOUT,
  401. .vsel_mask = LP8788_VOUT_3BIT_M,
  402. .enable_reg = LP8788_EN_LDO_C,
  403. .enable_mask = LP8788_EN_ALDO7_M,
  404. },
  405. {
  406. .name = "aldo8",
  407. .id = ALDO8,
  408. .ops = &lp8788_ldo_voltage_fixed_ops,
  409. .n_voltages = 1,
  410. .type = REGULATOR_VOLTAGE,
  411. .owner = THIS_MODULE,
  412. .enable_reg = LP8788_EN_LDO_C,
  413. .enable_mask = LP8788_EN_ALDO8_M,
  414. .min_uV = 2500000,
  415. },
  416. {
  417. .name = "aldo9",
  418. .id = ALDO9,
  419. .ops = &lp8788_ldo_voltage_fixed_ops,
  420. .n_voltages = 1,
  421. .type = REGULATOR_VOLTAGE,
  422. .owner = THIS_MODULE,
  423. .enable_reg = LP8788_EN_LDO_C,
  424. .enable_mask = LP8788_EN_ALDO9_M,
  425. .min_uV = 2500000,
  426. },
  427. {
  428. .name = "aldo10",
  429. .id = ALDO10,
  430. .ops = &lp8788_ldo_voltage_fixed_ops,
  431. .n_voltages = 1,
  432. .type = REGULATOR_VOLTAGE,
  433. .owner = THIS_MODULE,
  434. .enable_reg = LP8788_EN_LDO_C,
  435. .enable_mask = LP8788_EN_ALDO10_M,
  436. .min_uV = 1100000,
  437. },
  438. };
  439. static int lp8788_config_ldo_enable_mode(struct platform_device *pdev,
  440. struct lp8788_ldo *ldo,
  441. enum lp8788_ldo_id id)
  442. {
  443. struct lp8788 *lp = ldo->lp;
  444. enum lp8788_ext_ldo_en_id enable_id;
  445. static const u8 en_mask[] = {
  446. [EN_ALDO1] = LP8788_EN_SEL_ALDO1_M,
  447. [EN_ALDO234] = LP8788_EN_SEL_ALDO234_M,
  448. [EN_ALDO5] = LP8788_EN_SEL_ALDO5_M,
  449. [EN_ALDO7] = LP8788_EN_SEL_ALDO7_M,
  450. [EN_DLDO7] = LP8788_EN_SEL_DLDO7_M,
  451. [EN_DLDO911] = LP8788_EN_SEL_DLDO911_M,
  452. };
  453. switch (id) {
  454. case DLDO7:
  455. enable_id = EN_DLDO7;
  456. break;
  457. case DLDO9:
  458. case DLDO11:
  459. enable_id = EN_DLDO911;
  460. break;
  461. case ALDO1:
  462. enable_id = EN_ALDO1;
  463. break;
  464. case ALDO2 ... ALDO4:
  465. enable_id = EN_ALDO234;
  466. break;
  467. case ALDO5:
  468. enable_id = EN_ALDO5;
  469. break;
  470. case ALDO7:
  471. enable_id = EN_ALDO7;
  472. break;
  473. default:
  474. return 0;
  475. }
  476. /*
  477. * Do not use devm* here: the regulator core takes over the
  478. * lifecycle management of the GPIO descriptor.
  479. * FIXME: check default mode for GPIO here: high or low?
  480. */
  481. ldo->ena_gpiod = gpiod_get_index_optional(&pdev->dev,
  482. "enable",
  483. enable_id,
  484. GPIOD_OUT_HIGH |
  485. GPIOD_FLAGS_BIT_NONEXCLUSIVE);
  486. if (IS_ERR(ldo->ena_gpiod))
  487. return PTR_ERR(ldo->ena_gpiod);
  488. /* if no GPIO for ldo pin, then set default enable mode */
  489. if (!ldo->ena_gpiod)
  490. goto set_default_ldo_enable_mode;
  491. return 0;
  492. set_default_ldo_enable_mode:
  493. return lp8788_update_bits(lp, LP8788_EN_SEL, en_mask[enable_id], 0);
  494. }
  495. static int lp8788_dldo_probe(struct platform_device *pdev)
  496. {
  497. struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
  498. int id = pdev->id;
  499. struct lp8788_ldo *ldo;
  500. struct regulator_config cfg = { };
  501. struct regulator_dev *rdev;
  502. int ret;
  503. ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
  504. if (!ldo)
  505. return -ENOMEM;
  506. ldo->lp = lp;
  507. ret = lp8788_config_ldo_enable_mode(pdev, ldo, id);
  508. if (ret)
  509. return ret;
  510. if (ldo->ena_gpiod)
  511. cfg.ena_gpiod = ldo->ena_gpiod;
  512. cfg.dev = pdev->dev.parent;
  513. cfg.init_data = lp->pdata ? lp->pdata->dldo_data[id] : NULL;
  514. cfg.driver_data = ldo;
  515. cfg.regmap = lp->regmap;
  516. rdev = devm_regulator_register(&pdev->dev, &lp8788_dldo_desc[id], &cfg);
  517. if (IS_ERR(rdev)) {
  518. ret = PTR_ERR(rdev);
  519. dev_err(&pdev->dev, "DLDO%d regulator register err = %d\n",
  520. id + 1, ret);
  521. return ret;
  522. }
  523. ldo->regulator = rdev;
  524. platform_set_drvdata(pdev, ldo);
  525. return 0;
  526. }
  527. static struct platform_driver lp8788_dldo_driver = {
  528. .probe = lp8788_dldo_probe,
  529. .driver = {
  530. .name = LP8788_DEV_DLDO,
  531. },
  532. };
  533. static int lp8788_aldo_probe(struct platform_device *pdev)
  534. {
  535. struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
  536. int id = pdev->id;
  537. struct lp8788_ldo *ldo;
  538. struct regulator_config cfg = { };
  539. struct regulator_dev *rdev;
  540. int ret;
  541. ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
  542. if (!ldo)
  543. return -ENOMEM;
  544. ldo->lp = lp;
  545. ret = lp8788_config_ldo_enable_mode(pdev, ldo, id + ALDO1);
  546. if (ret)
  547. return ret;
  548. if (ldo->ena_gpiod)
  549. cfg.ena_gpiod = ldo->ena_gpiod;
  550. cfg.dev = pdev->dev.parent;
  551. cfg.init_data = lp->pdata ? lp->pdata->aldo_data[id] : NULL;
  552. cfg.driver_data = ldo;
  553. cfg.regmap = lp->regmap;
  554. rdev = devm_regulator_register(&pdev->dev, &lp8788_aldo_desc[id], &cfg);
  555. if (IS_ERR(rdev)) {
  556. ret = PTR_ERR(rdev);
  557. dev_err(&pdev->dev, "ALDO%d regulator register err = %d\n",
  558. id + 1, ret);
  559. return ret;
  560. }
  561. ldo->regulator = rdev;
  562. platform_set_drvdata(pdev, ldo);
  563. return 0;
  564. }
  565. static struct platform_driver lp8788_aldo_driver = {
  566. .probe = lp8788_aldo_probe,
  567. .driver = {
  568. .name = LP8788_DEV_ALDO,
  569. },
  570. };
  571. static struct platform_driver * const drivers[] = {
  572. &lp8788_dldo_driver,
  573. &lp8788_aldo_driver,
  574. };
  575. static int __init lp8788_ldo_init(void)
  576. {
  577. return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  578. }
  579. subsys_initcall(lp8788_ldo_init);
  580. static void __exit lp8788_ldo_exit(void)
  581. {
  582. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  583. }
  584. module_exit(lp8788_ldo_exit);
  585. MODULE_DESCRIPTION("TI LP8788 LDO Driver");
  586. MODULE_AUTHOR("Milo Kim");
  587. MODULE_LICENSE("GPL");
  588. MODULE_ALIAS("platform:lp8788-dldo");
  589. MODULE_ALIAS("platform:lp8788-aldo");