lp3972.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Regulator driver for National Semiconductors LP3972 PMIC chip
  4. *
  5. * Based on lp3971.c
  6. */
  7. #include <linux/bug.h>
  8. #include <linux/err.h>
  9. #include <linux/i2c.h>
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/regulator/driver.h>
  13. #include <linux/regulator/lp3972.h>
  14. #include <linux/slab.h>
  15. struct lp3972 {
  16. struct device *dev;
  17. struct mutex io_lock;
  18. struct i2c_client *i2c;
  19. };
  20. /* LP3972 Control Registers */
  21. #define LP3972_SCR_REG 0x07
  22. #define LP3972_OVER1_REG 0x10
  23. #define LP3972_OVSR1_REG 0x11
  24. #define LP3972_OVER2_REG 0x12
  25. #define LP3972_OVSR2_REG 0x13
  26. #define LP3972_VCC1_REG 0x20
  27. #define LP3972_ADTV1_REG 0x23
  28. #define LP3972_ADTV2_REG 0x24
  29. #define LP3972_AVRC_REG 0x25
  30. #define LP3972_CDTC1_REG 0x26
  31. #define LP3972_CDTC2_REG 0x27
  32. #define LP3972_SDTV1_REG 0x29
  33. #define LP3972_SDTV2_REG 0x2A
  34. #define LP3972_MDTV1_REG 0x32
  35. #define LP3972_MDTV2_REG 0x33
  36. #define LP3972_L2VCR_REG 0x39
  37. #define LP3972_L34VCR_REG 0x3A
  38. #define LP3972_SCR1_REG 0x80
  39. #define LP3972_SCR2_REG 0x81
  40. #define LP3972_OEN3_REG 0x82
  41. #define LP3972_OSR3_REG 0x83
  42. #define LP3972_LOER4_REG 0x84
  43. #define LP3972_B2TV_REG 0x85
  44. #define LP3972_B3TV_REG 0x86
  45. #define LP3972_B32RC_REG 0x87
  46. #define LP3972_ISRA_REG 0x88
  47. #define LP3972_BCCR_REG 0x89
  48. #define LP3972_II1RR_REG 0x8E
  49. #define LP3972_II2RR_REG 0x8F
  50. #define LP3972_SYS_CONTROL1_REG LP3972_SCR1_REG
  51. /* System control register 1 initial value,
  52. * bits 5, 6 and 7 are EPROM programmable */
  53. #define SYS_CONTROL1_INIT_VAL 0x02
  54. #define SYS_CONTROL1_INIT_MASK 0x1F
  55. #define LP3972_VOL_CHANGE_REG LP3972_VCC1_REG
  56. #define LP3972_VOL_CHANGE_FLAG_GO 0x01
  57. #define LP3972_VOL_CHANGE_FLAG_MASK 0x03
  58. /* LDO output enable mask */
  59. #define LP3972_OEN3_L1EN BIT(0)
  60. #define LP3972_OVER2_LDO2_EN BIT(2)
  61. #define LP3972_OVER2_LDO3_EN BIT(3)
  62. #define LP3972_OVER2_LDO4_EN BIT(4)
  63. #define LP3972_OVER1_S_EN BIT(2)
  64. static const unsigned int ldo1_voltage_map[] = {
  65. 1700000, 1725000, 1750000, 1775000, 1800000, 1825000, 1850000, 1875000,
  66. 1900000, 1925000, 1950000, 1975000, 2000000,
  67. };
  68. static const unsigned int ldo23_voltage_map[] = {
  69. 1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
  70. 2600000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
  71. };
  72. static const unsigned int ldo4_voltage_map[] = {
  73. 1000000, 1050000, 1100000, 1150000, 1200000, 1250000, 1300000, 1350000,
  74. 1400000, 1500000, 1800000, 1900000, 2500000, 2800000, 3000000, 3300000,
  75. };
  76. static const unsigned int ldo5_voltage_map[] = {
  77. 0, 0, 0, 0, 0, 850000, 875000, 900000,
  78. 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000, 1100000,
  79. 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000,
  80. 1325000, 1350000, 1375000, 1400000, 1425000, 1450000, 1475000, 1500000,
  81. };
  82. static const unsigned int buck1_voltage_map[] = {
  83. 725000, 750000, 775000, 800000, 825000, 850000, 875000, 900000,
  84. 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000, 1100000,
  85. 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000,
  86. 1325000, 1350000, 1375000, 1400000, 1425000, 1450000, 1475000, 1500000,
  87. };
  88. static const unsigned int buck23_voltage_map[] = {
  89. 0, 800000, 850000, 900000, 950000, 1000000, 1050000, 1100000,
  90. 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000,
  91. 1550000, 1600000, 1650000, 1700000, 1800000, 1900000, 2500000, 2800000,
  92. 3000000, 3300000,
  93. };
  94. static const int ldo_output_enable_mask[] = {
  95. LP3972_OEN3_L1EN,
  96. LP3972_OVER2_LDO2_EN,
  97. LP3972_OVER2_LDO3_EN,
  98. LP3972_OVER2_LDO4_EN,
  99. LP3972_OVER1_S_EN,
  100. };
  101. static const int ldo_output_enable_addr[] = {
  102. LP3972_OEN3_REG,
  103. LP3972_OVER2_REG,
  104. LP3972_OVER2_REG,
  105. LP3972_OVER2_REG,
  106. LP3972_OVER1_REG,
  107. };
  108. static const int ldo_vol_ctl_addr[] = {
  109. LP3972_MDTV1_REG,
  110. LP3972_L2VCR_REG,
  111. LP3972_L34VCR_REG,
  112. LP3972_L34VCR_REG,
  113. LP3972_SDTV1_REG,
  114. };
  115. static const int buck_vol_enable_addr[] = {
  116. LP3972_OVER1_REG,
  117. LP3972_OEN3_REG,
  118. LP3972_OEN3_REG,
  119. };
  120. static const int buck_base_addr[] = {
  121. LP3972_ADTV1_REG,
  122. LP3972_B2TV_REG,
  123. LP3972_B3TV_REG,
  124. };
  125. #define LP3972_LDO_OUTPUT_ENABLE_MASK(x) (ldo_output_enable_mask[x])
  126. #define LP3972_LDO_OUTPUT_ENABLE_REG(x) (ldo_output_enable_addr[x])
  127. /* LDO voltage control registers shift:
  128. LP3972_LDO1 -> 0, LP3972_LDO2 -> 4
  129. LP3972_LDO3 -> 0, LP3972_LDO4 -> 4
  130. LP3972_LDO5 -> 0
  131. */
  132. #define LP3972_LDO_VOL_CONTR_SHIFT(x) (((x) & 1) << 2)
  133. #define LP3972_LDO_VOL_CONTR_REG(x) (ldo_vol_ctl_addr[x])
  134. #define LP3972_LDO_VOL_CHANGE_SHIFT(x) ((x) ? 4 : 6)
  135. #define LP3972_LDO_VOL_MASK(x) (((x) % 4) ? 0x0f : 0x1f)
  136. #define LP3972_LDO_VOL_MIN_IDX(x) (((x) == 4) ? 0x05 : 0x00)
  137. #define LP3972_LDO_VOL_MAX_IDX(x) ((x) ? (((x) == 4) ? 0x1f : 0x0f) : 0x0c)
  138. #define LP3972_BUCK_VOL_ENABLE_REG(x) (buck_vol_enable_addr[x])
  139. #define LP3972_BUCK_VOL1_REG(x) (buck_base_addr[x])
  140. #define LP3972_BUCK_VOL_MASK 0x1f
  141. static int lp3972_i2c_read(struct i2c_client *i2c, char reg, int count,
  142. u16 *dest)
  143. {
  144. int ret;
  145. if (count != 1)
  146. return -EIO;
  147. ret = i2c_smbus_read_byte_data(i2c, reg);
  148. if (ret < 0)
  149. return ret;
  150. *dest = ret;
  151. return 0;
  152. }
  153. static int lp3972_i2c_write(struct i2c_client *i2c, char reg, int count,
  154. const u16 *src)
  155. {
  156. if (count != 1)
  157. return -EIO;
  158. return i2c_smbus_write_byte_data(i2c, reg, *src);
  159. }
  160. static u8 lp3972_reg_read(struct lp3972 *lp3972, u8 reg)
  161. {
  162. u16 val = 0;
  163. mutex_lock(&lp3972->io_lock);
  164. lp3972_i2c_read(lp3972->i2c, reg, 1, &val);
  165. dev_dbg(lp3972->dev, "reg read 0x%02x -> 0x%02x\n", (int)reg,
  166. (unsigned)val & 0xff);
  167. mutex_unlock(&lp3972->io_lock);
  168. return val & 0xff;
  169. }
  170. static int lp3972_set_bits(struct lp3972 *lp3972, u8 reg, u16 mask, u16 val)
  171. {
  172. u16 tmp;
  173. int ret;
  174. mutex_lock(&lp3972->io_lock);
  175. ret = lp3972_i2c_read(lp3972->i2c, reg, 1, &tmp);
  176. if (ret == 0) {
  177. tmp = (tmp & ~mask) | val;
  178. ret = lp3972_i2c_write(lp3972->i2c, reg, 1, &tmp);
  179. dev_dbg(lp3972->dev, "reg write 0x%02x -> 0x%02x\n", (int)reg,
  180. (unsigned)val & 0xff);
  181. }
  182. mutex_unlock(&lp3972->io_lock);
  183. return ret;
  184. }
  185. static int lp3972_ldo_is_enabled(struct regulator_dev *dev)
  186. {
  187. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  188. int ldo = rdev_get_id(dev) - LP3972_LDO1;
  189. u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo);
  190. u16 val;
  191. val = lp3972_reg_read(lp3972, LP3972_LDO_OUTPUT_ENABLE_REG(ldo));
  192. return !!(val & mask);
  193. }
  194. static int lp3972_ldo_enable(struct regulator_dev *dev)
  195. {
  196. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  197. int ldo = rdev_get_id(dev) - LP3972_LDO1;
  198. u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo);
  199. return lp3972_set_bits(lp3972, LP3972_LDO_OUTPUT_ENABLE_REG(ldo),
  200. mask, mask);
  201. }
  202. static int lp3972_ldo_disable(struct regulator_dev *dev)
  203. {
  204. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  205. int ldo = rdev_get_id(dev) - LP3972_LDO1;
  206. u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo);
  207. return lp3972_set_bits(lp3972, LP3972_LDO_OUTPUT_ENABLE_REG(ldo),
  208. mask, 0);
  209. }
  210. static int lp3972_ldo_get_voltage_sel(struct regulator_dev *dev)
  211. {
  212. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  213. int ldo = rdev_get_id(dev) - LP3972_LDO1;
  214. u16 mask = LP3972_LDO_VOL_MASK(ldo);
  215. u16 val, reg;
  216. reg = lp3972_reg_read(lp3972, LP3972_LDO_VOL_CONTR_REG(ldo));
  217. val = (reg >> LP3972_LDO_VOL_CONTR_SHIFT(ldo)) & mask;
  218. return val;
  219. }
  220. static int lp3972_ldo_set_voltage_sel(struct regulator_dev *dev,
  221. unsigned int selector)
  222. {
  223. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  224. int ldo = rdev_get_id(dev) - LP3972_LDO1;
  225. int shift, ret;
  226. shift = LP3972_LDO_VOL_CONTR_SHIFT(ldo);
  227. ret = lp3972_set_bits(lp3972, LP3972_LDO_VOL_CONTR_REG(ldo),
  228. LP3972_LDO_VOL_MASK(ldo) << shift, selector << shift);
  229. if (ret)
  230. return ret;
  231. /*
  232. * LDO1 and LDO5 support voltage control by either target voltage1
  233. * or target voltage2 register.
  234. * We use target voltage1 register for LDO1 and LDO5 in this driver.
  235. * We need to update voltage change control register(0x20) to enable
  236. * LDO1 and LDO5 to change to their programmed target values.
  237. */
  238. switch (ldo) {
  239. case LP3972_LDO1:
  240. case LP3972_LDO5:
  241. shift = LP3972_LDO_VOL_CHANGE_SHIFT(ldo);
  242. ret = lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
  243. LP3972_VOL_CHANGE_FLAG_MASK << shift,
  244. LP3972_VOL_CHANGE_FLAG_GO << shift);
  245. if (ret)
  246. return ret;
  247. ret = lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
  248. LP3972_VOL_CHANGE_FLAG_MASK << shift, 0);
  249. break;
  250. }
  251. return ret;
  252. }
  253. static const struct regulator_ops lp3972_ldo_ops = {
  254. .list_voltage = regulator_list_voltage_table,
  255. .map_voltage = regulator_map_voltage_ascend,
  256. .is_enabled = lp3972_ldo_is_enabled,
  257. .enable = lp3972_ldo_enable,
  258. .disable = lp3972_ldo_disable,
  259. .get_voltage_sel = lp3972_ldo_get_voltage_sel,
  260. .set_voltage_sel = lp3972_ldo_set_voltage_sel,
  261. };
  262. static int lp3972_dcdc_is_enabled(struct regulator_dev *dev)
  263. {
  264. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  265. int buck = rdev_get_id(dev) - LP3972_DCDC1;
  266. u16 mask = 1 << (buck * 2);
  267. u16 val;
  268. val = lp3972_reg_read(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck));
  269. return !!(val & mask);
  270. }
  271. static int lp3972_dcdc_enable(struct regulator_dev *dev)
  272. {
  273. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  274. int buck = rdev_get_id(dev) - LP3972_DCDC1;
  275. u16 mask = 1 << (buck * 2);
  276. u16 val;
  277. val = lp3972_set_bits(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck),
  278. mask, mask);
  279. return val;
  280. }
  281. static int lp3972_dcdc_disable(struct regulator_dev *dev)
  282. {
  283. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  284. int buck = rdev_get_id(dev) - LP3972_DCDC1;
  285. u16 mask = 1 << (buck * 2);
  286. u16 val;
  287. val = lp3972_set_bits(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck),
  288. mask, 0);
  289. return val;
  290. }
  291. static int lp3972_dcdc_get_voltage_sel(struct regulator_dev *dev)
  292. {
  293. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  294. int buck = rdev_get_id(dev) - LP3972_DCDC1;
  295. u16 reg;
  296. reg = lp3972_reg_read(lp3972, LP3972_BUCK_VOL1_REG(buck));
  297. reg &= LP3972_BUCK_VOL_MASK;
  298. return reg;
  299. }
  300. static int lp3972_dcdc_set_voltage_sel(struct regulator_dev *dev,
  301. unsigned int selector)
  302. {
  303. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  304. int buck = rdev_get_id(dev) - LP3972_DCDC1;
  305. int ret;
  306. ret = lp3972_set_bits(lp3972, LP3972_BUCK_VOL1_REG(buck),
  307. LP3972_BUCK_VOL_MASK, selector);
  308. if (ret)
  309. return ret;
  310. if (buck != 0)
  311. return ret;
  312. ret = lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
  313. LP3972_VOL_CHANGE_FLAG_MASK, LP3972_VOL_CHANGE_FLAG_GO);
  314. if (ret)
  315. return ret;
  316. return lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
  317. LP3972_VOL_CHANGE_FLAG_MASK, 0);
  318. }
  319. static const struct regulator_ops lp3972_dcdc_ops = {
  320. .list_voltage = regulator_list_voltage_table,
  321. .map_voltage = regulator_map_voltage_ascend,
  322. .is_enabled = lp3972_dcdc_is_enabled,
  323. .enable = lp3972_dcdc_enable,
  324. .disable = lp3972_dcdc_disable,
  325. .get_voltage_sel = lp3972_dcdc_get_voltage_sel,
  326. .set_voltage_sel = lp3972_dcdc_set_voltage_sel,
  327. };
  328. static const struct regulator_desc regulators[] = {
  329. {
  330. .name = "LDO1",
  331. .id = LP3972_LDO1,
  332. .ops = &lp3972_ldo_ops,
  333. .n_voltages = ARRAY_SIZE(ldo1_voltage_map),
  334. .volt_table = ldo1_voltage_map,
  335. .type = REGULATOR_VOLTAGE,
  336. .owner = THIS_MODULE,
  337. },
  338. {
  339. .name = "LDO2",
  340. .id = LP3972_LDO2,
  341. .ops = &lp3972_ldo_ops,
  342. .n_voltages = ARRAY_SIZE(ldo23_voltage_map),
  343. .volt_table = ldo23_voltage_map,
  344. .type = REGULATOR_VOLTAGE,
  345. .owner = THIS_MODULE,
  346. },
  347. {
  348. .name = "LDO3",
  349. .id = LP3972_LDO3,
  350. .ops = &lp3972_ldo_ops,
  351. .n_voltages = ARRAY_SIZE(ldo23_voltage_map),
  352. .volt_table = ldo23_voltage_map,
  353. .type = REGULATOR_VOLTAGE,
  354. .owner = THIS_MODULE,
  355. },
  356. {
  357. .name = "LDO4",
  358. .id = LP3972_LDO4,
  359. .ops = &lp3972_ldo_ops,
  360. .n_voltages = ARRAY_SIZE(ldo4_voltage_map),
  361. .volt_table = ldo4_voltage_map,
  362. .type = REGULATOR_VOLTAGE,
  363. .owner = THIS_MODULE,
  364. },
  365. {
  366. .name = "LDO5",
  367. .id = LP3972_LDO5,
  368. .ops = &lp3972_ldo_ops,
  369. .n_voltages = ARRAY_SIZE(ldo5_voltage_map),
  370. .volt_table = ldo5_voltage_map,
  371. .type = REGULATOR_VOLTAGE,
  372. .owner = THIS_MODULE,
  373. },
  374. {
  375. .name = "DCDC1",
  376. .id = LP3972_DCDC1,
  377. .ops = &lp3972_dcdc_ops,
  378. .n_voltages = ARRAY_SIZE(buck1_voltage_map),
  379. .volt_table = buck1_voltage_map,
  380. .type = REGULATOR_VOLTAGE,
  381. .owner = THIS_MODULE,
  382. },
  383. {
  384. .name = "DCDC2",
  385. .id = LP3972_DCDC2,
  386. .ops = &lp3972_dcdc_ops,
  387. .n_voltages = ARRAY_SIZE(buck23_voltage_map),
  388. .volt_table = buck23_voltage_map,
  389. .type = REGULATOR_VOLTAGE,
  390. .owner = THIS_MODULE,
  391. },
  392. {
  393. .name = "DCDC3",
  394. .id = LP3972_DCDC3,
  395. .ops = &lp3972_dcdc_ops,
  396. .n_voltages = ARRAY_SIZE(buck23_voltage_map),
  397. .volt_table = buck23_voltage_map,
  398. .type = REGULATOR_VOLTAGE,
  399. .owner = THIS_MODULE,
  400. },
  401. };
  402. static int setup_regulators(struct lp3972 *lp3972,
  403. struct lp3972_platform_data *pdata)
  404. {
  405. int i, err;
  406. /* Instantiate the regulators */
  407. for (i = 0; i < pdata->num_regulators; i++) {
  408. struct lp3972_regulator_subdev *reg = &pdata->regulators[i];
  409. struct regulator_config config = { };
  410. struct regulator_dev *rdev;
  411. config.dev = lp3972->dev;
  412. config.init_data = reg->initdata;
  413. config.driver_data = lp3972;
  414. rdev = devm_regulator_register(lp3972->dev,
  415. &regulators[reg->id], &config);
  416. if (IS_ERR(rdev)) {
  417. err = PTR_ERR(rdev);
  418. dev_err(lp3972->dev, "regulator init failed: %d\n",
  419. err);
  420. return err;
  421. }
  422. }
  423. return 0;
  424. }
  425. static int lp3972_i2c_probe(struct i2c_client *i2c,
  426. const struct i2c_device_id *id)
  427. {
  428. struct lp3972 *lp3972;
  429. struct lp3972_platform_data *pdata = dev_get_platdata(&i2c->dev);
  430. int ret;
  431. u16 val;
  432. if (!pdata) {
  433. dev_dbg(&i2c->dev, "No platform init data supplied\n");
  434. return -ENODEV;
  435. }
  436. lp3972 = devm_kzalloc(&i2c->dev, sizeof(struct lp3972), GFP_KERNEL);
  437. if (!lp3972)
  438. return -ENOMEM;
  439. lp3972->i2c = i2c;
  440. lp3972->dev = &i2c->dev;
  441. mutex_init(&lp3972->io_lock);
  442. /* Detect LP3972 */
  443. ret = lp3972_i2c_read(i2c, LP3972_SYS_CONTROL1_REG, 1, &val);
  444. if (ret == 0 &&
  445. (val & SYS_CONTROL1_INIT_MASK) != SYS_CONTROL1_INIT_VAL) {
  446. ret = -ENODEV;
  447. dev_err(&i2c->dev, "chip reported: val = 0x%x\n", val);
  448. }
  449. if (ret < 0) {
  450. dev_err(&i2c->dev, "failed to detect device. ret = %d\n", ret);
  451. return ret;
  452. }
  453. ret = setup_regulators(lp3972, pdata);
  454. if (ret < 0)
  455. return ret;
  456. i2c_set_clientdata(i2c, lp3972);
  457. return 0;
  458. }
  459. static const struct i2c_device_id lp3972_i2c_id[] = {
  460. { "lp3972", 0 },
  461. { }
  462. };
  463. MODULE_DEVICE_TABLE(i2c, lp3972_i2c_id);
  464. static struct i2c_driver lp3972_i2c_driver = {
  465. .driver = {
  466. .name = "lp3972",
  467. },
  468. .probe = lp3972_i2c_probe,
  469. .id_table = lp3972_i2c_id,
  470. };
  471. static int __init lp3972_module_init(void)
  472. {
  473. return i2c_add_driver(&lp3972_i2c_driver);
  474. }
  475. subsys_initcall(lp3972_module_init);
  476. static void __exit lp3972_module_exit(void)
  477. {
  478. i2c_del_driver(&lp3972_i2c_driver);
  479. }
  480. module_exit(lp3972_module_exit);
  481. MODULE_LICENSE("GPL");
  482. MODULE_AUTHOR("Axel Lin <axel.lin@gmail.com>");
  483. MODULE_DESCRIPTION("LP3972 PMIC driver");