da9210-regulator.h 8.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * da9210-regulator.h - Regulator definitions for DA9210
  4. * Copyright (C) 2013 Dialog Semiconductor Ltd.
  5. */
  6. #ifndef __DA9210_REGISTERS_H__
  7. #define __DA9210_REGISTERS_H__
  8. struct da9210_pdata {
  9. struct regulator_init_data da9210_constraints;
  10. };
  11. /* Page selection */
  12. #define DA9210_REG_PAGE_CON 0x00
  13. /* System Control and Event Registers */
  14. #define DA9210_REG_STATUS_A 0x50
  15. #define DA9210_REG_STATUS_B 0x51
  16. #define DA9210_REG_EVENT_A 0x52
  17. #define DA9210_REG_EVENT_B 0x53
  18. #define DA9210_REG_MASK_A 0x54
  19. #define DA9210_REG_MASK_B 0x55
  20. #define DA9210_REG_CONTROL_A 0x56
  21. /* GPIO Control Registers */
  22. #define DA9210_REG_GPIO_0_1 0x58
  23. #define DA9210_REG_GPIO_2_3 0x59
  24. #define DA9210_REG_GPIO_4_5 0x5A
  25. #define DA9210_REG_GPIO_6 0x5B
  26. /* Regulator Registers */
  27. #define DA9210_REG_BUCK_CONT 0x5D
  28. #define DA9210_REG_BUCK_ILIM 0xD0
  29. #define DA9210_REG_BUCK_CONF1 0xD1
  30. #define DA9210_REG_BUCK_CONF2 0xD2
  31. #define DA9210_REG_VBACK_AUTO 0xD4
  32. #define DA9210_REG_VBACK_BASE 0xD5
  33. #define DA9210_REG_VBACK_MAX_DVC_IF 0xD6
  34. #define DA9210_REG_VBACK_DVC 0xD7
  35. #define DA9210_REG_VBUCK_A 0xD8
  36. #define DA9210_REG_VBUCK_B 0xD9
  37. /* I2C Interface Settings */
  38. #define DA9210_REG_INTERFACE 0x105
  39. /* OTP */
  40. #define DA9210_REG_OPT_COUNT 0x140
  41. #define DA9210_REG_OPT_ADDR 0x141
  42. #define DA9210_REG_OPT_DATA 0x142
  43. /* Customer Trim and Configuration */
  44. #define DA9210_REG_CONFIG_A 0x143
  45. #define DA9210_REG_CONFIG_B 0x144
  46. #define DA9210_REG_CONFIG_C 0x145
  47. #define DA9210_REG_CONFIG_D 0x146
  48. #define DA9210_REG_CONFIG_E 0x147
  49. /*
  50. * Registers bits
  51. */
  52. /* DA9210_REG_PAGE_CON (addr=0x00) */
  53. #define DA9210_PEG_PAGE_SHIFT 0
  54. #define DA9210_REG_PAGE_MASK 0x0F
  55. /* On I2C registers 0x00 - 0xFF */
  56. #define DA9210_REG_PAGE0 0
  57. /* On I2C registers 0x100 - 0x1FF */
  58. #define DA9210_REG_PAGE2 2
  59. #define DA9210_PAGE_WRITE_MODE 0x00
  60. #define DA9210_REPEAT_WRITE_MODE 0x40
  61. #define DA9210_PAGE_REVERT 0x80
  62. /* DA9210_REG_STATUS_A (addr=0x50) */
  63. #define DA9210_GPI0 0x01
  64. #define DA9210_GPI1 0x02
  65. #define DA9210_GPI2 0x04
  66. #define DA9210_GPI3 0x08
  67. #define DA9210_GPI4 0x10
  68. #define DA9210_GPI5 0x20
  69. #define DA9210_GPI6 0x40
  70. /* DA9210_REG_EVENT_A (addr=0x52) */
  71. #define DA9210_E_GPI0 0x01
  72. #define DA9210_E_GPI1 0x02
  73. #define DA9210_E_GPI2 0x04
  74. #define DA9210_E_GPI3 0x08
  75. #define DA9210_E_GPI4 0x10
  76. #define DA9210_E_GPI5 0x20
  77. #define DA9210_E_GPI6 0x40
  78. /* DA9210_REG_EVENT_B (addr=0x53) */
  79. #define DA9210_E_OVCURR 0x01
  80. #define DA9210_E_NPWRGOOD 0x02
  81. #define DA9210_E_TEMP_WARN 0x04
  82. #define DA9210_E_TEMP_CRIT 0x08
  83. #define DA9210_E_VMAX 0x10
  84. /* DA9210_REG_MASK_A (addr=0x54) */
  85. #define DA9210_M_GPI0 0x01
  86. #define DA9210_M_GPI1 0x02
  87. #define DA9210_M_GPI2 0x04
  88. #define DA9210_M_GPI3 0x08
  89. #define DA9210_M_GPI4 0x10
  90. #define DA9210_M_GPI5 0x20
  91. #define DA9210_M_GPI6 0x40
  92. /* DA9210_REG_MASK_B (addr=0x55) */
  93. #define DA9210_M_OVCURR 0x01
  94. #define DA9210_M_NPWRGOOD 0x02
  95. #define DA9210_M_TEMP_WARN 0x04
  96. #define DA9210_M_TEMP_CRIT 0x08
  97. #define DA9210_M_VMAX 0x10
  98. /* DA9210_REG_CONTROL_A (addr=0x56) */
  99. #define DA9210_DEBOUNCING_SHIFT 0
  100. #define DA9210_DEBOUNCING_MASK 0x07
  101. #define DA9210_SLEW_RATE_SHIFT 3
  102. #define DA9210_SLEW_RATE_MASK 0x18
  103. #define DA9210_V_LOCK 0x20
  104. /* DA9210_REG_GPIO_0_1 (addr=0x58) */
  105. #define DA9210_GPIO0_PIN_SHIFT 0
  106. #define DA9210_GPIO0_PIN_MASK 0x03
  107. #define DA9210_GPIO0_PIN_GPI 0x00
  108. #define DA9210_GPIO0_PIN_GPO_OD 0x02
  109. #define DA9210_GPIO0_PIN_GPO 0x03
  110. #define DA9210_GPIO0_TYPE 0x04
  111. #define DA9210_GPIO0_TYPE_GPI 0x00
  112. #define DA9210_GPIO0_TYPE_GPO 0x04
  113. #define DA9210_GPIO0_MODE 0x08
  114. #define DA9210_GPIO1_PIN_SHIFT 4
  115. #define DA9210_GPIO1_PIN_MASK 0x30
  116. #define DA9210_GPIO1_PIN_GPI 0x00
  117. #define DA9210_GPIO1_PIN_VERROR 0x10
  118. #define DA9210_GPIO1_PIN_GPO_OD 0x20
  119. #define DA9210_GPIO1_PIN_GPO 0x30
  120. #define DA9210_GPIO1_TYPE_SHIFT 0x40
  121. #define DA9210_GPIO1_TYPE_GPI 0x00
  122. #define DA9210_GPIO1_TYPE_GPO 0x40
  123. #define DA9210_GPIO1_MODE 0x80
  124. /* DA9210_REG_GPIO_2_3 (addr=0x59) */
  125. #define DA9210_GPIO2_PIN_SHIFT 0
  126. #define DA9210_GPIO2_PIN_MASK 0x03
  127. #define DA9210_GPIO2_PIN_GPI 0x00
  128. #define DA9210_GPIO5_PIN_BUCK_CLK 0x10
  129. #define DA9210_GPIO2_PIN_GPO_OD 0x02
  130. #define DA9210_GPIO2_PIN_GPO 0x03
  131. #define DA9210_GPIO2_TYPE 0x04
  132. #define DA9210_GPIO2_TYPE_GPI 0x00
  133. #define DA9210_GPIO2_TYPE_GPO 0x04
  134. #define DA9210_GPIO2_MODE 0x08
  135. #define DA9210_GPIO3_PIN_SHIFT 4
  136. #define DA9210_GPIO3_PIN_MASK 0x30
  137. #define DA9210_GPIO3_PIN_GPI 0x00
  138. #define DA9210_GPIO3_PIN_IERROR 0x10
  139. #define DA9210_GPIO3_PIN_GPO_OD 0x20
  140. #define DA9210_GPIO3_PIN_GPO 0x30
  141. #define DA9210_GPIO3_TYPE_SHIFT 0x40
  142. #define DA9210_GPIO3_TYPE_GPI 0x00
  143. #define DA9210_GPIO3_TYPE_GPO 0x40
  144. #define DA9210_GPIO3_MODE 0x80
  145. /* DA9210_REG_GPIO_4_5 (addr=0x5A) */
  146. #define DA9210_GPIO4_PIN_SHIFT 0
  147. #define DA9210_GPIO4_PIN_MASK 0x03
  148. #define DA9210_GPIO4_PIN_GPI 0x00
  149. #define DA9210_GPIO4_PIN_GPO_OD 0x02
  150. #define DA9210_GPIO4_PIN_GPO 0x03
  151. #define DA9210_GPIO4_TYPE 0x04
  152. #define DA9210_GPIO4_TYPE_GPI 0x00
  153. #define DA9210_GPIO4_TYPE_GPO 0x04
  154. #define DA9210_GPIO4_MODE 0x08
  155. #define DA9210_GPIO5_PIN_SHIFT 4
  156. #define DA9210_GPIO5_PIN_MASK 0x30
  157. #define DA9210_GPIO5_PIN_GPI 0x00
  158. #define DA9210_GPIO5_PIN_INTERFACE 0x01
  159. #define DA9210_GPIO5_PIN_GPO_OD 0x20
  160. #define DA9210_GPIO5_PIN_GPO 0x30
  161. #define DA9210_GPIO5_TYPE_SHIFT 0x40
  162. #define DA9210_GPIO5_TYPE_GPI 0x00
  163. #define DA9210_GPIO5_TYPE_GPO 0x40
  164. #define DA9210_GPIO5_MODE 0x80
  165. /* DA9210_REG_GPIO_6 (addr=0x5B) */
  166. #define DA9210_GPIO6_PIN_SHIFT 0
  167. #define DA9210_GPIO6_PIN_MASK 0x03
  168. #define DA9210_GPIO6_PIN_GPI 0x00
  169. #define DA9210_GPIO6_PIN_INTERFACE 0x01
  170. #define DA9210_GPIO6_PIN_GPO_OD 0x02
  171. #define DA9210_GPIO6_PIN_GPO 0x03
  172. #define DA9210_GPIO6_TYPE 0x04
  173. #define DA9210_GPIO6_TYPE_GPI 0x00
  174. #define DA9210_GPIO6_TYPE_GPO 0x04
  175. #define DA9210_GPIO6_MODE 0x08
  176. /* DA9210_REG_BUCK_CONT (addr=0x5D) */
  177. #define DA9210_BUCK_EN 0x01
  178. #define DA9210_BUCK_GPI_SHIFT 1
  179. #define DA9210_BUCK_GPI_MASK 0x06
  180. #define DA9210_BUCK_GPI_OFF 0x00
  181. #define DA9210_BUCK_GPI_GPIO0 0x02
  182. #define DA9210_BUCK_GPI_GPIO3 0x04
  183. #define DA9210_BUCK_GPI_GPIO4 0x06
  184. #define DA9210_BUCK_PD_DIS 0x08
  185. #define DA9210_VBUCK_SEL 0x10
  186. #define DA9210_VBUCK_SEL_A 0x00
  187. #define DA9210_VBUCK_SEL_B 0x10
  188. #define DA9210_VBUCK_GPI_SHIFT 5
  189. #define DA9210_VBUCK_GPI_MASK 0x60
  190. #define DA9210_VBUCK_GPI_OFF 0x00
  191. #define DA9210_VBUCK_GPI_GPIO0 0x20
  192. #define DA9210_VBUCK_GPI_GPIO3 0x40
  193. #define DA9210_VBUCK_GPI_GPIO4 0x60
  194. #define DA9210_DVC_CTRL_EN 0x80
  195. /* DA9210_REG_BUCK_ILIM (addr=0xD0) */
  196. #define DA9210_BUCK_ILIM_SHIFT 0
  197. #define DA9210_BUCK_ILIM_MASK 0x0F
  198. #define DA9210_BUCK_IALARM 0x10
  199. /* DA9210_REG_BUCK_CONF1 (addr=0xD1) */
  200. #define DA9210_BUCK_MODE_SHIFT 0
  201. #define DA9210_BUCK_MODE_MASK 0x03
  202. #define DA9210_BUCK_MODE_MANUAL 0x00
  203. #define DA9210_BUCK_MODE_SLEEP 0x01
  204. #define DA9210_BUCK_MODE_SYNC 0x02
  205. #define DA9210_BUCK_MODE_AUTO 0x03
  206. #define DA9210_STARTUP_CTRL_SHIFT 2
  207. #define DA9210_STARTUP_CTRL_MASK 0x1C
  208. #define DA9210_PWR_DOWN_CTRL_SHIFT 5
  209. #define DA9210_PWR_DOWN_CTRL_MASK 0xE0
  210. /* DA9210_REG_BUCK_CONF2 (addr=0xD2) */
  211. #define DA9210_PHASE_SEL_SHIFT 0
  212. #define DA9210_PHASE_SEL_MASK 0x03
  213. #define DA9210_FREQ_SEL 0x40
  214. /* DA9210_REG_BUCK_AUTO (addr=0xD4) */
  215. #define DA9210_VBUCK_AUTO_SHIFT 0
  216. #define DA9210_VBUCK_AUTO_MASK 0x7F
  217. /* DA9210_REG_BUCK_BASE (addr=0xD5) */
  218. #define DA9210_VBUCK_BASE_SHIFT 0
  219. #define DA9210_VBUCK_BASE_MASK 0x7F
  220. /* DA9210_REG_VBUCK_MAX_DVC_IF (addr=0xD6) */
  221. #define DA9210_VBUCK_MAX_SHIFT 0
  222. #define DA9210_VBUCK_MAX_MASK 0x7F
  223. #define DA9210_DVC_STEP_SIZE 0x80
  224. #define DA9210_DVC_STEP_SIZE_10MV 0x00
  225. #define DA9210_DVC_STEP_SIZE_20MV 0x80
  226. /* DA9210_REG_VBUCK_DVC (addr=0xD7) */
  227. #define DA9210_VBUCK_DVC_SHIFT 0
  228. #define DA9210_VBUCK_DVC_MASK 0x7F
  229. /* DA9210_REG_VBUCK_A/B (addr=0xD8/0xD9) */
  230. #define DA9210_VBUCK_SHIFT 0
  231. #define DA9210_VBUCK_MASK 0x7F
  232. #define DA9210_VBUCK_BIAS 0
  233. #define DA9210_BUCK_SL 0x80
  234. /* DA9210_REG_INTERFACE (addr=0x105) */
  235. #define DA9210_IF_BASE_ADDR_SHIFT 4
  236. #define DA9210_IF_BASE_ADDR_MASK 0xF0
  237. /* DA9210_REG_CONFIG_E (addr=0x147) */
  238. #define DA9210_STAND_ALONE 0x01
  239. #endif /* __DA9210_REGISTERS_H__ */