axp20x-regulator.c 48 KB

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  1. /*
  2. * AXP20x regulators driver.
  3. *
  4. * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General
  7. * Public License. See the file "COPYING" in the main directory of this
  8. * archive for more details.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include <linux/init.h>
  19. #include <linux/mfd/axp20x.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/of_device.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/regmap.h>
  25. #include <linux/regulator/driver.h>
  26. #include <linux/regulator/machine.h>
  27. #include <linux/regulator/of_regulator.h>
  28. #define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0)
  29. #define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0)
  30. #define AXP20X_IO_ENABLED 0x03
  31. #define AXP20X_IO_DISABLED 0x07
  32. #define AXP20X_WORKMODE_DCDC2_MASK BIT_MASK(2)
  33. #define AXP20X_WORKMODE_DCDC3_MASK BIT_MASK(1)
  34. #define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0)
  35. #define AXP20X_VBUS_IPSOUT_MGMT_MASK BIT_MASK(2)
  36. #define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0)
  37. #define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0)
  38. #define AXP20X_LDO2_V_OUT_MASK GENMASK(7, 4)
  39. #define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0)
  40. #define AXP20X_LDO4_V_OUT_MASK GENMASK(3, 0)
  41. #define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4)
  42. #define AXP20X_PWR_OUT_EXTEN_MASK BIT_MASK(0)
  43. #define AXP20X_PWR_OUT_DCDC3_MASK BIT_MASK(1)
  44. #define AXP20X_PWR_OUT_LDO2_MASK BIT_MASK(2)
  45. #define AXP20X_PWR_OUT_LDO4_MASK BIT_MASK(3)
  46. #define AXP20X_PWR_OUT_DCDC2_MASK BIT_MASK(4)
  47. #define AXP20X_PWR_OUT_LDO3_MASK BIT_MASK(6)
  48. #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK BIT_MASK(0)
  49. #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
  50. ((x) << 0)
  51. #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK BIT_MASK(1)
  52. #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
  53. ((x) << 1)
  54. #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK BIT_MASK(2)
  55. #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2)
  56. #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK BIT_MASK(3)
  57. #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3)
  58. #define AXP20X_LDO4_V_OUT_1250mV_START 0x0
  59. #define AXP20X_LDO4_V_OUT_1250mV_STEPS 0
  60. #define AXP20X_LDO4_V_OUT_1250mV_END \
  61. (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
  62. #define AXP20X_LDO4_V_OUT_1300mV_START 0x1
  63. #define AXP20X_LDO4_V_OUT_1300mV_STEPS 7
  64. #define AXP20X_LDO4_V_OUT_1300mV_END \
  65. (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
  66. #define AXP20X_LDO4_V_OUT_2500mV_START 0x9
  67. #define AXP20X_LDO4_V_OUT_2500mV_STEPS 0
  68. #define AXP20X_LDO4_V_OUT_2500mV_END \
  69. (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
  70. #define AXP20X_LDO4_V_OUT_2700mV_START 0xa
  71. #define AXP20X_LDO4_V_OUT_2700mV_STEPS 1
  72. #define AXP20X_LDO4_V_OUT_2700mV_END \
  73. (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
  74. #define AXP20X_LDO4_V_OUT_3000mV_START 0xc
  75. #define AXP20X_LDO4_V_OUT_3000mV_STEPS 3
  76. #define AXP20X_LDO4_V_OUT_3000mV_END \
  77. (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
  78. #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES 16
  79. #define AXP22X_IO_ENABLED 0x03
  80. #define AXP22X_IO_DISABLED 0x04
  81. #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT_MASK(x)
  82. #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4)
  83. #define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0)
  84. #define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0)
  85. #define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0)
  86. #define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0)
  87. #define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0)
  88. #define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0)
  89. #define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0)
  90. #define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0)
  91. #define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0)
  92. #define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0)
  93. #define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0)
  94. #define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0)
  95. #define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0)
  96. #define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0)
  97. #define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0)
  98. #define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0)
  99. #define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0)
  100. #define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0)
  101. #define AXP22X_PWR_OUT_DC5LDO_MASK BIT_MASK(0)
  102. #define AXP22X_PWR_OUT_DCDC1_MASK BIT_MASK(1)
  103. #define AXP22X_PWR_OUT_DCDC2_MASK BIT_MASK(2)
  104. #define AXP22X_PWR_OUT_DCDC3_MASK BIT_MASK(3)
  105. #define AXP22X_PWR_OUT_DCDC4_MASK BIT_MASK(4)
  106. #define AXP22X_PWR_OUT_DCDC5_MASK BIT_MASK(5)
  107. #define AXP22X_PWR_OUT_ALDO1_MASK BIT_MASK(6)
  108. #define AXP22X_PWR_OUT_ALDO2_MASK BIT_MASK(7)
  109. #define AXP22X_PWR_OUT_SW_MASK BIT_MASK(6)
  110. #define AXP22X_PWR_OUT_DC1SW_MASK BIT_MASK(7)
  111. #define AXP22X_PWR_OUT_ELDO1_MASK BIT_MASK(0)
  112. #define AXP22X_PWR_OUT_ELDO2_MASK BIT_MASK(1)
  113. #define AXP22X_PWR_OUT_ELDO3_MASK BIT_MASK(2)
  114. #define AXP22X_PWR_OUT_DLDO1_MASK BIT_MASK(3)
  115. #define AXP22X_PWR_OUT_DLDO2_MASK BIT_MASK(4)
  116. #define AXP22X_PWR_OUT_DLDO3_MASK BIT_MASK(5)
  117. #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6)
  118. #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7)
  119. #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0)
  120. #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1)
  121. #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2)
  122. #define AXP803_PWR_OUT_DCDC4_MASK BIT_MASK(3)
  123. #define AXP803_PWR_OUT_DCDC5_MASK BIT_MASK(4)
  124. #define AXP803_PWR_OUT_DCDC6_MASK BIT_MASK(5)
  125. #define AXP803_PWR_OUT_FLDO1_MASK BIT_MASK(2)
  126. #define AXP803_PWR_OUT_FLDO2_MASK BIT_MASK(3)
  127. #define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0)
  128. #define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0)
  129. #define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0)
  130. #define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0)
  131. #define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0)
  132. #define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0)
  133. #define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0)
  134. #define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0)
  135. #define AXP803_DCDC23_POLYPHASE_DUAL BIT(6)
  136. #define AXP803_DCDC56_POLYPHASE_DUAL BIT(5)
  137. #define AXP803_DCDC234_500mV_START 0x00
  138. #define AXP803_DCDC234_500mV_STEPS 70
  139. #define AXP803_DCDC234_500mV_END \
  140. (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
  141. #define AXP803_DCDC234_1220mV_START 0x47
  142. #define AXP803_DCDC234_1220mV_STEPS 4
  143. #define AXP803_DCDC234_1220mV_END \
  144. (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
  145. #define AXP803_DCDC234_NUM_VOLTAGES 76
  146. #define AXP803_DCDC5_800mV_START 0x00
  147. #define AXP803_DCDC5_800mV_STEPS 32
  148. #define AXP803_DCDC5_800mV_END \
  149. (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
  150. #define AXP803_DCDC5_1140mV_START 0x21
  151. #define AXP803_DCDC5_1140mV_STEPS 35
  152. #define AXP803_DCDC5_1140mV_END \
  153. (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
  154. #define AXP803_DCDC5_NUM_VOLTAGES 69
  155. #define AXP803_DCDC6_600mV_START 0x00
  156. #define AXP803_DCDC6_600mV_STEPS 50
  157. #define AXP803_DCDC6_600mV_END \
  158. (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
  159. #define AXP803_DCDC6_1120mV_START 0x33
  160. #define AXP803_DCDC6_1120mV_STEPS 20
  161. #define AXP803_DCDC6_1120mV_END \
  162. (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
  163. #define AXP803_DCDC6_NUM_VOLTAGES 72
  164. #define AXP803_DLDO2_700mV_START 0x00
  165. #define AXP803_DLDO2_700mV_STEPS 26
  166. #define AXP803_DLDO2_700mV_END \
  167. (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
  168. #define AXP803_DLDO2_3400mV_START 0x1b
  169. #define AXP803_DLDO2_3400mV_STEPS 4
  170. #define AXP803_DLDO2_3400mV_END \
  171. (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
  172. #define AXP803_DLDO2_NUM_VOLTAGES 32
  173. #define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0)
  174. #define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0)
  175. #define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0)
  176. #define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0)
  177. #define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0)
  178. #define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0)
  179. #define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0)
  180. #define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0)
  181. #define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0)
  182. #define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0)
  183. #define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0)
  184. #define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0)
  185. #define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0)
  186. #define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0)
  187. #define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0)
  188. #define AXP806_PWR_OUT_DCDCA_MASK BIT_MASK(0)
  189. #define AXP806_PWR_OUT_DCDCB_MASK BIT_MASK(1)
  190. #define AXP806_PWR_OUT_DCDCC_MASK BIT_MASK(2)
  191. #define AXP806_PWR_OUT_DCDCD_MASK BIT_MASK(3)
  192. #define AXP806_PWR_OUT_DCDCE_MASK BIT_MASK(4)
  193. #define AXP806_PWR_OUT_ALDO1_MASK BIT_MASK(5)
  194. #define AXP806_PWR_OUT_ALDO2_MASK BIT_MASK(6)
  195. #define AXP806_PWR_OUT_ALDO3_MASK BIT_MASK(7)
  196. #define AXP806_PWR_OUT_BLDO1_MASK BIT_MASK(0)
  197. #define AXP806_PWR_OUT_BLDO2_MASK BIT_MASK(1)
  198. #define AXP806_PWR_OUT_BLDO3_MASK BIT_MASK(2)
  199. #define AXP806_PWR_OUT_BLDO4_MASK BIT_MASK(3)
  200. #define AXP806_PWR_OUT_CLDO1_MASK BIT_MASK(4)
  201. #define AXP806_PWR_OUT_CLDO2_MASK BIT_MASK(5)
  202. #define AXP806_PWR_OUT_CLDO3_MASK BIT_MASK(6)
  203. #define AXP806_PWR_OUT_SW_MASK BIT_MASK(7)
  204. #define AXP806_DCDCAB_POLYPHASE_DUAL 0x40
  205. #define AXP806_DCDCABC_POLYPHASE_TRI 0x80
  206. #define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6)
  207. #define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5)
  208. #define AXP806_DCDCA_600mV_START 0x00
  209. #define AXP806_DCDCA_600mV_STEPS 50
  210. #define AXP806_DCDCA_600mV_END \
  211. (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
  212. #define AXP806_DCDCA_1120mV_START 0x33
  213. #define AXP806_DCDCA_1120mV_STEPS 20
  214. #define AXP806_DCDCA_1120mV_END \
  215. (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
  216. #define AXP806_DCDCA_NUM_VOLTAGES 72
  217. #define AXP806_DCDCD_600mV_START 0x00
  218. #define AXP806_DCDCD_600mV_STEPS 45
  219. #define AXP806_DCDCD_600mV_END \
  220. (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
  221. #define AXP806_DCDCD_1600mV_START 0x2e
  222. #define AXP806_DCDCD_1600mV_STEPS 17
  223. #define AXP806_DCDCD_1600mV_END \
  224. (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
  225. #define AXP806_DCDCD_NUM_VOLTAGES 64
  226. #define AXP809_DCDC4_600mV_START 0x00
  227. #define AXP809_DCDC4_600mV_STEPS 47
  228. #define AXP809_DCDC4_600mV_END \
  229. (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
  230. #define AXP809_DCDC4_1800mV_START 0x30
  231. #define AXP809_DCDC4_1800mV_STEPS 8
  232. #define AXP809_DCDC4_1800mV_END \
  233. (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
  234. #define AXP809_DCDC4_NUM_VOLTAGES 57
  235. #define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0)
  236. #define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6)
  237. #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
  238. _vmask, _ereg, _emask, _enable_val, _disable_val) \
  239. [_family##_##_id] = { \
  240. .name = (_match), \
  241. .supply_name = (_supply), \
  242. .of_match = of_match_ptr(_match), \
  243. .regulators_node = of_match_ptr("regulators"), \
  244. .type = REGULATOR_VOLTAGE, \
  245. .id = _family##_##_id, \
  246. .n_voltages = (((_max) - (_min)) / (_step) + 1), \
  247. .owner = THIS_MODULE, \
  248. .min_uV = (_min) * 1000, \
  249. .uV_step = (_step) * 1000, \
  250. .vsel_reg = (_vreg), \
  251. .vsel_mask = (_vmask), \
  252. .enable_reg = (_ereg), \
  253. .enable_mask = (_emask), \
  254. .enable_val = (_enable_val), \
  255. .disable_val = (_disable_val), \
  256. .ops = &axp20x_ops, \
  257. }
  258. #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
  259. _vmask, _ereg, _emask) \
  260. [_family##_##_id] = { \
  261. .name = (_match), \
  262. .supply_name = (_supply), \
  263. .of_match = of_match_ptr(_match), \
  264. .regulators_node = of_match_ptr("regulators"), \
  265. .type = REGULATOR_VOLTAGE, \
  266. .id = _family##_##_id, \
  267. .n_voltages = (((_max) - (_min)) / (_step) + 1), \
  268. .owner = THIS_MODULE, \
  269. .min_uV = (_min) * 1000, \
  270. .uV_step = (_step) * 1000, \
  271. .vsel_reg = (_vreg), \
  272. .vsel_mask = (_vmask), \
  273. .enable_reg = (_ereg), \
  274. .enable_mask = (_emask), \
  275. .ops = &axp20x_ops, \
  276. }
  277. #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
  278. [_family##_##_id] = { \
  279. .name = (_match), \
  280. .supply_name = (_supply), \
  281. .of_match = of_match_ptr(_match), \
  282. .regulators_node = of_match_ptr("regulators"), \
  283. .type = REGULATOR_VOLTAGE, \
  284. .id = _family##_##_id, \
  285. .owner = THIS_MODULE, \
  286. .enable_reg = (_ereg), \
  287. .enable_mask = (_emask), \
  288. .ops = &axp20x_ops_sw, \
  289. }
  290. #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \
  291. [_family##_##_id] = { \
  292. .name = (_match), \
  293. .supply_name = (_supply), \
  294. .of_match = of_match_ptr(_match), \
  295. .regulators_node = of_match_ptr("regulators"), \
  296. .type = REGULATOR_VOLTAGE, \
  297. .id = _family##_##_id, \
  298. .n_voltages = 1, \
  299. .owner = THIS_MODULE, \
  300. .min_uV = (_volt) * 1000, \
  301. .ops = &axp20x_ops_fixed \
  302. }
  303. #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
  304. _vreg, _vmask, _ereg, _emask) \
  305. [_family##_##_id] = { \
  306. .name = (_match), \
  307. .supply_name = (_supply), \
  308. .of_match = of_match_ptr(_match), \
  309. .regulators_node = of_match_ptr("regulators"), \
  310. .type = REGULATOR_VOLTAGE, \
  311. .id = _family##_##_id, \
  312. .n_voltages = (_n_voltages), \
  313. .owner = THIS_MODULE, \
  314. .vsel_reg = (_vreg), \
  315. .vsel_mask = (_vmask), \
  316. .enable_reg = (_ereg), \
  317. .enable_mask = (_emask), \
  318. .linear_ranges = (_ranges), \
  319. .n_linear_ranges = ARRAY_SIZE(_ranges), \
  320. .ops = &axp20x_ops_range, \
  321. }
  322. static const int axp209_dcdc2_ldo3_slew_rates[] = {
  323. 1600,
  324. 800,
  325. };
  326. static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
  327. {
  328. struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
  329. int id = rdev_get_id(rdev);
  330. u8 reg, mask, enable, cfg = 0xff;
  331. const int *slew_rates;
  332. int rate_count = 0;
  333. switch (axp20x->variant) {
  334. case AXP209_ID:
  335. if (id == AXP20X_DCDC2) {
  336. slew_rates = axp209_dcdc2_ldo3_slew_rates;
  337. rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
  338. reg = AXP20X_DCDC2_LDO3_V_RAMP;
  339. mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
  340. AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
  341. enable = (ramp > 0) ?
  342. AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0;
  343. break;
  344. }
  345. if (id == AXP20X_LDO3) {
  346. slew_rates = axp209_dcdc2_ldo3_slew_rates;
  347. rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
  348. reg = AXP20X_DCDC2_LDO3_V_RAMP;
  349. mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
  350. AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
  351. enable = (ramp > 0) ?
  352. AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0;
  353. break;
  354. }
  355. if (rate_count > 0)
  356. break;
  357. fallthrough;
  358. default:
  359. /* Not supported for this regulator */
  360. return -ENOTSUPP;
  361. }
  362. if (ramp == 0) {
  363. cfg = enable;
  364. } else {
  365. int i;
  366. for (i = 0; i < rate_count; i++) {
  367. if (ramp > slew_rates[i])
  368. break;
  369. if (id == AXP20X_DCDC2)
  370. cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i);
  371. else
  372. cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
  373. }
  374. if (cfg == 0xff) {
  375. dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
  376. return -EINVAL;
  377. }
  378. cfg |= enable;
  379. }
  380. return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
  381. }
  382. static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
  383. {
  384. struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
  385. int id = rdev_get_id(rdev);
  386. switch (axp20x->variant) {
  387. case AXP209_ID:
  388. if ((id == AXP20X_LDO3) &&
  389. rdev->constraints && rdev->constraints->soft_start) {
  390. int v_out;
  391. int ret;
  392. /*
  393. * On some boards, the LDO3 can be overloaded when
  394. * turning on, causing the entire PMIC to shutdown
  395. * without warning. Turning it on at the minimal voltage
  396. * and then setting the voltage to the requested value
  397. * works reliably.
  398. */
  399. if (regulator_is_enabled_regmap(rdev))
  400. break;
  401. v_out = regulator_get_voltage_sel_regmap(rdev);
  402. if (v_out < 0)
  403. return v_out;
  404. if (v_out == 0)
  405. break;
  406. ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
  407. /*
  408. * A small pause is needed between
  409. * setting the voltage and enabling the LDO to give the
  410. * internal state machine time to process the request.
  411. */
  412. usleep_range(1000, 5000);
  413. ret |= regulator_enable_regmap(rdev);
  414. ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
  415. return ret;
  416. }
  417. break;
  418. default:
  419. /* No quirks */
  420. break;
  421. }
  422. return regulator_enable_regmap(rdev);
  423. };
  424. static const struct regulator_ops axp20x_ops_fixed = {
  425. .list_voltage = regulator_list_voltage_linear,
  426. };
  427. static const struct regulator_ops axp20x_ops_range = {
  428. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  429. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  430. .list_voltage = regulator_list_voltage_linear_range,
  431. .enable = regulator_enable_regmap,
  432. .disable = regulator_disable_regmap,
  433. .is_enabled = regulator_is_enabled_regmap,
  434. };
  435. static const struct regulator_ops axp20x_ops = {
  436. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  437. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  438. .list_voltage = regulator_list_voltage_linear,
  439. .enable = axp20x_regulator_enable_regmap,
  440. .disable = regulator_disable_regmap,
  441. .is_enabled = regulator_is_enabled_regmap,
  442. .set_ramp_delay = axp20x_set_ramp_delay,
  443. };
  444. static const struct regulator_ops axp20x_ops_sw = {
  445. .enable = regulator_enable_regmap,
  446. .disable = regulator_disable_regmap,
  447. .is_enabled = regulator_is_enabled_regmap,
  448. };
  449. static const struct linear_range axp20x_ldo4_ranges[] = {
  450. REGULATOR_LINEAR_RANGE(1250000,
  451. AXP20X_LDO4_V_OUT_1250mV_START,
  452. AXP20X_LDO4_V_OUT_1250mV_END,
  453. 0),
  454. REGULATOR_LINEAR_RANGE(1300000,
  455. AXP20X_LDO4_V_OUT_1300mV_START,
  456. AXP20X_LDO4_V_OUT_1300mV_END,
  457. 100000),
  458. REGULATOR_LINEAR_RANGE(2500000,
  459. AXP20X_LDO4_V_OUT_2500mV_START,
  460. AXP20X_LDO4_V_OUT_2500mV_END,
  461. 0),
  462. REGULATOR_LINEAR_RANGE(2700000,
  463. AXP20X_LDO4_V_OUT_2700mV_START,
  464. AXP20X_LDO4_V_OUT_2700mV_END,
  465. 100000),
  466. REGULATOR_LINEAR_RANGE(3000000,
  467. AXP20X_LDO4_V_OUT_3000mV_START,
  468. AXP20X_LDO4_V_OUT_3000mV_END,
  469. 100000),
  470. };
  471. static const struct regulator_desc axp20x_regulators[] = {
  472. AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
  473. AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
  474. AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
  475. AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
  476. AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
  477. AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
  478. AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
  479. AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
  480. AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK,
  481. AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
  482. AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
  483. AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
  484. AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
  485. AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
  486. axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
  487. AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK,
  488. AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
  489. AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
  490. AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
  491. AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
  492. AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
  493. };
  494. static const struct regulator_desc axp22x_regulators[] = {
  495. AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
  496. AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
  497. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
  498. AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
  499. AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
  500. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
  501. AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
  502. AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
  503. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
  504. AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
  505. AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
  506. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
  507. AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
  508. AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
  509. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
  510. /* secondary switchable output of DCDC1 */
  511. AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
  512. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
  513. /* LDO regulator internally chained to DCDC5 */
  514. AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
  515. AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
  516. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
  517. AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
  518. AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
  519. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
  520. AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
  521. AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
  522. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
  523. AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
  524. AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
  525. AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
  526. AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
  527. AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
  528. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
  529. AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
  530. AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
  531. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
  532. AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
  533. AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
  534. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
  535. AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
  536. AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
  537. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
  538. AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
  539. AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
  540. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
  541. AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
  542. AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
  543. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
  544. AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
  545. AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
  546. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
  547. /* Note the datasheet only guarantees reliable operation up to
  548. * 3.3V, this needs to be enforced via dts provided constraints */
  549. AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
  550. AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
  551. AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
  552. AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
  553. /* Note the datasheet only guarantees reliable operation up to
  554. * 3.3V, this needs to be enforced via dts provided constraints */
  555. AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
  556. AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
  557. AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
  558. AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
  559. AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
  560. };
  561. static const struct regulator_desc axp22x_drivevbus_regulator = {
  562. .name = "drivevbus",
  563. .supply_name = "drivevbus",
  564. .of_match = of_match_ptr("drivevbus"),
  565. .regulators_node = of_match_ptr("regulators"),
  566. .type = REGULATOR_VOLTAGE,
  567. .owner = THIS_MODULE,
  568. .enable_reg = AXP20X_VBUS_IPSOUT_MGMT,
  569. .enable_mask = AXP20X_VBUS_IPSOUT_MGMT_MASK,
  570. .ops = &axp20x_ops_sw,
  571. };
  572. /* DCDC ranges shared with AXP813 */
  573. static const struct linear_range axp803_dcdc234_ranges[] = {
  574. REGULATOR_LINEAR_RANGE(500000,
  575. AXP803_DCDC234_500mV_START,
  576. AXP803_DCDC234_500mV_END,
  577. 10000),
  578. REGULATOR_LINEAR_RANGE(1220000,
  579. AXP803_DCDC234_1220mV_START,
  580. AXP803_DCDC234_1220mV_END,
  581. 20000),
  582. };
  583. static const struct linear_range axp803_dcdc5_ranges[] = {
  584. REGULATOR_LINEAR_RANGE(800000,
  585. AXP803_DCDC5_800mV_START,
  586. AXP803_DCDC5_800mV_END,
  587. 10000),
  588. REGULATOR_LINEAR_RANGE(1140000,
  589. AXP803_DCDC5_1140mV_START,
  590. AXP803_DCDC5_1140mV_END,
  591. 20000),
  592. };
  593. static const struct linear_range axp803_dcdc6_ranges[] = {
  594. REGULATOR_LINEAR_RANGE(600000,
  595. AXP803_DCDC6_600mV_START,
  596. AXP803_DCDC6_600mV_END,
  597. 10000),
  598. REGULATOR_LINEAR_RANGE(1120000,
  599. AXP803_DCDC6_1120mV_START,
  600. AXP803_DCDC6_1120mV_END,
  601. 20000),
  602. };
  603. /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */
  604. static const struct linear_range axp803_dldo2_ranges[] = {
  605. REGULATOR_LINEAR_RANGE(700000,
  606. AXP803_DLDO2_700mV_START,
  607. AXP803_DLDO2_700mV_END,
  608. 100000),
  609. REGULATOR_LINEAR_RANGE(3400000,
  610. AXP803_DLDO2_3400mV_START,
  611. AXP803_DLDO2_3400mV_END,
  612. 200000),
  613. };
  614. static const struct regulator_desc axp803_regulators[] = {
  615. AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
  616. AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
  617. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
  618. AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
  619. axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
  620. AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
  621. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
  622. AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
  623. axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
  624. AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
  625. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
  626. AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
  627. axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
  628. AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
  629. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
  630. AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
  631. axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
  632. AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
  633. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
  634. AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
  635. axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
  636. AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
  637. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
  638. /* secondary switchable output of DCDC1 */
  639. AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
  640. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
  641. AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
  642. AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
  643. AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
  644. AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
  645. AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
  646. AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
  647. AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
  648. AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
  649. AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
  650. AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
  651. AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
  652. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
  653. AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
  654. axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
  655. AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
  656. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
  657. AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
  658. AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
  659. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
  660. AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
  661. AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
  662. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
  663. AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
  664. AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
  665. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
  666. AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
  667. AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
  668. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
  669. AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
  670. AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
  671. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
  672. AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
  673. AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
  674. AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
  675. AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
  676. AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
  677. AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
  678. AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
  679. AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
  680. AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
  681. AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
  682. AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
  683. AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
  684. AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
  685. AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
  686. AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
  687. };
  688. static const struct linear_range axp806_dcdca_ranges[] = {
  689. REGULATOR_LINEAR_RANGE(600000,
  690. AXP806_DCDCA_600mV_START,
  691. AXP806_DCDCA_600mV_END,
  692. 10000),
  693. REGULATOR_LINEAR_RANGE(1120000,
  694. AXP806_DCDCA_1120mV_START,
  695. AXP806_DCDCA_1120mV_END,
  696. 20000),
  697. };
  698. static const struct linear_range axp806_dcdcd_ranges[] = {
  699. REGULATOR_LINEAR_RANGE(600000,
  700. AXP806_DCDCD_600mV_START,
  701. AXP806_DCDCD_600mV_END,
  702. 20000),
  703. REGULATOR_LINEAR_RANGE(1600000,
  704. AXP806_DCDCD_1600mV_START,
  705. AXP806_DCDCD_1600mV_END,
  706. 100000),
  707. };
  708. static const struct regulator_desc axp806_regulators[] = {
  709. AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
  710. axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
  711. AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
  712. AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
  713. AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
  714. AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
  715. AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
  716. AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
  717. axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
  718. AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
  719. AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
  720. AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
  721. axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
  722. AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
  723. AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
  724. AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
  725. AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
  726. AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
  727. AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
  728. AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
  729. AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
  730. AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
  731. AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
  732. AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
  733. AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
  734. AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
  735. AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
  736. AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
  737. AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
  738. AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
  739. AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
  740. AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
  741. AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
  742. AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
  743. AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
  744. AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
  745. AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
  746. AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
  747. AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
  748. AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
  749. AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
  750. AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
  751. AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
  752. axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
  753. AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
  754. AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
  755. AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
  756. AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
  757. AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
  758. AXP_DESC_SW(AXP806, SW, "sw", "swin",
  759. AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
  760. };
  761. static const struct linear_range axp809_dcdc4_ranges[] = {
  762. REGULATOR_LINEAR_RANGE(600000,
  763. AXP809_DCDC4_600mV_START,
  764. AXP809_DCDC4_600mV_END,
  765. 20000),
  766. REGULATOR_LINEAR_RANGE(1800000,
  767. AXP809_DCDC4_1800mV_START,
  768. AXP809_DCDC4_1800mV_END,
  769. 100000),
  770. };
  771. static const struct regulator_desc axp809_regulators[] = {
  772. AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
  773. AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
  774. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
  775. AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
  776. AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
  777. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
  778. AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
  779. AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
  780. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
  781. AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
  782. axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
  783. AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
  784. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
  785. AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
  786. AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
  787. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
  788. /* secondary switchable output of DCDC1 */
  789. AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
  790. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
  791. /* LDO regulator internally chained to DCDC5 */
  792. AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
  793. AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
  794. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
  795. AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
  796. AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
  797. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
  798. AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
  799. AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
  800. AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
  801. AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
  802. AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
  803. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
  804. AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
  805. axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
  806. AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
  807. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
  808. AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
  809. AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
  810. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
  811. AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
  812. AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
  813. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
  814. AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
  815. AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
  816. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
  817. AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
  818. AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
  819. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
  820. /*
  821. * Note the datasheet only guarantees reliable operation up to
  822. * 3.3V, this needs to be enforced via dts provided constraints
  823. */
  824. AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
  825. AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
  826. AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
  827. AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
  828. /*
  829. * Note the datasheet only guarantees reliable operation up to
  830. * 3.3V, this needs to be enforced via dts provided constraints
  831. */
  832. AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
  833. AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
  834. AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
  835. AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
  836. AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
  837. AXP_DESC_SW(AXP809, SW, "sw", "swin",
  838. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
  839. };
  840. static const struct regulator_desc axp813_regulators[] = {
  841. AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
  842. AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
  843. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
  844. AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
  845. axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
  846. AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
  847. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
  848. AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
  849. axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
  850. AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
  851. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
  852. AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
  853. axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
  854. AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
  855. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
  856. AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
  857. axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
  858. AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
  859. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
  860. AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
  861. axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
  862. AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
  863. AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
  864. AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
  865. axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
  866. AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
  867. AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
  868. AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
  869. AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
  870. AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
  871. AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
  872. AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
  873. AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
  874. AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
  875. AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
  876. AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
  877. AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
  878. AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
  879. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
  880. AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
  881. axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
  882. AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
  883. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
  884. AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
  885. AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
  886. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
  887. AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
  888. AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
  889. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
  890. AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
  891. AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
  892. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
  893. AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
  894. AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
  895. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
  896. AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
  897. AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
  898. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
  899. /* to do / check ... */
  900. AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
  901. AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
  902. AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
  903. AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
  904. AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
  905. AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
  906. /*
  907. * TODO: FLDO3 = {DCDC5, FLDOIN} / 2
  908. *
  909. * This means FLDO3 effectively switches supplies at runtime,
  910. * something the regulator subsystem does not support.
  911. */
  912. AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
  913. AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
  914. AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
  915. AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
  916. AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
  917. AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
  918. AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
  919. AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
  920. AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
  921. AXP_DESC_SW(AXP813, SW, "sw", "swin",
  922. AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
  923. };
  924. static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
  925. {
  926. struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
  927. unsigned int reg = AXP20X_DCDC_FREQ;
  928. u32 min, max, def, step;
  929. switch (axp20x->variant) {
  930. case AXP202_ID:
  931. case AXP209_ID:
  932. min = 750;
  933. max = 1875;
  934. def = 1500;
  935. step = 75;
  936. break;
  937. case AXP803_ID:
  938. case AXP813_ID:
  939. /*
  940. * AXP803/AXP813 DCDC work frequency setting has the same
  941. * range and step as AXP22X, but at a different register.
  942. * (See include/linux/mfd/axp20x.h)
  943. */
  944. reg = AXP803_DCDC_FREQ_CTRL;
  945. fallthrough; /* to the check below */
  946. case AXP806_ID:
  947. /*
  948. * AXP806 also have DCDC work frequency setting register at a
  949. * different position.
  950. */
  951. if (axp20x->variant == AXP806_ID)
  952. reg = AXP806_DCDC_FREQ_CTRL;
  953. fallthrough;
  954. case AXP221_ID:
  955. case AXP223_ID:
  956. case AXP809_ID:
  957. min = 1800;
  958. max = 4050;
  959. def = 3000;
  960. step = 150;
  961. break;
  962. default:
  963. dev_err(&pdev->dev,
  964. "Setting DCDC frequency for unsupported AXP variant\n");
  965. return -EINVAL;
  966. }
  967. if (dcdcfreq == 0)
  968. dcdcfreq = def;
  969. if (dcdcfreq < min) {
  970. dcdcfreq = min;
  971. dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
  972. min);
  973. }
  974. if (dcdcfreq > max) {
  975. dcdcfreq = max;
  976. dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
  977. max);
  978. }
  979. dcdcfreq = (dcdcfreq - min) / step;
  980. return regmap_update_bits(axp20x->regmap, reg,
  981. AXP20X_FREQ_DCDC_MASK, dcdcfreq);
  982. }
  983. static int axp20x_regulator_parse_dt(struct platform_device *pdev)
  984. {
  985. struct device_node *np, *regulators;
  986. int ret = 0;
  987. u32 dcdcfreq = 0;
  988. np = of_node_get(pdev->dev.parent->of_node);
  989. if (!np)
  990. return 0;
  991. regulators = of_get_child_by_name(np, "regulators");
  992. if (!regulators) {
  993. dev_warn(&pdev->dev, "regulators node not found\n");
  994. } else {
  995. of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
  996. ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
  997. if (ret < 0) {
  998. dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
  999. }
  1000. of_node_put(regulators);
  1001. }
  1002. of_node_put(np);
  1003. return ret;
  1004. }
  1005. static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
  1006. {
  1007. struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
  1008. unsigned int reg = AXP20X_DCDC_MODE;
  1009. unsigned int mask;
  1010. switch (axp20x->variant) {
  1011. case AXP202_ID:
  1012. case AXP209_ID:
  1013. if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
  1014. return -EINVAL;
  1015. mask = AXP20X_WORKMODE_DCDC2_MASK;
  1016. if (id == AXP20X_DCDC3)
  1017. mask = AXP20X_WORKMODE_DCDC3_MASK;
  1018. workmode <<= ffs(mask) - 1;
  1019. break;
  1020. case AXP806_ID:
  1021. /*
  1022. * AXP806 DCDC regulator IDs have the same range as AXP22X.
  1023. * (See include/linux/mfd/axp20x.h)
  1024. */
  1025. reg = AXP806_DCDC_MODE_CTRL2;
  1026. fallthrough; /* to the check below */
  1027. case AXP221_ID:
  1028. case AXP223_ID:
  1029. case AXP809_ID:
  1030. if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
  1031. return -EINVAL;
  1032. mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
  1033. workmode <<= id - AXP22X_DCDC1;
  1034. break;
  1035. case AXP803_ID:
  1036. if (id < AXP803_DCDC1 || id > AXP803_DCDC6)
  1037. return -EINVAL;
  1038. mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);
  1039. workmode <<= id - AXP803_DCDC1;
  1040. break;
  1041. case AXP813_ID:
  1042. if (id < AXP813_DCDC1 || id > AXP813_DCDC7)
  1043. return -EINVAL;
  1044. mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);
  1045. workmode <<= id - AXP813_DCDC1;
  1046. break;
  1047. default:
  1048. /* should not happen */
  1049. WARN_ON(1);
  1050. return -EINVAL;
  1051. }
  1052. return regmap_update_bits(rdev->regmap, reg, mask, workmode);
  1053. }
  1054. /*
  1055. * This function checks whether a regulator is part of a poly-phase
  1056. * output setup based on the registers settings. Returns true if it is.
  1057. */
  1058. static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
  1059. {
  1060. u32 reg = 0;
  1061. /*
  1062. * Currently in our supported AXP variants, only AXP803, AXP806,
  1063. * and AXP813 have polyphase regulators.
  1064. */
  1065. switch (axp20x->variant) {
  1066. case AXP803_ID:
  1067. case AXP813_ID:
  1068. regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, &reg);
  1069. switch (id) {
  1070. case AXP803_DCDC3:
  1071. return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
  1072. case AXP803_DCDC6:
  1073. return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
  1074. }
  1075. break;
  1076. case AXP806_ID:
  1077. regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, &reg);
  1078. switch (id) {
  1079. case AXP806_DCDCB:
  1080. return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
  1081. AXP806_DCDCAB_POLYPHASE_DUAL) ||
  1082. ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
  1083. AXP806_DCDCABC_POLYPHASE_TRI));
  1084. case AXP806_DCDCC:
  1085. return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
  1086. AXP806_DCDCABC_POLYPHASE_TRI);
  1087. case AXP806_DCDCE:
  1088. return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
  1089. }
  1090. break;
  1091. default:
  1092. return false;
  1093. }
  1094. return false;
  1095. }
  1096. static int axp20x_regulator_probe(struct platform_device *pdev)
  1097. {
  1098. struct regulator_dev *rdev;
  1099. struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
  1100. const struct regulator_desc *regulators;
  1101. struct regulator_config config = {
  1102. .dev = pdev->dev.parent,
  1103. .regmap = axp20x->regmap,
  1104. .driver_data = axp20x,
  1105. };
  1106. int ret, i, nregulators;
  1107. u32 workmode;
  1108. const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
  1109. const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
  1110. bool drivevbus = false;
  1111. switch (axp20x->variant) {
  1112. case AXP202_ID:
  1113. case AXP209_ID:
  1114. regulators = axp20x_regulators;
  1115. nregulators = AXP20X_REG_ID_MAX;
  1116. break;
  1117. case AXP221_ID:
  1118. case AXP223_ID:
  1119. regulators = axp22x_regulators;
  1120. nregulators = AXP22X_REG_ID_MAX;
  1121. drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
  1122. "x-powers,drive-vbus-en");
  1123. break;
  1124. case AXP803_ID:
  1125. regulators = axp803_regulators;
  1126. nregulators = AXP803_REG_ID_MAX;
  1127. drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
  1128. "x-powers,drive-vbus-en");
  1129. break;
  1130. case AXP806_ID:
  1131. regulators = axp806_regulators;
  1132. nregulators = AXP806_REG_ID_MAX;
  1133. break;
  1134. case AXP809_ID:
  1135. regulators = axp809_regulators;
  1136. nregulators = AXP809_REG_ID_MAX;
  1137. break;
  1138. case AXP813_ID:
  1139. regulators = axp813_regulators;
  1140. nregulators = AXP813_REG_ID_MAX;
  1141. drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
  1142. "x-powers,drive-vbus-en");
  1143. break;
  1144. default:
  1145. dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
  1146. axp20x->variant);
  1147. return -EINVAL;
  1148. }
  1149. /* This only sets the dcdc freq. Ignore any errors */
  1150. axp20x_regulator_parse_dt(pdev);
  1151. for (i = 0; i < nregulators; i++) {
  1152. const struct regulator_desc *desc = &regulators[i];
  1153. struct regulator_desc *new_desc;
  1154. /*
  1155. * If this regulator is a slave in a poly-phase setup,
  1156. * skip it, as its controls are bound to the master
  1157. * regulator and won't work.
  1158. */
  1159. if (axp20x_is_polyphase_slave(axp20x, i))
  1160. continue;
  1161. /* Support for AXP813's FLDO3 is not implemented */
  1162. if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)
  1163. continue;
  1164. /*
  1165. * Regulators DC1SW and DC5LDO are connected internally,
  1166. * so we have to handle their supply names separately.
  1167. *
  1168. * We always register the regulators in proper sequence,
  1169. * so the supply names are correctly read. See the last
  1170. * part of this loop to see where we save the DT defined
  1171. * name.
  1172. */
  1173. if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
  1174. (regulators == axp803_regulators && i == AXP803_DC1SW) ||
  1175. (regulators == axp809_regulators && i == AXP809_DC1SW)) {
  1176. new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
  1177. GFP_KERNEL);
  1178. if (!new_desc)
  1179. return -ENOMEM;
  1180. *new_desc = regulators[i];
  1181. new_desc->supply_name = dcdc1_name;
  1182. desc = new_desc;
  1183. }
  1184. if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
  1185. (regulators == axp809_regulators && i == AXP809_DC5LDO)) {
  1186. new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
  1187. GFP_KERNEL);
  1188. if (!new_desc)
  1189. return -ENOMEM;
  1190. *new_desc = regulators[i];
  1191. new_desc->supply_name = dcdc5_name;
  1192. desc = new_desc;
  1193. }
  1194. rdev = devm_regulator_register(&pdev->dev, desc, &config);
  1195. if (IS_ERR(rdev)) {
  1196. dev_err(&pdev->dev, "Failed to register %s\n",
  1197. regulators[i].name);
  1198. return PTR_ERR(rdev);
  1199. }
  1200. ret = of_property_read_u32(rdev->dev.of_node,
  1201. "x-powers,dcdc-workmode",
  1202. &workmode);
  1203. if (!ret) {
  1204. if (axp20x_set_dcdc_workmode(rdev, i, workmode))
  1205. dev_err(&pdev->dev, "Failed to set workmode on %s\n",
  1206. rdev->desc->name);
  1207. }
  1208. /*
  1209. * Save AXP22X DCDC1 / DCDC5 regulator names for later.
  1210. */
  1211. if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
  1212. (regulators == axp809_regulators && i == AXP809_DCDC1))
  1213. of_property_read_string(rdev->dev.of_node,
  1214. "regulator-name",
  1215. &dcdc1_name);
  1216. if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
  1217. (regulators == axp809_regulators && i == AXP809_DCDC5))
  1218. of_property_read_string(rdev->dev.of_node,
  1219. "regulator-name",
  1220. &dcdc5_name);
  1221. }
  1222. if (drivevbus) {
  1223. /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
  1224. regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
  1225. AXP22X_MISC_N_VBUSEN_FUNC, 0);
  1226. rdev = devm_regulator_register(&pdev->dev,
  1227. &axp22x_drivevbus_regulator,
  1228. &config);
  1229. if (IS_ERR(rdev)) {
  1230. dev_err(&pdev->dev, "Failed to register drivevbus\n");
  1231. return PTR_ERR(rdev);
  1232. }
  1233. }
  1234. return 0;
  1235. }
  1236. static struct platform_driver axp20x_regulator_driver = {
  1237. .probe = axp20x_regulator_probe,
  1238. .driver = {
  1239. .name = "axp20x-regulator",
  1240. },
  1241. };
  1242. module_platform_driver(axp20x_regulator_driver);
  1243. MODULE_LICENSE("GPL v2");
  1244. MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
  1245. MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
  1246. MODULE_ALIAS("platform:axp20x-regulator");