anatop-regulator.c 9.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352
  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
  4. #include <linux/slab.h>
  5. #include <linux/device.h>
  6. #include <linux/module.h>
  7. #include <linux/mfd/syscon.h>
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/regmap.h>
  14. #include <linux/regulator/driver.h>
  15. #include <linux/regulator/of_regulator.h>
  16. #include <linux/regulator/machine.h>
  17. #define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
  18. #define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
  19. #define LDO_POWER_GATE 0x00
  20. #define LDO_FET_FULL_ON 0x1f
  21. struct anatop_regulator {
  22. u32 delay_reg;
  23. int delay_bit_shift;
  24. int delay_bit_width;
  25. struct regulator_desc rdesc;
  26. bool bypass;
  27. int sel;
  28. };
  29. static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
  30. unsigned int old_sel,
  31. unsigned int new_sel)
  32. {
  33. struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
  34. u32 val;
  35. int ret = 0;
  36. /* check whether need to care about LDO ramp up speed */
  37. if (anatop_reg->delay_bit_width && new_sel > old_sel) {
  38. /*
  39. * the delay for LDO ramp up time is
  40. * based on the register setting, we need
  41. * to calculate how many steps LDO need to
  42. * ramp up, and how much delay needed. (us)
  43. */
  44. regmap_read(reg->regmap, anatop_reg->delay_reg, &val);
  45. val = (val >> anatop_reg->delay_bit_shift) &
  46. ((1 << anatop_reg->delay_bit_width) - 1);
  47. ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
  48. val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
  49. }
  50. return ret;
  51. }
  52. static int anatop_regmap_enable(struct regulator_dev *reg)
  53. {
  54. struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
  55. int sel;
  56. sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
  57. return regulator_set_voltage_sel_regmap(reg, sel);
  58. }
  59. static int anatop_regmap_disable(struct regulator_dev *reg)
  60. {
  61. return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
  62. }
  63. static int anatop_regmap_is_enabled(struct regulator_dev *reg)
  64. {
  65. return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
  66. }
  67. static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
  68. unsigned selector)
  69. {
  70. struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
  71. int ret;
  72. if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
  73. anatop_reg->sel = selector;
  74. return 0;
  75. }
  76. ret = regulator_set_voltage_sel_regmap(reg, selector);
  77. if (!ret)
  78. anatop_reg->sel = selector;
  79. return ret;
  80. }
  81. static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
  82. {
  83. struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
  84. if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
  85. return anatop_reg->sel;
  86. return regulator_get_voltage_sel_regmap(reg);
  87. }
  88. static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable)
  89. {
  90. struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
  91. int sel;
  92. sel = regulator_get_voltage_sel_regmap(reg);
  93. if (sel == LDO_FET_FULL_ON)
  94. WARN_ON(!anatop_reg->bypass);
  95. else if (sel != LDO_POWER_GATE)
  96. WARN_ON(anatop_reg->bypass);
  97. *enable = anatop_reg->bypass;
  98. return 0;
  99. }
  100. static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
  101. {
  102. struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
  103. int sel;
  104. if (enable == anatop_reg->bypass)
  105. return 0;
  106. sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
  107. anatop_reg->bypass = enable;
  108. return regulator_set_voltage_sel_regmap(reg, sel);
  109. }
  110. static struct regulator_ops anatop_rops = {
  111. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  112. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  113. .list_voltage = regulator_list_voltage_linear,
  114. .map_voltage = regulator_map_voltage_linear,
  115. };
  116. static const struct regulator_ops anatop_core_rops = {
  117. .enable = anatop_regmap_enable,
  118. .disable = anatop_regmap_disable,
  119. .is_enabled = anatop_regmap_is_enabled,
  120. .set_voltage_sel = anatop_regmap_core_set_voltage_sel,
  121. .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
  122. .get_voltage_sel = anatop_regmap_core_get_voltage_sel,
  123. .list_voltage = regulator_list_voltage_linear,
  124. .map_voltage = regulator_map_voltage_linear,
  125. .get_bypass = anatop_regmap_get_bypass,
  126. .set_bypass = anatop_regmap_set_bypass,
  127. };
  128. static int anatop_regulator_probe(struct platform_device *pdev)
  129. {
  130. struct device *dev = &pdev->dev;
  131. struct device_node *np = dev->of_node;
  132. struct device_node *anatop_np;
  133. struct regulator_desc *rdesc;
  134. struct regulator_dev *rdev;
  135. struct anatop_regulator *sreg;
  136. struct regulator_init_data *initdata;
  137. struct regulator_config config = { };
  138. struct regmap *regmap;
  139. u32 control_reg;
  140. u32 vol_bit_shift;
  141. u32 vol_bit_width;
  142. u32 min_bit_val;
  143. u32 min_voltage;
  144. u32 max_voltage;
  145. int ret = 0;
  146. u32 val;
  147. sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
  148. if (!sreg)
  149. return -ENOMEM;
  150. rdesc = &sreg->rdesc;
  151. rdesc->type = REGULATOR_VOLTAGE;
  152. rdesc->owner = THIS_MODULE;
  153. of_property_read_string(np, "regulator-name", &rdesc->name);
  154. if (!rdesc->name) {
  155. dev_err(dev, "failed to get a regulator-name\n");
  156. return -EINVAL;
  157. }
  158. initdata = of_get_regulator_init_data(dev, np, rdesc);
  159. if (!initdata)
  160. return -ENOMEM;
  161. initdata->supply_regulator = "vin";
  162. anatop_np = of_get_parent(np);
  163. if (!anatop_np)
  164. return -ENODEV;
  165. regmap = syscon_node_to_regmap(anatop_np);
  166. of_node_put(anatop_np);
  167. if (IS_ERR(regmap))
  168. return PTR_ERR(regmap);
  169. ret = of_property_read_u32(np, "anatop-reg-offset", &control_reg);
  170. if (ret) {
  171. dev_err(dev, "no anatop-reg-offset property set\n");
  172. return ret;
  173. }
  174. ret = of_property_read_u32(np, "anatop-vol-bit-width", &vol_bit_width);
  175. if (ret) {
  176. dev_err(dev, "no anatop-vol-bit-width property set\n");
  177. return ret;
  178. }
  179. ret = of_property_read_u32(np, "anatop-vol-bit-shift", &vol_bit_shift);
  180. if (ret) {
  181. dev_err(dev, "no anatop-vol-bit-shift property set\n");
  182. return ret;
  183. }
  184. ret = of_property_read_u32(np, "anatop-min-bit-val", &min_bit_val);
  185. if (ret) {
  186. dev_err(dev, "no anatop-min-bit-val property set\n");
  187. return ret;
  188. }
  189. ret = of_property_read_u32(np, "anatop-min-voltage", &min_voltage);
  190. if (ret) {
  191. dev_err(dev, "no anatop-min-voltage property set\n");
  192. return ret;
  193. }
  194. ret = of_property_read_u32(np, "anatop-max-voltage", &max_voltage);
  195. if (ret) {
  196. dev_err(dev, "no anatop-max-voltage property set\n");
  197. return ret;
  198. }
  199. /* read LDO ramp up setting, only for core reg */
  200. of_property_read_u32(np, "anatop-delay-reg-offset",
  201. &sreg->delay_reg);
  202. of_property_read_u32(np, "anatop-delay-bit-width",
  203. &sreg->delay_bit_width);
  204. of_property_read_u32(np, "anatop-delay-bit-shift",
  205. &sreg->delay_bit_shift);
  206. rdesc->n_voltages = (max_voltage - min_voltage) / 25000 + 1
  207. + min_bit_val;
  208. rdesc->min_uV = min_voltage;
  209. rdesc->uV_step = 25000;
  210. rdesc->linear_min_sel = min_bit_val;
  211. rdesc->vsel_reg = control_reg;
  212. rdesc->vsel_mask = ((1 << vol_bit_width) - 1) << vol_bit_shift;
  213. rdesc->min_dropout_uV = 125000;
  214. config.dev = &pdev->dev;
  215. config.init_data = initdata;
  216. config.driver_data = sreg;
  217. config.of_node = pdev->dev.of_node;
  218. config.regmap = regmap;
  219. /* Only core regulators have the ramp up delay configuration. */
  220. if (control_reg && sreg->delay_bit_width) {
  221. rdesc->ops = &anatop_core_rops;
  222. ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
  223. if (ret) {
  224. dev_err(dev, "failed to read initial state\n");
  225. return ret;
  226. }
  227. sreg->sel = (val & rdesc->vsel_mask) >> vol_bit_shift;
  228. if (sreg->sel == LDO_FET_FULL_ON) {
  229. sreg->sel = 0;
  230. sreg->bypass = true;
  231. }
  232. /*
  233. * In case vddpu was disabled by the bootloader, we need to set
  234. * a sane default until imx6-cpufreq was probed and changes the
  235. * voltage to the correct value. In this case we set 1.25V.
  236. */
  237. if (!sreg->sel && !strcmp(rdesc->name, "vddpu"))
  238. sreg->sel = 22;
  239. /* set the default voltage of the pcie phy to be 1.100v */
  240. if (!sreg->sel && !strcmp(rdesc->name, "vddpcie"))
  241. sreg->sel = 0x10;
  242. if (!sreg->bypass && !sreg->sel) {
  243. dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
  244. return -EINVAL;
  245. }
  246. } else {
  247. u32 enable_bit;
  248. rdesc->ops = &anatop_rops;
  249. if (!of_property_read_u32(np, "anatop-enable-bit",
  250. &enable_bit)) {
  251. anatop_rops.enable = regulator_enable_regmap;
  252. anatop_rops.disable = regulator_disable_regmap;
  253. anatop_rops.is_enabled = regulator_is_enabled_regmap;
  254. rdesc->enable_reg = control_reg;
  255. rdesc->enable_mask = BIT(enable_bit);
  256. }
  257. }
  258. /* register regulator */
  259. rdev = devm_regulator_register(dev, rdesc, &config);
  260. if (IS_ERR(rdev)) {
  261. ret = PTR_ERR(rdev);
  262. if (ret == -EPROBE_DEFER)
  263. dev_dbg(dev, "failed to register %s, deferring...\n",
  264. rdesc->name);
  265. else
  266. dev_err(dev, "failed to register %s\n", rdesc->name);
  267. return ret;
  268. }
  269. platform_set_drvdata(pdev, rdev);
  270. return 0;
  271. }
  272. static const struct of_device_id of_anatop_regulator_match_tbl[] = {
  273. { .compatible = "fsl,anatop-regulator", },
  274. { /* end */ }
  275. };
  276. MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);
  277. static struct platform_driver anatop_regulator_driver = {
  278. .driver = {
  279. .name = "anatop_regulator",
  280. .of_match_table = of_anatop_regulator_match_tbl,
  281. },
  282. .probe = anatop_regulator_probe,
  283. };
  284. static int __init anatop_regulator_init(void)
  285. {
  286. return platform_driver_register(&anatop_regulator_driver);
  287. }
  288. postcore_initcall(anatop_regulator_init);
  289. static void __exit anatop_regulator_exit(void)
  290. {
  291. platform_driver_unregister(&anatop_regulator_driver);
  292. }
  293. module_exit(anatop_regulator_exit);
  294. MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
  295. MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
  296. MODULE_DESCRIPTION("ANATOP Regulator driver");
  297. MODULE_LICENSE("GPL v2");
  298. MODULE_ALIAS("platform:anatop_regulator");