pwm-zx.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2017 Sanechips Technology Co., Ltd.
  4. * Copyright 2017 Linaro Ltd.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pwm.h>
  13. #include <linux/slab.h>
  14. #define ZX_PWM_MODE 0x0
  15. #define ZX_PWM_CLKDIV_SHIFT 2
  16. #define ZX_PWM_CLKDIV_MASK GENMASK(11, 2)
  17. #define ZX_PWM_CLKDIV(x) (((x) << ZX_PWM_CLKDIV_SHIFT) & \
  18. ZX_PWM_CLKDIV_MASK)
  19. #define ZX_PWM_POLAR BIT(1)
  20. #define ZX_PWM_EN BIT(0)
  21. #define ZX_PWM_PERIOD 0x4
  22. #define ZX_PWM_DUTY 0x8
  23. #define ZX_PWM_CLKDIV_MAX 1023
  24. #define ZX_PWM_PERIOD_MAX 65535
  25. struct zx_pwm_chip {
  26. struct pwm_chip chip;
  27. struct clk *pclk;
  28. struct clk *wclk;
  29. void __iomem *base;
  30. };
  31. static inline struct zx_pwm_chip *to_zx_pwm_chip(struct pwm_chip *chip)
  32. {
  33. return container_of(chip, struct zx_pwm_chip, chip);
  34. }
  35. static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm,
  36. unsigned int offset)
  37. {
  38. return readl(zpc->base + (hwpwm + 1) * 0x10 + offset);
  39. }
  40. static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm,
  41. unsigned int offset, u32 value)
  42. {
  43. writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset);
  44. }
  45. static void zx_pwm_set_mask(struct zx_pwm_chip *zpc, unsigned int hwpwm,
  46. unsigned int offset, u32 mask, u32 value)
  47. {
  48. u32 data;
  49. data = zx_pwm_readl(zpc, hwpwm, offset);
  50. data &= ~mask;
  51. data |= value & mask;
  52. zx_pwm_writel(zpc, hwpwm, offset, data);
  53. }
  54. static void zx_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  55. struct pwm_state *state)
  56. {
  57. struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
  58. unsigned long rate;
  59. unsigned int div;
  60. u32 value;
  61. u64 tmp;
  62. value = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE);
  63. if (value & ZX_PWM_POLAR)
  64. state->polarity = PWM_POLARITY_NORMAL;
  65. else
  66. state->polarity = PWM_POLARITY_INVERSED;
  67. if (value & ZX_PWM_EN)
  68. state->enabled = true;
  69. else
  70. state->enabled = false;
  71. div = (value & ZX_PWM_CLKDIV_MASK) >> ZX_PWM_CLKDIV_SHIFT;
  72. rate = clk_get_rate(zpc->wclk);
  73. tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_PERIOD);
  74. tmp *= div * NSEC_PER_SEC;
  75. state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
  76. tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_DUTY);
  77. tmp *= div * NSEC_PER_SEC;
  78. state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
  79. }
  80. static int zx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  81. unsigned int duty_ns, unsigned int period_ns)
  82. {
  83. struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
  84. unsigned int period_cycles, duty_cycles;
  85. unsigned long long c;
  86. unsigned int div = 1;
  87. unsigned long rate;
  88. /* Find out the best divider */
  89. rate = clk_get_rate(zpc->wclk);
  90. while (1) {
  91. c = rate / div;
  92. c = c * period_ns;
  93. do_div(c, NSEC_PER_SEC);
  94. if (c < ZX_PWM_PERIOD_MAX)
  95. break;
  96. div++;
  97. if (div > ZX_PWM_CLKDIV_MAX)
  98. return -ERANGE;
  99. }
  100. /* Calculate duty cycles */
  101. period_cycles = c;
  102. c *= duty_ns;
  103. do_div(c, period_ns);
  104. duty_cycles = c;
  105. /*
  106. * If the PWM is being enabled, we have to temporarily disable it
  107. * before configuring the registers.
  108. */
  109. if (pwm_is_enabled(pwm))
  110. zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_EN, 0);
  111. /* Set up registers */
  112. zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_CLKDIV_MASK,
  113. ZX_PWM_CLKDIV(div));
  114. zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_PERIOD, period_cycles);
  115. zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_DUTY, duty_cycles);
  116. /* Re-enable the PWM if needed */
  117. if (pwm_is_enabled(pwm))
  118. zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
  119. ZX_PWM_EN, ZX_PWM_EN);
  120. return 0;
  121. }
  122. static int zx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  123. const struct pwm_state *state)
  124. {
  125. struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
  126. struct pwm_state cstate;
  127. int ret;
  128. pwm_get_state(pwm, &cstate);
  129. if (state->polarity != cstate.polarity)
  130. zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_POLAR,
  131. (state->polarity == PWM_POLARITY_INVERSED) ?
  132. 0 : ZX_PWM_POLAR);
  133. if (state->period != cstate.period ||
  134. state->duty_cycle != cstate.duty_cycle) {
  135. ret = zx_pwm_config(chip, pwm, state->duty_cycle,
  136. state->period);
  137. if (ret)
  138. return ret;
  139. }
  140. if (state->enabled != cstate.enabled) {
  141. if (state->enabled) {
  142. ret = clk_prepare_enable(zpc->wclk);
  143. if (ret)
  144. return ret;
  145. zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
  146. ZX_PWM_EN, ZX_PWM_EN);
  147. } else {
  148. zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
  149. ZX_PWM_EN, 0);
  150. clk_disable_unprepare(zpc->wclk);
  151. }
  152. }
  153. return 0;
  154. }
  155. static const struct pwm_ops zx_pwm_ops = {
  156. .apply = zx_pwm_apply,
  157. .get_state = zx_pwm_get_state,
  158. .owner = THIS_MODULE,
  159. };
  160. static int zx_pwm_probe(struct platform_device *pdev)
  161. {
  162. struct zx_pwm_chip *zpc;
  163. struct resource *res;
  164. unsigned int i;
  165. int ret;
  166. zpc = devm_kzalloc(&pdev->dev, sizeof(*zpc), GFP_KERNEL);
  167. if (!zpc)
  168. return -ENOMEM;
  169. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  170. zpc->base = devm_ioremap_resource(&pdev->dev, res);
  171. if (IS_ERR(zpc->base))
  172. return PTR_ERR(zpc->base);
  173. zpc->pclk = devm_clk_get(&pdev->dev, "pclk");
  174. if (IS_ERR(zpc->pclk))
  175. return PTR_ERR(zpc->pclk);
  176. zpc->wclk = devm_clk_get(&pdev->dev, "wclk");
  177. if (IS_ERR(zpc->wclk))
  178. return PTR_ERR(zpc->wclk);
  179. ret = clk_prepare_enable(zpc->pclk);
  180. if (ret)
  181. return ret;
  182. zpc->chip.dev = &pdev->dev;
  183. zpc->chip.ops = &zx_pwm_ops;
  184. zpc->chip.base = -1;
  185. zpc->chip.npwm = 4;
  186. zpc->chip.of_xlate = of_pwm_xlate_with_flags;
  187. zpc->chip.of_pwm_n_cells = 3;
  188. /*
  189. * PWM devices may be enabled by firmware, and let's disable all of
  190. * them initially to save power.
  191. */
  192. for (i = 0; i < zpc->chip.npwm; i++)
  193. zx_pwm_set_mask(zpc, i, ZX_PWM_MODE, ZX_PWM_EN, 0);
  194. ret = pwmchip_add(&zpc->chip);
  195. if (ret < 0) {
  196. dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  197. clk_disable_unprepare(zpc->pclk);
  198. return ret;
  199. }
  200. platform_set_drvdata(pdev, zpc);
  201. return 0;
  202. }
  203. static int zx_pwm_remove(struct platform_device *pdev)
  204. {
  205. struct zx_pwm_chip *zpc = platform_get_drvdata(pdev);
  206. int ret;
  207. ret = pwmchip_remove(&zpc->chip);
  208. clk_disable_unprepare(zpc->pclk);
  209. return ret;
  210. }
  211. static const struct of_device_id zx_pwm_dt_ids[] = {
  212. { .compatible = "zte,zx296718-pwm", },
  213. { /* sentinel */ }
  214. };
  215. MODULE_DEVICE_TABLE(of, zx_pwm_dt_ids);
  216. static struct platform_driver zx_pwm_driver = {
  217. .driver = {
  218. .name = "zx-pwm",
  219. .of_match_table = zx_pwm_dt_ids,
  220. },
  221. .probe = zx_pwm_probe,
  222. .remove = zx_pwm_remove,
  223. };
  224. module_platform_driver(zx_pwm_driver);
  225. MODULE_ALIAS("platform:zx-pwm");
  226. MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
  227. MODULE_DESCRIPTION("ZTE ZX PWM Driver");
  228. MODULE_LICENSE("GPL v2");