pwm-tiehrpwm.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * EHRPWM PWM driver
  4. *
  5. * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
  6. */
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/pwm.h>
  10. #include <linux/io.h>
  11. #include <linux/err.h>
  12. #include <linux/clk.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/of_device.h>
  15. /* EHRPWM registers and bits definitions */
  16. /* Time base module registers */
  17. #define TBCTL 0x00
  18. #define TBPRD 0x0A
  19. #define TBCTL_PRDLD_MASK BIT(3)
  20. #define TBCTL_PRDLD_SHDW 0
  21. #define TBCTL_PRDLD_IMDT BIT(3)
  22. #define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
  23. BIT(8) | BIT(7))
  24. #define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
  25. #define TBCTL_CTRMODE_UP 0
  26. #define TBCTL_CTRMODE_DOWN BIT(0)
  27. #define TBCTL_CTRMODE_UPDOWN BIT(1)
  28. #define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0))
  29. #define TBCTL_HSPCLKDIV_SHIFT 7
  30. #define TBCTL_CLKDIV_SHIFT 10
  31. #define CLKDIV_MAX 7
  32. #define HSPCLKDIV_MAX 7
  33. #define PERIOD_MAX 0xFFFF
  34. /* compare module registers */
  35. #define CMPA 0x12
  36. #define CMPB 0x14
  37. /* Action qualifier module registers */
  38. #define AQCTLA 0x16
  39. #define AQCTLB 0x18
  40. #define AQSFRC 0x1A
  41. #define AQCSFRC 0x1C
  42. #define AQCTL_CBU_MASK (BIT(9) | BIT(8))
  43. #define AQCTL_CBU_FRCLOW BIT(8)
  44. #define AQCTL_CBU_FRCHIGH BIT(9)
  45. #define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8))
  46. #define AQCTL_CAU_MASK (BIT(5) | BIT(4))
  47. #define AQCTL_CAU_FRCLOW BIT(4)
  48. #define AQCTL_CAU_FRCHIGH BIT(5)
  49. #define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4))
  50. #define AQCTL_PRD_MASK (BIT(3) | BIT(2))
  51. #define AQCTL_PRD_FRCLOW BIT(2)
  52. #define AQCTL_PRD_FRCHIGH BIT(3)
  53. #define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2))
  54. #define AQCTL_ZRO_MASK (BIT(1) | BIT(0))
  55. #define AQCTL_ZRO_FRCLOW BIT(0)
  56. #define AQCTL_ZRO_FRCHIGH BIT(1)
  57. #define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0))
  58. #define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \
  59. AQCTL_ZRO_FRCHIGH)
  60. #define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \
  61. AQCTL_ZRO_FRCLOW)
  62. #define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \
  63. AQCTL_ZRO_FRCHIGH)
  64. #define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \
  65. AQCTL_ZRO_FRCLOW)
  66. #define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6))
  67. #define AQSFRC_RLDCSF_ZRO 0
  68. #define AQSFRC_RLDCSF_PRD BIT(6)
  69. #define AQSFRC_RLDCSF_ZROPRD BIT(7)
  70. #define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6))
  71. #define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2))
  72. #define AQCSFRC_CSFB_FRCDIS 0
  73. #define AQCSFRC_CSFB_FRCLOW BIT(2)
  74. #define AQCSFRC_CSFB_FRCHIGH BIT(3)
  75. #define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2))
  76. #define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0))
  77. #define AQCSFRC_CSFA_FRCDIS 0
  78. #define AQCSFRC_CSFA_FRCLOW BIT(0)
  79. #define AQCSFRC_CSFA_FRCHIGH BIT(1)
  80. #define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0))
  81. #define NUM_PWM_CHANNEL 2 /* EHRPWM channels */
  82. struct ehrpwm_context {
  83. u16 tbctl;
  84. u16 tbprd;
  85. u16 cmpa;
  86. u16 cmpb;
  87. u16 aqctla;
  88. u16 aqctlb;
  89. u16 aqsfrc;
  90. u16 aqcsfrc;
  91. };
  92. struct ehrpwm_pwm_chip {
  93. struct pwm_chip chip;
  94. unsigned long clk_rate;
  95. void __iomem *mmio_base;
  96. unsigned long period_cycles[NUM_PWM_CHANNEL];
  97. enum pwm_polarity polarity[NUM_PWM_CHANNEL];
  98. struct clk *tbclk;
  99. struct ehrpwm_context ctx;
  100. };
  101. static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip)
  102. {
  103. return container_of(chip, struct ehrpwm_pwm_chip, chip);
  104. }
  105. static inline u16 ehrpwm_read(void __iomem *base, unsigned int offset)
  106. {
  107. return readw(base + offset);
  108. }
  109. static inline void ehrpwm_write(void __iomem *base, unsigned int offset,
  110. u16 value)
  111. {
  112. writew(value, base + offset);
  113. }
  114. static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask,
  115. u16 value)
  116. {
  117. unsigned short val;
  118. val = readw(base + offset);
  119. val &= ~mask;
  120. val |= value & mask;
  121. writew(val, base + offset);
  122. }
  123. /**
  124. * set_prescale_div - Set up the prescaler divider function
  125. * @rqst_prescaler: prescaler value min
  126. * @prescale_div: prescaler value set
  127. * @tb_clk_div: Time Base Control prescaler bits
  128. */
  129. static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div,
  130. u16 *tb_clk_div)
  131. {
  132. unsigned int clkdiv, hspclkdiv;
  133. for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) {
  134. for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) {
  135. /*
  136. * calculations for prescaler value :
  137. * prescale_div = HSPCLKDIVIDER * CLKDIVIDER.
  138. * HSPCLKDIVIDER = 2 ** hspclkdiv
  139. * CLKDIVIDER = (1), if clkdiv == 0 *OR*
  140. * (2 * clkdiv), if clkdiv != 0
  141. *
  142. * Configure prescale_div value such that period
  143. * register value is less than 65535.
  144. */
  145. *prescale_div = (1 << clkdiv) *
  146. (hspclkdiv ? (hspclkdiv * 2) : 1);
  147. if (*prescale_div > rqst_prescaler) {
  148. *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) |
  149. (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT);
  150. return 0;
  151. }
  152. }
  153. }
  154. return 1;
  155. }
  156. static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan)
  157. {
  158. u16 aqctl_val, aqctl_mask;
  159. unsigned int aqctl_reg;
  160. /*
  161. * Configure PWM output to HIGH/LOW level on counter
  162. * reaches compare register value and LOW/HIGH level
  163. * on counter value reaches period register value and
  164. * zero value on counter
  165. */
  166. if (chan == 1) {
  167. aqctl_reg = AQCTLB;
  168. aqctl_mask = AQCTL_CBU_MASK;
  169. if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
  170. aqctl_val = AQCTL_CHANB_POLINVERSED;
  171. else
  172. aqctl_val = AQCTL_CHANB_POLNORMAL;
  173. } else {
  174. aqctl_reg = AQCTLA;
  175. aqctl_mask = AQCTL_CAU_MASK;
  176. if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
  177. aqctl_val = AQCTL_CHANA_POLINVERSED;
  178. else
  179. aqctl_val = AQCTL_CHANA_POLNORMAL;
  180. }
  181. aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK;
  182. ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
  183. }
  184. /*
  185. * period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE
  186. * duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE
  187. */
  188. static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  189. int duty_ns, int period_ns)
  190. {
  191. struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
  192. u32 period_cycles, duty_cycles;
  193. u16 ps_divval, tb_divval;
  194. unsigned int i, cmp_reg;
  195. unsigned long long c;
  196. if (period_ns > NSEC_PER_SEC)
  197. return -ERANGE;
  198. c = pc->clk_rate;
  199. c = c * period_ns;
  200. do_div(c, NSEC_PER_SEC);
  201. period_cycles = (unsigned long)c;
  202. if (period_cycles < 1) {
  203. period_cycles = 1;
  204. duty_cycles = 1;
  205. } else {
  206. c = pc->clk_rate;
  207. c = c * duty_ns;
  208. do_div(c, NSEC_PER_SEC);
  209. duty_cycles = (unsigned long)c;
  210. }
  211. /*
  212. * Period values should be same for multiple PWM channels as IP uses
  213. * same period register for multiple channels.
  214. */
  215. for (i = 0; i < NUM_PWM_CHANNEL; i++) {
  216. if (pc->period_cycles[i] &&
  217. (pc->period_cycles[i] != period_cycles)) {
  218. /*
  219. * Allow channel to reconfigure period if no other
  220. * channels being configured.
  221. */
  222. if (i == pwm->hwpwm)
  223. continue;
  224. dev_err(chip->dev,
  225. "period value conflicts with channel %u\n",
  226. i);
  227. return -EINVAL;
  228. }
  229. }
  230. pc->period_cycles[pwm->hwpwm] = period_cycles;
  231. /* Configure clock prescaler to support Low frequency PWM wave */
  232. if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval,
  233. &tb_divval)) {
  234. dev_err(chip->dev, "Unsupported values\n");
  235. return -EINVAL;
  236. }
  237. pm_runtime_get_sync(chip->dev);
  238. /* Update clock prescaler values */
  239. ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);
  240. /* Update period & duty cycle with presacler division */
  241. period_cycles = period_cycles / ps_divval;
  242. duty_cycles = duty_cycles / ps_divval;
  243. /* Configure shadow loading on Period register */
  244. ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);
  245. ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);
  246. /* Configure ehrpwm counter for up-count mode */
  247. ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
  248. TBCTL_CTRMODE_UP);
  249. if (pwm->hwpwm == 1)
  250. /* Channel 1 configured with compare B register */
  251. cmp_reg = CMPB;
  252. else
  253. /* Channel 0 configured with compare A register */
  254. cmp_reg = CMPA;
  255. ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
  256. pm_runtime_put_sync(chip->dev);
  257. return 0;
  258. }
  259. static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip,
  260. struct pwm_device *pwm,
  261. enum pwm_polarity polarity)
  262. {
  263. struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
  264. /* Configuration of polarity in hardware delayed, do at enable */
  265. pc->polarity[pwm->hwpwm] = polarity;
  266. return 0;
  267. }
  268. static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  269. {
  270. struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
  271. u16 aqcsfrc_val, aqcsfrc_mask;
  272. int ret;
  273. /* Leave clock enabled on enabling PWM */
  274. pm_runtime_get_sync(chip->dev);
  275. /* Disabling Action Qualifier on PWM output */
  276. if (pwm->hwpwm) {
  277. aqcsfrc_val = AQCSFRC_CSFB_FRCDIS;
  278. aqcsfrc_mask = AQCSFRC_CSFB_MASK;
  279. } else {
  280. aqcsfrc_val = AQCSFRC_CSFA_FRCDIS;
  281. aqcsfrc_mask = AQCSFRC_CSFA_MASK;
  282. }
  283. /* Changes to shadow mode */
  284. ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
  285. AQSFRC_RLDCSF_ZRO);
  286. ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
  287. /* Channels polarity can be configured from action qualifier module */
  288. configure_polarity(pc, pwm->hwpwm);
  289. /* Enable TBCLK */
  290. ret = clk_enable(pc->tbclk);
  291. if (ret) {
  292. dev_err(chip->dev, "Failed to enable TBCLK for %s: %d\n",
  293. dev_name(pc->chip.dev), ret);
  294. return ret;
  295. }
  296. return 0;
  297. }
  298. static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  299. {
  300. struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
  301. u16 aqcsfrc_val, aqcsfrc_mask;
  302. /* Action Qualifier puts PWM output low forcefully */
  303. if (pwm->hwpwm) {
  304. aqcsfrc_val = AQCSFRC_CSFB_FRCLOW;
  305. aqcsfrc_mask = AQCSFRC_CSFB_MASK;
  306. } else {
  307. aqcsfrc_val = AQCSFRC_CSFA_FRCLOW;
  308. aqcsfrc_mask = AQCSFRC_CSFA_MASK;
  309. }
  310. /* Update shadow register first before modifying active register */
  311. ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
  312. AQSFRC_RLDCSF_ZRO);
  313. ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
  314. /*
  315. * Changes to immediate action on Action Qualifier. This puts
  316. * Action Qualifier control on PWM output from next TBCLK
  317. */
  318. ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
  319. AQSFRC_RLDCSF_IMDT);
  320. ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
  321. /* Disabling TBCLK on PWM disable */
  322. clk_disable(pc->tbclk);
  323. /* Disable clock on PWM disable */
  324. pm_runtime_put_sync(chip->dev);
  325. }
  326. static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  327. {
  328. struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
  329. if (pwm_is_enabled(pwm)) {
  330. dev_warn(chip->dev, "Removing PWM device without disabling\n");
  331. pm_runtime_put_sync(chip->dev);
  332. }
  333. /* set period value to zero on free */
  334. pc->period_cycles[pwm->hwpwm] = 0;
  335. }
  336. static const struct pwm_ops ehrpwm_pwm_ops = {
  337. .free = ehrpwm_pwm_free,
  338. .config = ehrpwm_pwm_config,
  339. .set_polarity = ehrpwm_pwm_set_polarity,
  340. .enable = ehrpwm_pwm_enable,
  341. .disable = ehrpwm_pwm_disable,
  342. .owner = THIS_MODULE,
  343. };
  344. static const struct of_device_id ehrpwm_of_match[] = {
  345. { .compatible = "ti,am3352-ehrpwm" },
  346. { .compatible = "ti,am33xx-ehrpwm" },
  347. {},
  348. };
  349. MODULE_DEVICE_TABLE(of, ehrpwm_of_match);
  350. static int ehrpwm_pwm_probe(struct platform_device *pdev)
  351. {
  352. struct device_node *np = pdev->dev.of_node;
  353. struct ehrpwm_pwm_chip *pc;
  354. struct resource *r;
  355. struct clk *clk;
  356. int ret;
  357. pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
  358. if (!pc)
  359. return -ENOMEM;
  360. clk = devm_clk_get(&pdev->dev, "fck");
  361. if (IS_ERR(clk)) {
  362. if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
  363. dev_warn(&pdev->dev, "Binding is obsolete.\n");
  364. clk = devm_clk_get(pdev->dev.parent, "fck");
  365. }
  366. }
  367. if (IS_ERR(clk)) {
  368. dev_err(&pdev->dev, "failed to get clock\n");
  369. return PTR_ERR(clk);
  370. }
  371. pc->clk_rate = clk_get_rate(clk);
  372. if (!pc->clk_rate) {
  373. dev_err(&pdev->dev, "failed to get clock rate\n");
  374. return -EINVAL;
  375. }
  376. pc->chip.dev = &pdev->dev;
  377. pc->chip.ops = &ehrpwm_pwm_ops;
  378. pc->chip.of_xlate = of_pwm_xlate_with_flags;
  379. pc->chip.of_pwm_n_cells = 3;
  380. pc->chip.base = -1;
  381. pc->chip.npwm = NUM_PWM_CHANNEL;
  382. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  383. pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
  384. if (IS_ERR(pc->mmio_base))
  385. return PTR_ERR(pc->mmio_base);
  386. /* Acquire tbclk for Time Base EHRPWM submodule */
  387. pc->tbclk = devm_clk_get(&pdev->dev, "tbclk");
  388. if (IS_ERR(pc->tbclk)) {
  389. dev_err(&pdev->dev, "Failed to get tbclk\n");
  390. return PTR_ERR(pc->tbclk);
  391. }
  392. ret = clk_prepare(pc->tbclk);
  393. if (ret < 0) {
  394. dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret);
  395. return ret;
  396. }
  397. ret = pwmchip_add(&pc->chip);
  398. if (ret < 0) {
  399. dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
  400. goto err_clk_unprepare;
  401. }
  402. platform_set_drvdata(pdev, pc);
  403. pm_runtime_enable(&pdev->dev);
  404. return 0;
  405. err_clk_unprepare:
  406. clk_unprepare(pc->tbclk);
  407. return ret;
  408. }
  409. static int ehrpwm_pwm_remove(struct platform_device *pdev)
  410. {
  411. struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev);
  412. clk_unprepare(pc->tbclk);
  413. pm_runtime_disable(&pdev->dev);
  414. return pwmchip_remove(&pc->chip);
  415. }
  416. #ifdef CONFIG_PM_SLEEP
  417. static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc)
  418. {
  419. pm_runtime_get_sync(pc->chip.dev);
  420. pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL);
  421. pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD);
  422. pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA);
  423. pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB);
  424. pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA);
  425. pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB);
  426. pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC);
  427. pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC);
  428. pm_runtime_put_sync(pc->chip.dev);
  429. }
  430. static void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc)
  431. {
  432. ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd);
  433. ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa);
  434. ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb);
  435. ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla);
  436. ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb);
  437. ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc);
  438. ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc);
  439. ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl);
  440. }
  441. static int ehrpwm_pwm_suspend(struct device *dev)
  442. {
  443. struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
  444. unsigned int i;
  445. ehrpwm_pwm_save_context(pc);
  446. for (i = 0; i < pc->chip.npwm; i++) {
  447. struct pwm_device *pwm = &pc->chip.pwms[i];
  448. if (!pwm_is_enabled(pwm))
  449. continue;
  450. /* Disable explicitly if PWM is running */
  451. pm_runtime_put_sync(dev);
  452. }
  453. return 0;
  454. }
  455. static int ehrpwm_pwm_resume(struct device *dev)
  456. {
  457. struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
  458. unsigned int i;
  459. for (i = 0; i < pc->chip.npwm; i++) {
  460. struct pwm_device *pwm = &pc->chip.pwms[i];
  461. if (!pwm_is_enabled(pwm))
  462. continue;
  463. /* Enable explicitly if PWM was running */
  464. pm_runtime_get_sync(dev);
  465. }
  466. ehrpwm_pwm_restore_context(pc);
  467. return 0;
  468. }
  469. #endif
  470. static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend,
  471. ehrpwm_pwm_resume);
  472. static struct platform_driver ehrpwm_pwm_driver = {
  473. .driver = {
  474. .name = "ehrpwm",
  475. .of_match_table = ehrpwm_of_match,
  476. .pm = &ehrpwm_pwm_pm_ops,
  477. },
  478. .probe = ehrpwm_pwm_probe,
  479. .remove = ehrpwm_pwm_remove,
  480. };
  481. module_platform_driver(ehrpwm_pwm_driver);
  482. MODULE_DESCRIPTION("EHRPWM PWM driver");
  483. MODULE_AUTHOR("Texas Instruments");
  484. MODULE_LICENSE("GPL");