pwm-tiecap.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ECAP PWM driver
  4. *
  5. * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
  6. */
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/io.h>
  10. #include <linux/err.h>
  11. #include <linux/clk.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/pwm.h>
  14. #include <linux/of_device.h>
  15. /* ECAP registers and bits definitions */
  16. #define CAP1 0x08
  17. #define CAP2 0x0C
  18. #define CAP3 0x10
  19. #define CAP4 0x14
  20. #define ECCTL2 0x2A
  21. #define ECCTL2_APWM_POL_LOW BIT(10)
  22. #define ECCTL2_APWM_MODE BIT(9)
  23. #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
  24. #define ECCTL2_TSCTR_FREERUN BIT(4)
  25. struct ecap_context {
  26. u32 cap3;
  27. u32 cap4;
  28. u16 ecctl2;
  29. };
  30. struct ecap_pwm_chip {
  31. struct pwm_chip chip;
  32. unsigned int clk_rate;
  33. void __iomem *mmio_base;
  34. struct ecap_context ctx;
  35. };
  36. static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
  37. {
  38. return container_of(chip, struct ecap_pwm_chip, chip);
  39. }
  40. /*
  41. * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
  42. * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
  43. */
  44. static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  45. int duty_ns, int period_ns)
  46. {
  47. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  48. u32 period_cycles, duty_cycles;
  49. unsigned long long c;
  50. u16 value;
  51. if (period_ns > NSEC_PER_SEC)
  52. return -ERANGE;
  53. c = pc->clk_rate;
  54. c = c * period_ns;
  55. do_div(c, NSEC_PER_SEC);
  56. period_cycles = (u32)c;
  57. if (period_cycles < 1) {
  58. period_cycles = 1;
  59. duty_cycles = 1;
  60. } else {
  61. c = pc->clk_rate;
  62. c = c * duty_ns;
  63. do_div(c, NSEC_PER_SEC);
  64. duty_cycles = (u32)c;
  65. }
  66. pm_runtime_get_sync(pc->chip.dev);
  67. value = readw(pc->mmio_base + ECCTL2);
  68. /* Configure APWM mode & disable sync option */
  69. value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
  70. writew(value, pc->mmio_base + ECCTL2);
  71. if (!pwm_is_enabled(pwm)) {
  72. /* Update active registers if not running */
  73. writel(duty_cycles, pc->mmio_base + CAP2);
  74. writel(period_cycles, pc->mmio_base + CAP1);
  75. } else {
  76. /*
  77. * Update shadow registers to configure period and
  78. * compare values. This helps current PWM period to
  79. * complete on reconfiguring
  80. */
  81. writel(duty_cycles, pc->mmio_base + CAP4);
  82. writel(period_cycles, pc->mmio_base + CAP3);
  83. }
  84. if (!pwm_is_enabled(pwm)) {
  85. value = readw(pc->mmio_base + ECCTL2);
  86. /* Disable APWM mode to put APWM output Low */
  87. value &= ~ECCTL2_APWM_MODE;
  88. writew(value, pc->mmio_base + ECCTL2);
  89. }
  90. pm_runtime_put_sync(pc->chip.dev);
  91. return 0;
  92. }
  93. static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
  94. enum pwm_polarity polarity)
  95. {
  96. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  97. u16 value;
  98. pm_runtime_get_sync(pc->chip.dev);
  99. value = readw(pc->mmio_base + ECCTL2);
  100. if (polarity == PWM_POLARITY_INVERSED)
  101. /* Duty cycle defines LOW period of PWM */
  102. value |= ECCTL2_APWM_POL_LOW;
  103. else
  104. /* Duty cycle defines HIGH period of PWM */
  105. value &= ~ECCTL2_APWM_POL_LOW;
  106. writew(value, pc->mmio_base + ECCTL2);
  107. pm_runtime_put_sync(pc->chip.dev);
  108. return 0;
  109. }
  110. static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  111. {
  112. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  113. u16 value;
  114. /* Leave clock enabled on enabling PWM */
  115. pm_runtime_get_sync(pc->chip.dev);
  116. /*
  117. * Enable 'Free run Time stamp counter mode' to start counter
  118. * and 'APWM mode' to enable APWM output
  119. */
  120. value = readw(pc->mmio_base + ECCTL2);
  121. value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
  122. writew(value, pc->mmio_base + ECCTL2);
  123. return 0;
  124. }
  125. static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  126. {
  127. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  128. u16 value;
  129. /*
  130. * Disable 'Free run Time stamp counter mode' to stop counter
  131. * and 'APWM mode' to put APWM output to low
  132. */
  133. value = readw(pc->mmio_base + ECCTL2);
  134. value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
  135. writew(value, pc->mmio_base + ECCTL2);
  136. /* Disable clock on PWM disable */
  137. pm_runtime_put_sync(pc->chip.dev);
  138. }
  139. static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  140. {
  141. if (pwm_is_enabled(pwm)) {
  142. dev_warn(chip->dev, "Removing PWM device without disabling\n");
  143. pm_runtime_put_sync(chip->dev);
  144. }
  145. }
  146. static const struct pwm_ops ecap_pwm_ops = {
  147. .free = ecap_pwm_free,
  148. .config = ecap_pwm_config,
  149. .set_polarity = ecap_pwm_set_polarity,
  150. .enable = ecap_pwm_enable,
  151. .disable = ecap_pwm_disable,
  152. .owner = THIS_MODULE,
  153. };
  154. static const struct of_device_id ecap_of_match[] = {
  155. { .compatible = "ti,am3352-ecap" },
  156. { .compatible = "ti,am33xx-ecap" },
  157. {},
  158. };
  159. MODULE_DEVICE_TABLE(of, ecap_of_match);
  160. static int ecap_pwm_probe(struct platform_device *pdev)
  161. {
  162. struct device_node *np = pdev->dev.of_node;
  163. struct ecap_pwm_chip *pc;
  164. struct resource *r;
  165. struct clk *clk;
  166. int ret;
  167. pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
  168. if (!pc)
  169. return -ENOMEM;
  170. clk = devm_clk_get(&pdev->dev, "fck");
  171. if (IS_ERR(clk)) {
  172. if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
  173. dev_warn(&pdev->dev, "Binding is obsolete.\n");
  174. clk = devm_clk_get(pdev->dev.parent, "fck");
  175. }
  176. }
  177. if (IS_ERR(clk)) {
  178. dev_err(&pdev->dev, "failed to get clock\n");
  179. return PTR_ERR(clk);
  180. }
  181. pc->clk_rate = clk_get_rate(clk);
  182. if (!pc->clk_rate) {
  183. dev_err(&pdev->dev, "failed to get clock rate\n");
  184. return -EINVAL;
  185. }
  186. pc->chip.dev = &pdev->dev;
  187. pc->chip.ops = &ecap_pwm_ops;
  188. pc->chip.of_xlate = of_pwm_xlate_with_flags;
  189. pc->chip.of_pwm_n_cells = 3;
  190. pc->chip.base = -1;
  191. pc->chip.npwm = 1;
  192. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  193. pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
  194. if (IS_ERR(pc->mmio_base))
  195. return PTR_ERR(pc->mmio_base);
  196. ret = pwmchip_add(&pc->chip);
  197. if (ret < 0) {
  198. dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
  199. return ret;
  200. }
  201. platform_set_drvdata(pdev, pc);
  202. pm_runtime_enable(&pdev->dev);
  203. return 0;
  204. }
  205. static int ecap_pwm_remove(struct platform_device *pdev)
  206. {
  207. struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
  208. pm_runtime_disable(&pdev->dev);
  209. return pwmchip_remove(&pc->chip);
  210. }
  211. #ifdef CONFIG_PM_SLEEP
  212. static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
  213. {
  214. pm_runtime_get_sync(pc->chip.dev);
  215. pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
  216. pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
  217. pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
  218. pm_runtime_put_sync(pc->chip.dev);
  219. }
  220. static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
  221. {
  222. writel(pc->ctx.cap3, pc->mmio_base + CAP3);
  223. writel(pc->ctx.cap4, pc->mmio_base + CAP4);
  224. writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
  225. }
  226. static int ecap_pwm_suspend(struct device *dev)
  227. {
  228. struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
  229. struct pwm_device *pwm = pc->chip.pwms;
  230. ecap_pwm_save_context(pc);
  231. /* Disable explicitly if PWM is running */
  232. if (pwm_is_enabled(pwm))
  233. pm_runtime_put_sync(dev);
  234. return 0;
  235. }
  236. static int ecap_pwm_resume(struct device *dev)
  237. {
  238. struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
  239. struct pwm_device *pwm = pc->chip.pwms;
  240. /* Enable explicitly if PWM was running */
  241. if (pwm_is_enabled(pwm))
  242. pm_runtime_get_sync(dev);
  243. ecap_pwm_restore_context(pc);
  244. return 0;
  245. }
  246. #endif
  247. static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
  248. static struct platform_driver ecap_pwm_driver = {
  249. .driver = {
  250. .name = "ecap",
  251. .of_match_table = ecap_of_match,
  252. .pm = &ecap_pwm_pm_ops,
  253. },
  254. .probe = ecap_pwm_probe,
  255. .remove = ecap_pwm_remove,
  256. };
  257. module_platform_driver(ecap_pwm_driver);
  258. MODULE_DESCRIPTION("ECAP PWM driver");
  259. MODULE_AUTHOR("Texas Instruments");
  260. MODULE_LICENSE("GPL");