pwm-stm32-lp.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * STM32 Low-Power Timer PWM driver
  4. *
  5. * Copyright (C) STMicroelectronics 2017
  6. *
  7. * Author: Gerald Baeza <gerald.baeza@st.com>
  8. *
  9. * Inspired by Gerald Baeza's pwm-stm32 driver
  10. */
  11. #include <linux/bitfield.h>
  12. #include <linux/mfd/stm32-lptimer.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/pinctrl/consumer.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pwm.h>
  18. struct stm32_pwm_lp {
  19. struct pwm_chip chip;
  20. struct clk *clk;
  21. struct regmap *regmap;
  22. };
  23. static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip)
  24. {
  25. return container_of(chip, struct stm32_pwm_lp, chip);
  26. }
  27. /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
  28. #define STM32_LPTIM_MAX_PRESCALER 128
  29. static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  30. const struct pwm_state *state)
  31. {
  32. struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
  33. unsigned long long prd, div, dty;
  34. struct pwm_state cstate;
  35. u32 val, mask, cfgr, presc = 0;
  36. bool reenable;
  37. int ret;
  38. pwm_get_state(pwm, &cstate);
  39. reenable = !cstate.enabled;
  40. if (!state->enabled) {
  41. if (cstate.enabled) {
  42. /* Disable LP timer */
  43. ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
  44. if (ret)
  45. return ret;
  46. /* disable clock to PWM counter */
  47. clk_disable(priv->clk);
  48. }
  49. return 0;
  50. }
  51. /* Calculate the period and prescaler value */
  52. div = (unsigned long long)clk_get_rate(priv->clk) * state->period;
  53. do_div(div, NSEC_PER_SEC);
  54. if (!div) {
  55. /* Clock is too slow to achieve requested period. */
  56. dev_dbg(priv->chip.dev, "Can't reach %llu ns\n", state->period);
  57. return -EINVAL;
  58. }
  59. prd = div;
  60. while (div > STM32_LPTIM_MAX_ARR) {
  61. presc++;
  62. if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) {
  63. dev_err(priv->chip.dev, "max prescaler exceeded\n");
  64. return -EINVAL;
  65. }
  66. div = prd >> presc;
  67. }
  68. prd = div;
  69. /* Calculate the duty cycle */
  70. dty = prd * state->duty_cycle;
  71. do_div(dty, state->period);
  72. if (!cstate.enabled) {
  73. /* enable clock to drive PWM counter */
  74. ret = clk_enable(priv->clk);
  75. if (ret)
  76. return ret;
  77. }
  78. ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr);
  79. if (ret)
  80. goto err;
  81. if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) ||
  82. (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) {
  83. val = FIELD_PREP(STM32_LPTIM_PRESC, presc);
  84. val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity);
  85. mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL;
  86. /* Must disable LP timer to modify CFGR */
  87. reenable = true;
  88. ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
  89. if (ret)
  90. goto err;
  91. ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask,
  92. val);
  93. if (ret)
  94. goto err;
  95. }
  96. if (reenable) {
  97. /* Must (re)enable LP timer to modify CMP & ARR */
  98. ret = regmap_write(priv->regmap, STM32_LPTIM_CR,
  99. STM32_LPTIM_ENABLE);
  100. if (ret)
  101. goto err;
  102. }
  103. ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, prd - 1);
  104. if (ret)
  105. goto err;
  106. ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty));
  107. if (ret)
  108. goto err;
  109. /* ensure CMP & ARR registers are properly written */
  110. ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
  111. (val & STM32_LPTIM_CMPOK_ARROK),
  112. 100, 1000);
  113. if (ret) {
  114. dev_err(priv->chip.dev, "ARR/CMP registers write issue\n");
  115. goto err;
  116. }
  117. ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
  118. STM32_LPTIM_CMPOKCF_ARROKCF);
  119. if (ret)
  120. goto err;
  121. if (reenable) {
  122. /* Start LP timer in continuous mode */
  123. ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
  124. STM32_LPTIM_CNTSTRT,
  125. STM32_LPTIM_CNTSTRT);
  126. if (ret) {
  127. regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
  128. goto err;
  129. }
  130. }
  131. return 0;
  132. err:
  133. if (!cstate.enabled)
  134. clk_disable(priv->clk);
  135. return ret;
  136. }
  137. static void stm32_pwm_lp_get_state(struct pwm_chip *chip,
  138. struct pwm_device *pwm,
  139. struct pwm_state *state)
  140. {
  141. struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
  142. unsigned long rate = clk_get_rate(priv->clk);
  143. u32 val, presc, prd;
  144. u64 tmp;
  145. regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
  146. state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val);
  147. /* Keep PWM counter clock refcount in sync with PWM initial state */
  148. if (state->enabled)
  149. clk_enable(priv->clk);
  150. regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val);
  151. presc = FIELD_GET(STM32_LPTIM_PRESC, val);
  152. state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val);
  153. regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd);
  154. tmp = prd + 1;
  155. tmp = (tmp << presc) * NSEC_PER_SEC;
  156. state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
  157. regmap_read(priv->regmap, STM32_LPTIM_CMP, &val);
  158. tmp = prd - val;
  159. tmp = (tmp << presc) * NSEC_PER_SEC;
  160. state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
  161. }
  162. static const struct pwm_ops stm32_pwm_lp_ops = {
  163. .owner = THIS_MODULE,
  164. .apply = stm32_pwm_lp_apply,
  165. .get_state = stm32_pwm_lp_get_state,
  166. };
  167. static int stm32_pwm_lp_probe(struct platform_device *pdev)
  168. {
  169. struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
  170. struct stm32_pwm_lp *priv;
  171. int ret;
  172. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  173. if (!priv)
  174. return -ENOMEM;
  175. priv->regmap = ddata->regmap;
  176. priv->clk = ddata->clk;
  177. priv->chip.base = -1;
  178. priv->chip.dev = &pdev->dev;
  179. priv->chip.ops = &stm32_pwm_lp_ops;
  180. priv->chip.npwm = 1;
  181. priv->chip.of_xlate = of_pwm_xlate_with_flags;
  182. priv->chip.of_pwm_n_cells = 3;
  183. ret = pwmchip_add(&priv->chip);
  184. if (ret < 0)
  185. return ret;
  186. platform_set_drvdata(pdev, priv);
  187. return 0;
  188. }
  189. static int stm32_pwm_lp_remove(struct platform_device *pdev)
  190. {
  191. struct stm32_pwm_lp *priv = platform_get_drvdata(pdev);
  192. return pwmchip_remove(&priv->chip);
  193. }
  194. static int __maybe_unused stm32_pwm_lp_suspend(struct device *dev)
  195. {
  196. struct stm32_pwm_lp *priv = dev_get_drvdata(dev);
  197. struct pwm_state state;
  198. pwm_get_state(&priv->chip.pwms[0], &state);
  199. if (state.enabled) {
  200. dev_err(dev, "The consumer didn't stop us (%s)\n",
  201. priv->chip.pwms[0].label);
  202. return -EBUSY;
  203. }
  204. return pinctrl_pm_select_sleep_state(dev);
  205. }
  206. static int __maybe_unused stm32_pwm_lp_resume(struct device *dev)
  207. {
  208. return pinctrl_pm_select_default_state(dev);
  209. }
  210. static SIMPLE_DEV_PM_OPS(stm32_pwm_lp_pm_ops, stm32_pwm_lp_suspend,
  211. stm32_pwm_lp_resume);
  212. static const struct of_device_id stm32_pwm_lp_of_match[] = {
  213. { .compatible = "st,stm32-pwm-lp", },
  214. {},
  215. };
  216. MODULE_DEVICE_TABLE(of, stm32_pwm_lp_of_match);
  217. static struct platform_driver stm32_pwm_lp_driver = {
  218. .probe = stm32_pwm_lp_probe,
  219. .remove = stm32_pwm_lp_remove,
  220. .driver = {
  221. .name = "stm32-pwm-lp",
  222. .of_match_table = of_match_ptr(stm32_pwm_lp_of_match),
  223. .pm = &stm32_pwm_lp_pm_ops,
  224. },
  225. };
  226. module_platform_driver(stm32_pwm_lp_driver);
  227. MODULE_ALIAS("platform:stm32-pwm-lp");
  228. MODULE_DESCRIPTION("STMicroelectronics STM32 PWM LP driver");
  229. MODULE_LICENSE("GPL v2");