pwm-sti.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * PWM device driver for ST SoCs
  4. *
  5. * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
  6. *
  7. * Author: Ajit Pal Singh <ajitpal.singh@st.com>
  8. * Lee Jones <lee.jones@linaro.org>
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/math64.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pwm.h>
  18. #include <linux/regmap.h>
  19. #include <linux/sched.h>
  20. #include <linux/slab.h>
  21. #include <linux/time.h>
  22. #include <linux/wait.h>
  23. #define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Device's Duty Cycle register */
  24. #define PWM_CPT_VAL(x) (0x10 + (4 * (x))) /* Capture value */
  25. #define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */
  26. #define STI_PWM_CTRL 0x50 /* Control/Config register */
  27. #define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */
  28. #define STI_INT_STA 0x58 /* Interrupt Status register */
  29. #define PWM_INT_ACK 0x5c
  30. #define PWM_PRESCALE_LOW_MASK 0x0f
  31. #define PWM_PRESCALE_HIGH_MASK 0xf0
  32. #define PWM_CPT_EDGE_MASK 0x03
  33. #define PWM_INT_ACK_MASK 0x1ff
  34. #define STI_MAX_CPT_DEVS 4
  35. #define CPT_DC_MAX 0xff
  36. /* Regfield IDs */
  37. enum {
  38. /* Bits in PWM_CTRL*/
  39. PWMCLK_PRESCALE_LOW,
  40. PWMCLK_PRESCALE_HIGH,
  41. CPTCLK_PRESCALE,
  42. PWM_OUT_EN,
  43. PWM_CPT_EN,
  44. PWM_CPT_INT_EN,
  45. PWM_CPT_INT_STAT,
  46. /* Keep last */
  47. MAX_REGFIELDS
  48. };
  49. /*
  50. * Each capture input can be programmed to detect rising-edge, falling-edge,
  51. * either edge or neither egde.
  52. */
  53. enum sti_cpt_edge {
  54. CPT_EDGE_DISABLED,
  55. CPT_EDGE_RISING,
  56. CPT_EDGE_FALLING,
  57. CPT_EDGE_BOTH,
  58. };
  59. struct sti_cpt_ddata {
  60. u32 snapshot[3];
  61. unsigned int index;
  62. struct mutex lock;
  63. wait_queue_head_t wait;
  64. };
  65. struct sti_pwm_compat_data {
  66. const struct reg_field *reg_fields;
  67. unsigned int pwm_num_devs;
  68. unsigned int cpt_num_devs;
  69. unsigned int max_pwm_cnt;
  70. unsigned int max_prescale;
  71. };
  72. struct sti_pwm_chip {
  73. struct device *dev;
  74. struct clk *pwm_clk;
  75. struct clk *cpt_clk;
  76. struct regmap *regmap;
  77. struct sti_pwm_compat_data *cdata;
  78. struct regmap_field *prescale_low;
  79. struct regmap_field *prescale_high;
  80. struct regmap_field *pwm_out_en;
  81. struct regmap_field *pwm_cpt_en;
  82. struct regmap_field *pwm_cpt_int_en;
  83. struct regmap_field *pwm_cpt_int_stat;
  84. struct pwm_chip chip;
  85. struct pwm_device *cur;
  86. unsigned long configured;
  87. unsigned int en_count;
  88. struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
  89. void __iomem *mmio;
  90. };
  91. static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
  92. [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3),
  93. [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14),
  94. [CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8),
  95. [PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9),
  96. [PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10),
  97. [PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4),
  98. [PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4),
  99. };
  100. static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)
  101. {
  102. return container_of(chip, struct sti_pwm_chip, chip);
  103. }
  104. /*
  105. * Calculate the prescaler value corresponding to the period.
  106. */
  107. static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
  108. unsigned int *prescale)
  109. {
  110. struct sti_pwm_compat_data *cdata = pc->cdata;
  111. unsigned long clk_rate;
  112. unsigned long value;
  113. unsigned int ps;
  114. clk_rate = clk_get_rate(pc->pwm_clk);
  115. if (!clk_rate) {
  116. dev_err(pc->dev, "failed to get clock rate\n");
  117. return -EINVAL;
  118. }
  119. /*
  120. * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1
  121. */
  122. value = NSEC_PER_SEC / clk_rate;
  123. value *= cdata->max_pwm_cnt + 1;
  124. if (period % value)
  125. return -EINVAL;
  126. ps = period / value - 1;
  127. if (ps > cdata->max_prescale)
  128. return -EINVAL;
  129. *prescale = ps;
  130. return 0;
  131. }
  132. /*
  133. * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. The
  134. * only way to change the period (apart from changing the PWM input clock) is
  135. * to change the PWM clock prescaler.
  136. *
  137. * The prescaler is of 8 bits, so 256 prescaler values and hence 256 possible
  138. * period values are supported (for a particular clock rate). The requested
  139. * period will be applied only if it matches one of these 256 values.
  140. */
  141. static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  142. int duty_ns, int period_ns)
  143. {
  144. struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
  145. struct sti_pwm_compat_data *cdata = pc->cdata;
  146. unsigned int ncfg, value, prescale = 0;
  147. struct pwm_device *cur = pc->cur;
  148. struct device *dev = pc->dev;
  149. bool period_same = false;
  150. int ret;
  151. ncfg = hweight_long(pc->configured);
  152. if (ncfg)
  153. period_same = (period_ns == pwm_get_period(cur));
  154. /*
  155. * Allow configuration changes if one of the following conditions
  156. * satisfy.
  157. * 1. No devices have been configured.
  158. * 2. Only one device has been configured and the new request is for
  159. * the same device.
  160. * 3. Only one device has been configured and the new request is for
  161. * a new device and period of the new device is same as the current
  162. * configured period.
  163. * 4. More than one devices are configured and period of the new
  164. * requestis the same as the current period.
  165. */
  166. if (!ncfg ||
  167. ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) ||
  168. ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) ||
  169. ((ncfg > 1) && period_same)) {
  170. /* Enable clock before writing to PWM registers. */
  171. ret = clk_enable(pc->pwm_clk);
  172. if (ret)
  173. return ret;
  174. ret = clk_enable(pc->cpt_clk);
  175. if (ret)
  176. return ret;
  177. if (!period_same) {
  178. ret = sti_pwm_get_prescale(pc, period_ns, &prescale);
  179. if (ret)
  180. goto clk_dis;
  181. value = prescale & PWM_PRESCALE_LOW_MASK;
  182. ret = regmap_field_write(pc->prescale_low, value);
  183. if (ret)
  184. goto clk_dis;
  185. value = (prescale & PWM_PRESCALE_HIGH_MASK) >> 4;
  186. ret = regmap_field_write(pc->prescale_high, value);
  187. if (ret)
  188. goto clk_dis;
  189. }
  190. /*
  191. * When PWMVal == 0, PWM pulse = 1 local clock cycle.
  192. * When PWMVal == max_pwm_count,
  193. * PWM pulse = (max_pwm_count + 1) local cycles,
  194. * that is continuous pulse: signal never goes low.
  195. */
  196. value = cdata->max_pwm_cnt * duty_ns / period_ns;
  197. ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value);
  198. if (ret)
  199. goto clk_dis;
  200. ret = regmap_field_write(pc->pwm_cpt_int_en, 0);
  201. set_bit(pwm->hwpwm, &pc->configured);
  202. pc->cur = pwm;
  203. dev_dbg(dev, "prescale:%u, period:%i, duty:%i, value:%u\n",
  204. prescale, period_ns, duty_ns, value);
  205. } else {
  206. return -EINVAL;
  207. }
  208. clk_dis:
  209. clk_disable(pc->pwm_clk);
  210. clk_disable(pc->cpt_clk);
  211. return ret;
  212. }
  213. static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  214. {
  215. struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
  216. struct device *dev = pc->dev;
  217. int ret = 0;
  218. /*
  219. * Since we have a common enable for all PWM devices, do not enable if
  220. * already enabled.
  221. */
  222. mutex_lock(&pc->sti_pwm_lock);
  223. if (!pc->en_count) {
  224. ret = clk_enable(pc->pwm_clk);
  225. if (ret)
  226. goto out;
  227. ret = clk_enable(pc->cpt_clk);
  228. if (ret)
  229. goto out;
  230. ret = regmap_field_write(pc->pwm_out_en, 1);
  231. if (ret) {
  232. dev_err(dev, "failed to enable PWM device %u: %d\n",
  233. pwm->hwpwm, ret);
  234. goto out;
  235. }
  236. }
  237. pc->en_count++;
  238. out:
  239. mutex_unlock(&pc->sti_pwm_lock);
  240. return ret;
  241. }
  242. static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  243. {
  244. struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
  245. mutex_lock(&pc->sti_pwm_lock);
  246. if (--pc->en_count) {
  247. mutex_unlock(&pc->sti_pwm_lock);
  248. return;
  249. }
  250. regmap_field_write(pc->pwm_out_en, 0);
  251. clk_disable(pc->pwm_clk);
  252. clk_disable(pc->cpt_clk);
  253. mutex_unlock(&pc->sti_pwm_lock);
  254. }
  255. static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  256. {
  257. struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
  258. clear_bit(pwm->hwpwm, &pc->configured);
  259. }
  260. static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
  261. struct pwm_capture *result, unsigned long timeout)
  262. {
  263. struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
  264. struct sti_pwm_compat_data *cdata = pc->cdata;
  265. struct sti_cpt_ddata *ddata = pwm_get_chip_data(pwm);
  266. struct device *dev = pc->dev;
  267. unsigned int effective_ticks;
  268. unsigned long long high, low;
  269. int ret;
  270. if (pwm->hwpwm >= cdata->cpt_num_devs) {
  271. dev_err(dev, "device %u is not valid\n", pwm->hwpwm);
  272. return -EINVAL;
  273. }
  274. mutex_lock(&ddata->lock);
  275. ddata->index = 0;
  276. /* Prepare capture measurement */
  277. regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING);
  278. regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm));
  279. /* Enable capture */
  280. ret = regmap_field_write(pc->pwm_cpt_en, 1);
  281. if (ret) {
  282. dev_err(dev, "failed to enable PWM capture %u: %d\n",
  283. pwm->hwpwm, ret);
  284. goto out;
  285. }
  286. ret = wait_event_interruptible_timeout(ddata->wait, ddata->index > 1,
  287. msecs_to_jiffies(timeout));
  288. regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_DISABLED);
  289. if (ret == -ERESTARTSYS)
  290. goto out;
  291. switch (ddata->index) {
  292. case 0:
  293. case 1:
  294. /*
  295. * Getting here could mean:
  296. * - input signal is constant of less than 1 Hz
  297. * - there is no input signal at all
  298. *
  299. * In such case the frequency is rounded down to 0
  300. */
  301. result->period = 0;
  302. result->duty_cycle = 0;
  303. break;
  304. case 2:
  305. /* We have everying we need */
  306. high = ddata->snapshot[1] - ddata->snapshot[0];
  307. low = ddata->snapshot[2] - ddata->snapshot[1];
  308. effective_ticks = clk_get_rate(pc->cpt_clk);
  309. result->period = (high + low) * NSEC_PER_SEC;
  310. result->period /= effective_ticks;
  311. result->duty_cycle = high * NSEC_PER_SEC;
  312. result->duty_cycle /= effective_ticks;
  313. break;
  314. default:
  315. dev_err(dev, "internal error\n");
  316. break;
  317. }
  318. out:
  319. /* Disable capture */
  320. regmap_field_write(pc->pwm_cpt_en, 0);
  321. mutex_unlock(&ddata->lock);
  322. return ret;
  323. }
  324. static const struct pwm_ops sti_pwm_ops = {
  325. .capture = sti_pwm_capture,
  326. .config = sti_pwm_config,
  327. .enable = sti_pwm_enable,
  328. .disable = sti_pwm_disable,
  329. .free = sti_pwm_free,
  330. .owner = THIS_MODULE,
  331. };
  332. static irqreturn_t sti_pwm_interrupt(int irq, void *data)
  333. {
  334. struct sti_pwm_chip *pc = data;
  335. struct device *dev = pc->dev;
  336. struct sti_cpt_ddata *ddata;
  337. int devicenum;
  338. unsigned int cpt_int_stat;
  339. unsigned int reg;
  340. int ret = IRQ_NONE;
  341. ret = regmap_field_read(pc->pwm_cpt_int_stat, &cpt_int_stat);
  342. if (ret)
  343. return ret;
  344. while (cpt_int_stat) {
  345. devicenum = ffs(cpt_int_stat) - 1;
  346. ddata = pwm_get_chip_data(&pc->chip.pwms[devicenum]);
  347. /*
  348. * Capture input:
  349. * _______ _______
  350. * | | | |
  351. * __| |_________________| |________
  352. * ^0 ^1 ^2
  353. *
  354. * Capture start by the first available rising edge. When a
  355. * capture event occurs, capture value (CPT_VALx) is stored,
  356. * index incremented, capture edge changed.
  357. *
  358. * After the capture, if the index > 1, we have collected the
  359. * necessary data so we signal the thread waiting for it and
  360. * disable the capture by setting capture edge to none
  361. */
  362. regmap_read(pc->regmap,
  363. PWM_CPT_VAL(devicenum),
  364. &ddata->snapshot[ddata->index]);
  365. switch (ddata->index) {
  366. case 0:
  367. case 1:
  368. regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), &reg);
  369. reg ^= PWM_CPT_EDGE_MASK;
  370. regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg);
  371. ddata->index++;
  372. break;
  373. case 2:
  374. regmap_write(pc->regmap,
  375. PWM_CPT_EDGE(devicenum),
  376. CPT_EDGE_DISABLED);
  377. wake_up(&ddata->wait);
  378. break;
  379. default:
  380. dev_err(dev, "Internal error\n");
  381. }
  382. cpt_int_stat &= ~BIT_MASK(devicenum);
  383. ret = IRQ_HANDLED;
  384. }
  385. /* Just ACK everything */
  386. regmap_write(pc->regmap, PWM_INT_ACK, PWM_INT_ACK_MASK);
  387. return ret;
  388. }
  389. static int sti_pwm_probe_dt(struct sti_pwm_chip *pc)
  390. {
  391. struct device *dev = pc->dev;
  392. const struct reg_field *reg_fields;
  393. struct device_node *np = dev->of_node;
  394. struct sti_pwm_compat_data *cdata = pc->cdata;
  395. u32 num_devs;
  396. int ret;
  397. ret = of_property_read_u32(np, "st,pwm-num-chan", &num_devs);
  398. if (!ret)
  399. cdata->pwm_num_devs = num_devs;
  400. ret = of_property_read_u32(np, "st,capture-num-chan", &num_devs);
  401. if (!ret)
  402. cdata->cpt_num_devs = num_devs;
  403. if (!cdata->pwm_num_devs && !cdata->cpt_num_devs) {
  404. dev_err(dev, "No channels configured\n");
  405. return -EINVAL;
  406. }
  407. reg_fields = cdata->reg_fields;
  408. pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap,
  409. reg_fields[PWMCLK_PRESCALE_LOW]);
  410. if (IS_ERR(pc->prescale_low))
  411. return PTR_ERR(pc->prescale_low);
  412. pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap,
  413. reg_fields[PWMCLK_PRESCALE_HIGH]);
  414. if (IS_ERR(pc->prescale_high))
  415. return PTR_ERR(pc->prescale_high);
  416. pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap,
  417. reg_fields[PWM_OUT_EN]);
  418. if (IS_ERR(pc->pwm_out_en))
  419. return PTR_ERR(pc->pwm_out_en);
  420. pc->pwm_cpt_en = devm_regmap_field_alloc(dev, pc->regmap,
  421. reg_fields[PWM_CPT_EN]);
  422. if (IS_ERR(pc->pwm_cpt_en))
  423. return PTR_ERR(pc->pwm_cpt_en);
  424. pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap,
  425. reg_fields[PWM_CPT_INT_EN]);
  426. if (IS_ERR(pc->pwm_cpt_int_en))
  427. return PTR_ERR(pc->pwm_cpt_int_en);
  428. pc->pwm_cpt_int_stat = devm_regmap_field_alloc(dev, pc->regmap,
  429. reg_fields[PWM_CPT_INT_STAT]);
  430. if (PTR_ERR_OR_ZERO(pc->pwm_cpt_int_stat))
  431. return PTR_ERR(pc->pwm_cpt_int_stat);
  432. return 0;
  433. }
  434. static const struct regmap_config sti_pwm_regmap_config = {
  435. .reg_bits = 32,
  436. .val_bits = 32,
  437. .reg_stride = 4,
  438. };
  439. static int sti_pwm_probe(struct platform_device *pdev)
  440. {
  441. struct device *dev = &pdev->dev;
  442. struct sti_pwm_compat_data *cdata;
  443. struct sti_pwm_chip *pc;
  444. struct resource *res;
  445. unsigned int i;
  446. int irq, ret;
  447. pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
  448. if (!pc)
  449. return -ENOMEM;
  450. cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL);
  451. if (!cdata)
  452. return -ENOMEM;
  453. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  454. pc->mmio = devm_ioremap_resource(dev, res);
  455. if (IS_ERR(pc->mmio))
  456. return PTR_ERR(pc->mmio);
  457. pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
  458. &sti_pwm_regmap_config);
  459. if (IS_ERR(pc->regmap))
  460. return PTR_ERR(pc->regmap);
  461. irq = platform_get_irq(pdev, 0);
  462. if (irq < 0)
  463. return irq;
  464. ret = devm_request_irq(&pdev->dev, irq, sti_pwm_interrupt, 0,
  465. pdev->name, pc);
  466. if (ret < 0) {
  467. dev_err(&pdev->dev, "Failed to request IRQ\n");
  468. return ret;
  469. }
  470. /*
  471. * Setup PWM data with default values: some values could be replaced
  472. * with specific ones provided from Device Tree.
  473. */
  474. cdata->reg_fields = sti_pwm_regfields;
  475. cdata->max_prescale = 0xff;
  476. cdata->max_pwm_cnt = 255;
  477. cdata->pwm_num_devs = 0;
  478. cdata->cpt_num_devs = 0;
  479. pc->cdata = cdata;
  480. pc->dev = dev;
  481. pc->en_count = 0;
  482. mutex_init(&pc->sti_pwm_lock);
  483. ret = sti_pwm_probe_dt(pc);
  484. if (ret)
  485. return ret;
  486. if (!cdata->pwm_num_devs)
  487. goto skip_pwm;
  488. pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm");
  489. if (IS_ERR(pc->pwm_clk)) {
  490. dev_err(dev, "failed to get PWM clock\n");
  491. return PTR_ERR(pc->pwm_clk);
  492. }
  493. ret = clk_prepare(pc->pwm_clk);
  494. if (ret) {
  495. dev_err(dev, "failed to prepare clock\n");
  496. return ret;
  497. }
  498. skip_pwm:
  499. if (!cdata->cpt_num_devs)
  500. goto skip_cpt;
  501. pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture");
  502. if (IS_ERR(pc->cpt_clk)) {
  503. dev_err(dev, "failed to get PWM capture clock\n");
  504. return PTR_ERR(pc->cpt_clk);
  505. }
  506. ret = clk_prepare(pc->cpt_clk);
  507. if (ret) {
  508. dev_err(dev, "failed to prepare clock\n");
  509. return ret;
  510. }
  511. skip_cpt:
  512. pc->chip.dev = dev;
  513. pc->chip.ops = &sti_pwm_ops;
  514. pc->chip.base = -1;
  515. pc->chip.npwm = pc->cdata->pwm_num_devs;
  516. ret = pwmchip_add(&pc->chip);
  517. if (ret < 0) {
  518. clk_unprepare(pc->pwm_clk);
  519. clk_unprepare(pc->cpt_clk);
  520. return ret;
  521. }
  522. for (i = 0; i < cdata->cpt_num_devs; i++) {
  523. struct sti_cpt_ddata *ddata;
  524. ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
  525. if (!ddata)
  526. return -ENOMEM;
  527. init_waitqueue_head(&ddata->wait);
  528. mutex_init(&ddata->lock);
  529. pwm_set_chip_data(&pc->chip.pwms[i], ddata);
  530. }
  531. platform_set_drvdata(pdev, pc);
  532. return 0;
  533. }
  534. static int sti_pwm_remove(struct platform_device *pdev)
  535. {
  536. struct sti_pwm_chip *pc = platform_get_drvdata(pdev);
  537. unsigned int i;
  538. for (i = 0; i < pc->cdata->pwm_num_devs; i++)
  539. pwm_disable(&pc->chip.pwms[i]);
  540. clk_unprepare(pc->pwm_clk);
  541. clk_unprepare(pc->cpt_clk);
  542. return pwmchip_remove(&pc->chip);
  543. }
  544. static const struct of_device_id sti_pwm_of_match[] = {
  545. { .compatible = "st,sti-pwm", },
  546. { /* sentinel */ }
  547. };
  548. MODULE_DEVICE_TABLE(of, sti_pwm_of_match);
  549. static struct platform_driver sti_pwm_driver = {
  550. .driver = {
  551. .name = "sti-pwm",
  552. .of_match_table = sti_pwm_of_match,
  553. },
  554. .probe = sti_pwm_probe,
  555. .remove = sti_pwm_remove,
  556. };
  557. module_platform_driver(sti_pwm_driver);
  558. MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
  559. MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
  560. MODULE_LICENSE("GPL");