pwm-spear.c 6.4 KB

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  1. /*
  2. * ST Microelectronics SPEAr Pulse Width Modulator driver
  3. *
  4. * Copyright (C) 2012 ST Microelectronics
  5. * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/err.h>
  13. #include <linux/io.h>
  14. #include <linux/ioport.h>
  15. #include <linux/kernel.h>
  16. #include <linux/math64.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pwm.h>
  21. #include <linux/slab.h>
  22. #include <linux/types.h>
  23. #define NUM_PWM 4
  24. /* PWM registers and bits definitions */
  25. #define PWMCR 0x00 /* Control Register */
  26. #define PWMCR_PWM_ENABLE 0x1
  27. #define PWMCR_PRESCALE_SHIFT 2
  28. #define PWMCR_MIN_PRESCALE 0x00
  29. #define PWMCR_MAX_PRESCALE 0x3FFF
  30. #define PWMDCR 0x04 /* Duty Cycle Register */
  31. #define PWMDCR_MIN_DUTY 0x0001
  32. #define PWMDCR_MAX_DUTY 0xFFFF
  33. #define PWMPCR 0x08 /* Period Register */
  34. #define PWMPCR_MIN_PERIOD 0x0001
  35. #define PWMPCR_MAX_PERIOD 0xFFFF
  36. /* Following only available on 13xx SoCs */
  37. #define PWMMCR 0x3C /* Master Control Register */
  38. #define PWMMCR_PWM_ENABLE 0x1
  39. /**
  40. * struct spear_pwm_chip - struct representing pwm chip
  41. *
  42. * @mmio_base: base address of pwm chip
  43. * @clk: pointer to clk structure of pwm chip
  44. * @chip: linux pwm chip representation
  45. */
  46. struct spear_pwm_chip {
  47. void __iomem *mmio_base;
  48. struct clk *clk;
  49. struct pwm_chip chip;
  50. };
  51. static inline struct spear_pwm_chip *to_spear_pwm_chip(struct pwm_chip *chip)
  52. {
  53. return container_of(chip, struct spear_pwm_chip, chip);
  54. }
  55. static inline u32 spear_pwm_readl(struct spear_pwm_chip *chip, unsigned int num,
  56. unsigned long offset)
  57. {
  58. return readl_relaxed(chip->mmio_base + (num << 4) + offset);
  59. }
  60. static inline void spear_pwm_writel(struct spear_pwm_chip *chip,
  61. unsigned int num, unsigned long offset,
  62. unsigned long val)
  63. {
  64. writel_relaxed(val, chip->mmio_base + (num << 4) + offset);
  65. }
  66. static int spear_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  67. int duty_ns, int period_ns)
  68. {
  69. struct spear_pwm_chip *pc = to_spear_pwm_chip(chip);
  70. u64 val, div, clk_rate;
  71. unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
  72. int ret;
  73. /*
  74. * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
  75. * according to formulas described below:
  76. *
  77. * period_ns = 10^9 * (PRESCALE + 1) * PV / PWM_CLK_RATE
  78. * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
  79. *
  80. * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
  81. * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
  82. */
  83. clk_rate = clk_get_rate(pc->clk);
  84. while (1) {
  85. div = 1000000000;
  86. div *= 1 + prescale;
  87. val = clk_rate * period_ns;
  88. pv = div64_u64(val, div);
  89. val = clk_rate * duty_ns;
  90. dc = div64_u64(val, div);
  91. /* if duty_ns and period_ns are not achievable then return */
  92. if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
  93. return -EINVAL;
  94. /*
  95. * if pv and dc have crossed their upper limit, then increase
  96. * prescale and recalculate pv and dc.
  97. */
  98. if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
  99. if (++prescale > PWMCR_MAX_PRESCALE)
  100. return -EINVAL;
  101. continue;
  102. }
  103. break;
  104. }
  105. /*
  106. * NOTE: the clock to PWM has to be enabled first before writing to the
  107. * registers.
  108. */
  109. ret = clk_enable(pc->clk);
  110. if (ret)
  111. return ret;
  112. spear_pwm_writel(pc, pwm->hwpwm, PWMCR,
  113. prescale << PWMCR_PRESCALE_SHIFT);
  114. spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc);
  115. spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv);
  116. clk_disable(pc->clk);
  117. return 0;
  118. }
  119. static int spear_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  120. {
  121. struct spear_pwm_chip *pc = to_spear_pwm_chip(chip);
  122. int rc = 0;
  123. u32 val;
  124. rc = clk_enable(pc->clk);
  125. if (rc)
  126. return rc;
  127. val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR);
  128. val |= PWMCR_PWM_ENABLE;
  129. spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val);
  130. return 0;
  131. }
  132. static void spear_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  133. {
  134. struct spear_pwm_chip *pc = to_spear_pwm_chip(chip);
  135. u32 val;
  136. val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR);
  137. val &= ~PWMCR_PWM_ENABLE;
  138. spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val);
  139. clk_disable(pc->clk);
  140. }
  141. static const struct pwm_ops spear_pwm_ops = {
  142. .config = spear_pwm_config,
  143. .enable = spear_pwm_enable,
  144. .disable = spear_pwm_disable,
  145. .owner = THIS_MODULE,
  146. };
  147. static int spear_pwm_probe(struct platform_device *pdev)
  148. {
  149. struct device_node *np = pdev->dev.of_node;
  150. struct spear_pwm_chip *pc;
  151. struct resource *r;
  152. int ret;
  153. u32 val;
  154. pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
  155. if (!pc)
  156. return -ENOMEM;
  157. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  158. pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
  159. if (IS_ERR(pc->mmio_base))
  160. return PTR_ERR(pc->mmio_base);
  161. pc->clk = devm_clk_get(&pdev->dev, NULL);
  162. if (IS_ERR(pc->clk))
  163. return PTR_ERR(pc->clk);
  164. platform_set_drvdata(pdev, pc);
  165. pc->chip.dev = &pdev->dev;
  166. pc->chip.ops = &spear_pwm_ops;
  167. pc->chip.base = -1;
  168. pc->chip.npwm = NUM_PWM;
  169. ret = clk_prepare(pc->clk);
  170. if (ret)
  171. return ret;
  172. if (of_device_is_compatible(np, "st,spear1340-pwm")) {
  173. ret = clk_enable(pc->clk);
  174. if (ret) {
  175. clk_unprepare(pc->clk);
  176. return ret;
  177. }
  178. /*
  179. * Following enables PWM chip, channels would still be
  180. * enabled individually through their control register
  181. */
  182. val = readl_relaxed(pc->mmio_base + PWMMCR);
  183. val |= PWMMCR_PWM_ENABLE;
  184. writel_relaxed(val, pc->mmio_base + PWMMCR);
  185. clk_disable(pc->clk);
  186. }
  187. ret = pwmchip_add(&pc->chip);
  188. if (ret < 0) {
  189. clk_unprepare(pc->clk);
  190. dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
  191. }
  192. return ret;
  193. }
  194. static int spear_pwm_remove(struct platform_device *pdev)
  195. {
  196. struct spear_pwm_chip *pc = platform_get_drvdata(pdev);
  197. /* clk was prepared in probe, hence unprepare it here */
  198. clk_unprepare(pc->clk);
  199. return pwmchip_remove(&pc->chip);
  200. }
  201. static const struct of_device_id spear_pwm_of_match[] = {
  202. { .compatible = "st,spear320-pwm" },
  203. { .compatible = "st,spear1340-pwm" },
  204. { }
  205. };
  206. MODULE_DEVICE_TABLE(of, spear_pwm_of_match);
  207. static struct platform_driver spear_pwm_driver = {
  208. .driver = {
  209. .name = "spear-pwm",
  210. .of_match_table = spear_pwm_of_match,
  211. },
  212. .probe = spear_pwm_probe,
  213. .remove = spear_pwm_remove,
  214. };
  215. module_platform_driver(spear_pwm_driver);
  216. MODULE_LICENSE("GPL");
  217. MODULE_AUTHOR("Shiraz Hashim <shiraz.linux.kernel@gmail.com>");
  218. MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.com>");
  219. MODULE_ALIAS("platform:spear-pwm");