pwm-samsung.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2007 Ben Dooks
  4. * Copyright (c) 2008 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
  6. * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
  7. * Copyright (c) 2017 Samsung Electronics Co., Ltd.
  8. *
  9. * PWM driver for Samsung SoCs
  10. */
  11. #include <linux/bitops.h>
  12. #include <linux/clk.h>
  13. #include <linux/export.h>
  14. #include <linux/err.h>
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pwm.h>
  21. #include <linux/slab.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/time.h>
  24. /* For struct samsung_timer_variant and samsung_pwm_lock. */
  25. #include <clocksource/samsung_pwm.h>
  26. #define REG_TCFG0 0x00
  27. #define REG_TCFG1 0x04
  28. #define REG_TCON 0x08
  29. #define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
  30. #define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
  31. #define TCFG0_PRESCALER_MASK 0xff
  32. #define TCFG0_PRESCALER1_SHIFT 8
  33. #define TCFG1_MUX_MASK 0xf
  34. #define TCFG1_SHIFT(chan) (4 * (chan))
  35. /*
  36. * Each channel occupies 4 bits in TCON register, but there is a gap of 4
  37. * bits (one channel) after channel 0, so channels have different numbering
  38. * when accessing TCON register. See to_tcon_channel() function.
  39. *
  40. * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
  41. * in its set of bits is 2 as opposed to 3 for other channels.
  42. */
  43. #define TCON_START(chan) BIT(4 * (chan) + 0)
  44. #define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1)
  45. #define TCON_INVERT(chan) BIT(4 * (chan) + 2)
  46. #define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3)
  47. #define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2)
  48. #define TCON_AUTORELOAD(chan) \
  49. ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
  50. /**
  51. * struct samsung_pwm_channel - private data of PWM channel
  52. * @period_ns: current period in nanoseconds programmed to the hardware
  53. * @duty_ns: current duty time in nanoseconds programmed to the hardware
  54. * @tin_ns: time of one timer tick in nanoseconds with current timer rate
  55. */
  56. struct samsung_pwm_channel {
  57. u32 period_ns;
  58. u32 duty_ns;
  59. u32 tin_ns;
  60. };
  61. /**
  62. * struct samsung_pwm_chip - private data of PWM chip
  63. * @chip: generic PWM chip
  64. * @variant: local copy of hardware variant data
  65. * @inverter_mask: inverter status for all channels - one bit per channel
  66. * @disabled_mask: disabled status for all channels - one bit per channel
  67. * @base: base address of mapped PWM registers
  68. * @base_clk: base clock used to drive the timers
  69. * @tclk0: external clock 0 (can be ERR_PTR if not present)
  70. * @tclk1: external clock 1 (can be ERR_PTR if not present)
  71. */
  72. struct samsung_pwm_chip {
  73. struct pwm_chip chip;
  74. struct samsung_pwm_variant variant;
  75. u8 inverter_mask;
  76. u8 disabled_mask;
  77. void __iomem *base;
  78. struct clk *base_clk;
  79. struct clk *tclk0;
  80. struct clk *tclk1;
  81. };
  82. #ifndef CONFIG_CLKSRC_SAMSUNG_PWM
  83. /*
  84. * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
  85. * and some registers need access synchronization. If both drivers are
  86. * compiled in, the spinlock is defined in the clocksource driver,
  87. * otherwise following definition is used.
  88. *
  89. * Currently we do not need any more complex synchronization method
  90. * because all the supported SoCs contain only one instance of the PWM
  91. * IP. Should this change, both drivers will need to be modified to
  92. * properly synchronize accesses to particular instances.
  93. */
  94. static DEFINE_SPINLOCK(samsung_pwm_lock);
  95. #endif
  96. static inline
  97. struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
  98. {
  99. return container_of(chip, struct samsung_pwm_chip, chip);
  100. }
  101. static inline unsigned int to_tcon_channel(unsigned int channel)
  102. {
  103. /* TCON register has a gap of 4 bits (1 channel) after channel 0 */
  104. return (channel == 0) ? 0 : (channel + 1);
  105. }
  106. static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm,
  107. unsigned int channel, u8 divisor)
  108. {
  109. u8 shift = TCFG1_SHIFT(channel);
  110. unsigned long flags;
  111. u32 reg;
  112. u8 bits;
  113. bits = (fls(divisor) - 1) - pwm->variant.div_base;
  114. spin_lock_irqsave(&samsung_pwm_lock, flags);
  115. reg = readl(pwm->base + REG_TCFG1);
  116. reg &= ~(TCFG1_MUX_MASK << shift);
  117. reg |= bits << shift;
  118. writel(reg, pwm->base + REG_TCFG1);
  119. spin_unlock_irqrestore(&samsung_pwm_lock, flags);
  120. }
  121. static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan)
  122. {
  123. struct samsung_pwm_variant *variant = &chip->variant;
  124. u32 reg;
  125. reg = readl(chip->base + REG_TCFG1);
  126. reg >>= TCFG1_SHIFT(chan);
  127. reg &= TCFG1_MUX_MASK;
  128. return (BIT(reg) & variant->tclk_mask) == 0;
  129. }
  130. static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip,
  131. unsigned int chan)
  132. {
  133. unsigned long rate;
  134. u32 reg;
  135. rate = clk_get_rate(chip->base_clk);
  136. reg = readl(chip->base + REG_TCFG0);
  137. if (chan >= 2)
  138. reg >>= TCFG0_PRESCALER1_SHIFT;
  139. reg &= TCFG0_PRESCALER_MASK;
  140. return rate / (reg + 1);
  141. }
  142. static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip,
  143. unsigned int chan, unsigned long freq)
  144. {
  145. struct samsung_pwm_variant *variant = &chip->variant;
  146. unsigned long rate;
  147. struct clk *clk;
  148. u8 div;
  149. if (!pwm_samsung_is_tdiv(chip, chan)) {
  150. clk = (chan < 2) ? chip->tclk0 : chip->tclk1;
  151. if (!IS_ERR(clk)) {
  152. rate = clk_get_rate(clk);
  153. if (rate)
  154. return rate;
  155. }
  156. dev_warn(chip->chip.dev,
  157. "tclk of PWM %d is inoperational, using tdiv\n", chan);
  158. }
  159. rate = pwm_samsung_get_tin_rate(chip, chan);
  160. dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate);
  161. /*
  162. * Compare minimum PWM frequency that can be achieved with possible
  163. * divider settings and choose the lowest divisor that can generate
  164. * frequencies lower than requested.
  165. */
  166. if (variant->bits < 32) {
  167. /* Only for s3c24xx */
  168. for (div = variant->div_base; div < 4; ++div)
  169. if ((rate >> (variant->bits + div)) < freq)
  170. break;
  171. } else {
  172. /*
  173. * Other variants have enough counter bits to generate any
  174. * requested rate, so no need to check higher divisors.
  175. */
  176. div = variant->div_base;
  177. }
  178. pwm_samsung_set_divisor(chip, chan, BIT(div));
  179. return rate >> div;
  180. }
  181. static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
  182. {
  183. struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
  184. struct samsung_pwm_channel *our_chan;
  185. if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
  186. dev_warn(chip->dev,
  187. "tried to request PWM channel %d without output\n",
  188. pwm->hwpwm);
  189. return -EINVAL;
  190. }
  191. our_chan = kzalloc(sizeof(*our_chan), GFP_KERNEL);
  192. if (!our_chan)
  193. return -ENOMEM;
  194. pwm_set_chip_data(pwm, our_chan);
  195. return 0;
  196. }
  197. static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm)
  198. {
  199. kfree(pwm_get_chip_data(pwm));
  200. }
  201. static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  202. {
  203. struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
  204. unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
  205. unsigned long flags;
  206. u32 tcon;
  207. spin_lock_irqsave(&samsung_pwm_lock, flags);
  208. tcon = readl(our_chip->base + REG_TCON);
  209. tcon &= ~TCON_START(tcon_chan);
  210. tcon |= TCON_MANUALUPDATE(tcon_chan);
  211. writel(tcon, our_chip->base + REG_TCON);
  212. tcon &= ~TCON_MANUALUPDATE(tcon_chan);
  213. tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
  214. writel(tcon, our_chip->base + REG_TCON);
  215. our_chip->disabled_mask &= ~BIT(pwm->hwpwm);
  216. spin_unlock_irqrestore(&samsung_pwm_lock, flags);
  217. return 0;
  218. }
  219. static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  220. {
  221. struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
  222. unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
  223. unsigned long flags;
  224. u32 tcon;
  225. spin_lock_irqsave(&samsung_pwm_lock, flags);
  226. tcon = readl(our_chip->base + REG_TCON);
  227. tcon &= ~TCON_AUTORELOAD(tcon_chan);
  228. writel(tcon, our_chip->base + REG_TCON);
  229. our_chip->disabled_mask |= BIT(pwm->hwpwm);
  230. spin_unlock_irqrestore(&samsung_pwm_lock, flags);
  231. }
  232. static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
  233. struct pwm_device *pwm)
  234. {
  235. unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
  236. u32 tcon;
  237. unsigned long flags;
  238. spin_lock_irqsave(&samsung_pwm_lock, flags);
  239. tcon = readl(chip->base + REG_TCON);
  240. tcon |= TCON_MANUALUPDATE(tcon_chan);
  241. writel(tcon, chip->base + REG_TCON);
  242. tcon &= ~TCON_MANUALUPDATE(tcon_chan);
  243. writel(tcon, chip->base + REG_TCON);
  244. spin_unlock_irqrestore(&samsung_pwm_lock, flags);
  245. }
  246. static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
  247. int duty_ns, int period_ns, bool force_period)
  248. {
  249. struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
  250. struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
  251. u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
  252. /*
  253. * We currently avoid using 64bit arithmetic by using the
  254. * fact that anything faster than 1Hz is easily representable
  255. * by 32bits.
  256. */
  257. if (period_ns > NSEC_PER_SEC)
  258. return -ERANGE;
  259. tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
  260. oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
  261. /* We need tick count for calculation, not last tick. */
  262. ++tcnt;
  263. /* Check to see if we are changing the clock rate of the PWM. */
  264. if (chan->period_ns != period_ns || force_period) {
  265. unsigned long tin_rate;
  266. u32 period;
  267. period = NSEC_PER_SEC / period_ns;
  268. dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n",
  269. duty_ns, period_ns, period);
  270. tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period);
  271. dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate);
  272. tin_ns = NSEC_PER_SEC / tin_rate;
  273. tcnt = period_ns / tin_ns;
  274. }
  275. /* Period is too short. */
  276. if (tcnt <= 1)
  277. return -ERANGE;
  278. /* Note that counters count down. */
  279. tcmp = duty_ns / tin_ns;
  280. /* 0% duty is not available */
  281. if (!tcmp)
  282. ++tcmp;
  283. tcmp = tcnt - tcmp;
  284. /* Decrement to get tick numbers, instead of tick counts. */
  285. --tcnt;
  286. /* -1UL will give 100% duty. */
  287. --tcmp;
  288. dev_dbg(our_chip->chip.dev,
  289. "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
  290. /* Update PWM registers. */
  291. writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
  292. writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
  293. /*
  294. * In case the PWM is currently at 100% duty cycle, force a manual
  295. * update to prevent the signal staying high if the PWM is disabled
  296. * shortly afer this update (before it autoreloaded the new values).
  297. */
  298. if (oldtcmp == (u32) -1) {
  299. dev_dbg(our_chip->chip.dev, "Forcing manual update");
  300. pwm_samsung_manual_update(our_chip, pwm);
  301. }
  302. chan->period_ns = period_ns;
  303. chan->tin_ns = tin_ns;
  304. chan->duty_ns = duty_ns;
  305. return 0;
  306. }
  307. static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
  308. int duty_ns, int period_ns)
  309. {
  310. return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false);
  311. }
  312. static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip,
  313. unsigned int channel, bool invert)
  314. {
  315. unsigned int tcon_chan = to_tcon_channel(channel);
  316. unsigned long flags;
  317. u32 tcon;
  318. spin_lock_irqsave(&samsung_pwm_lock, flags);
  319. tcon = readl(chip->base + REG_TCON);
  320. if (invert) {
  321. chip->inverter_mask |= BIT(channel);
  322. tcon |= TCON_INVERT(tcon_chan);
  323. } else {
  324. chip->inverter_mask &= ~BIT(channel);
  325. tcon &= ~TCON_INVERT(tcon_chan);
  326. }
  327. writel(tcon, chip->base + REG_TCON);
  328. spin_unlock_irqrestore(&samsung_pwm_lock, flags);
  329. }
  330. static int pwm_samsung_set_polarity(struct pwm_chip *chip,
  331. struct pwm_device *pwm,
  332. enum pwm_polarity polarity)
  333. {
  334. struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
  335. bool invert = (polarity == PWM_POLARITY_NORMAL);
  336. /* Inverted means normal in the hardware. */
  337. pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert);
  338. return 0;
  339. }
  340. static const struct pwm_ops pwm_samsung_ops = {
  341. .request = pwm_samsung_request,
  342. .free = pwm_samsung_free,
  343. .enable = pwm_samsung_enable,
  344. .disable = pwm_samsung_disable,
  345. .config = pwm_samsung_config,
  346. .set_polarity = pwm_samsung_set_polarity,
  347. .owner = THIS_MODULE,
  348. };
  349. #ifdef CONFIG_OF
  350. static const struct samsung_pwm_variant s3c24xx_variant = {
  351. .bits = 16,
  352. .div_base = 1,
  353. .has_tint_cstat = false,
  354. .tclk_mask = BIT(4),
  355. };
  356. static const struct samsung_pwm_variant s3c64xx_variant = {
  357. .bits = 32,
  358. .div_base = 0,
  359. .has_tint_cstat = true,
  360. .tclk_mask = BIT(7) | BIT(6) | BIT(5),
  361. };
  362. static const struct samsung_pwm_variant s5p64x0_variant = {
  363. .bits = 32,
  364. .div_base = 0,
  365. .has_tint_cstat = true,
  366. .tclk_mask = 0,
  367. };
  368. static const struct samsung_pwm_variant s5pc100_variant = {
  369. .bits = 32,
  370. .div_base = 0,
  371. .has_tint_cstat = true,
  372. .tclk_mask = BIT(5),
  373. };
  374. static const struct of_device_id samsung_pwm_matches[] = {
  375. { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant },
  376. { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant },
  377. { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant },
  378. { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant },
  379. { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant },
  380. {},
  381. };
  382. MODULE_DEVICE_TABLE(of, samsung_pwm_matches);
  383. static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
  384. {
  385. struct device_node *np = chip->chip.dev->of_node;
  386. const struct of_device_id *match;
  387. struct property *prop;
  388. const __be32 *cur;
  389. u32 val;
  390. match = of_match_node(samsung_pwm_matches, np);
  391. if (!match)
  392. return -ENODEV;
  393. memcpy(&chip->variant, match->data, sizeof(chip->variant));
  394. of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
  395. if (val >= SAMSUNG_PWM_NUM) {
  396. dev_err(chip->chip.dev,
  397. "%s: invalid channel index in samsung,pwm-outputs property\n",
  398. __func__);
  399. continue;
  400. }
  401. chip->variant.output_mask |= BIT(val);
  402. }
  403. return 0;
  404. }
  405. #else
  406. static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
  407. {
  408. return -ENODEV;
  409. }
  410. #endif
  411. static int pwm_samsung_probe(struct platform_device *pdev)
  412. {
  413. struct device *dev = &pdev->dev;
  414. struct samsung_pwm_chip *chip;
  415. struct resource *res;
  416. unsigned int chan;
  417. int ret;
  418. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  419. if (chip == NULL)
  420. return -ENOMEM;
  421. chip->chip.dev = &pdev->dev;
  422. chip->chip.ops = &pwm_samsung_ops;
  423. chip->chip.base = -1;
  424. chip->chip.npwm = SAMSUNG_PWM_NUM;
  425. chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1;
  426. if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
  427. ret = pwm_samsung_parse_dt(chip);
  428. if (ret)
  429. return ret;
  430. chip->chip.of_xlate = of_pwm_xlate_with_flags;
  431. chip->chip.of_pwm_n_cells = 3;
  432. } else {
  433. if (!pdev->dev.platform_data) {
  434. dev_err(&pdev->dev, "no platform data specified\n");
  435. return -EINVAL;
  436. }
  437. memcpy(&chip->variant, pdev->dev.platform_data,
  438. sizeof(chip->variant));
  439. }
  440. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  441. chip->base = devm_ioremap_resource(&pdev->dev, res);
  442. if (IS_ERR(chip->base))
  443. return PTR_ERR(chip->base);
  444. chip->base_clk = devm_clk_get(&pdev->dev, "timers");
  445. if (IS_ERR(chip->base_clk)) {
  446. dev_err(dev, "failed to get timer base clk\n");
  447. return PTR_ERR(chip->base_clk);
  448. }
  449. ret = clk_prepare_enable(chip->base_clk);
  450. if (ret < 0) {
  451. dev_err(dev, "failed to enable base clock\n");
  452. return ret;
  453. }
  454. for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan)
  455. if (chip->variant.output_mask & BIT(chan))
  456. pwm_samsung_set_invert(chip, chan, true);
  457. /* Following clocks are optional. */
  458. chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0");
  459. chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1");
  460. platform_set_drvdata(pdev, chip);
  461. ret = pwmchip_add(&chip->chip);
  462. if (ret < 0) {
  463. dev_err(dev, "failed to register PWM chip\n");
  464. clk_disable_unprepare(chip->base_clk);
  465. return ret;
  466. }
  467. dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
  468. clk_get_rate(chip->base_clk),
  469. !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0,
  470. !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0);
  471. return 0;
  472. }
  473. static int pwm_samsung_remove(struct platform_device *pdev)
  474. {
  475. struct samsung_pwm_chip *chip = platform_get_drvdata(pdev);
  476. int ret;
  477. ret = pwmchip_remove(&chip->chip);
  478. if (ret < 0)
  479. return ret;
  480. clk_disable_unprepare(chip->base_clk);
  481. return 0;
  482. }
  483. #ifdef CONFIG_PM_SLEEP
  484. static int pwm_samsung_resume(struct device *dev)
  485. {
  486. struct samsung_pwm_chip *our_chip = dev_get_drvdata(dev);
  487. struct pwm_chip *chip = &our_chip->chip;
  488. unsigned int i;
  489. for (i = 0; i < SAMSUNG_PWM_NUM; i++) {
  490. struct pwm_device *pwm = &chip->pwms[i];
  491. struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
  492. if (!chan)
  493. continue;
  494. if (our_chip->variant.output_mask & BIT(i))
  495. pwm_samsung_set_invert(our_chip, i,
  496. our_chip->inverter_mask & BIT(i));
  497. if (chan->period_ns) {
  498. __pwm_samsung_config(chip, pwm, chan->duty_ns,
  499. chan->period_ns, true);
  500. /* needed to make PWM disable work on Odroid-XU3 */
  501. pwm_samsung_manual_update(our_chip, pwm);
  502. }
  503. if (our_chip->disabled_mask & BIT(i))
  504. pwm_samsung_disable(chip, pwm);
  505. else
  506. pwm_samsung_enable(chip, pwm);
  507. }
  508. return 0;
  509. }
  510. #endif
  511. static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume);
  512. static struct platform_driver pwm_samsung_driver = {
  513. .driver = {
  514. .name = "samsung-pwm",
  515. .pm = &pwm_samsung_pm_ops,
  516. .of_match_table = of_match_ptr(samsung_pwm_matches),
  517. },
  518. .probe = pwm_samsung_probe,
  519. .remove = pwm_samsung_remove,
  520. };
  521. module_platform_driver(pwm_samsung_driver);
  522. MODULE_LICENSE("GPL");
  523. MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
  524. MODULE_ALIAS("platform:samsung-pwm");