pwm-rockchip.c 9.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PWM driver for Rockchip SoCs
  4. *
  5. * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
  6. * Copyright (C) 2014 ROCKCHIP, Inc.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/io.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pwm.h>
  15. #include <linux/time.h>
  16. #define PWM_CTRL_TIMER_EN (1 << 0)
  17. #define PWM_CTRL_OUTPUT_EN (1 << 3)
  18. #define PWM_ENABLE (1 << 0)
  19. #define PWM_CONTINUOUS (1 << 1)
  20. #define PWM_DUTY_POSITIVE (1 << 3)
  21. #define PWM_DUTY_NEGATIVE (0 << 3)
  22. #define PWM_INACTIVE_NEGATIVE (0 << 4)
  23. #define PWM_INACTIVE_POSITIVE (1 << 4)
  24. #define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
  25. #define PWM_OUTPUT_LEFT (0 << 5)
  26. #define PWM_LOCK_EN (1 << 6)
  27. #define PWM_LP_DISABLE (0 << 8)
  28. struct rockchip_pwm_chip {
  29. struct pwm_chip chip;
  30. struct clk *clk;
  31. struct clk *pclk;
  32. const struct rockchip_pwm_data *data;
  33. void __iomem *base;
  34. };
  35. struct rockchip_pwm_regs {
  36. unsigned long duty;
  37. unsigned long period;
  38. unsigned long cntr;
  39. unsigned long ctrl;
  40. };
  41. struct rockchip_pwm_data {
  42. struct rockchip_pwm_regs regs;
  43. unsigned int prescaler;
  44. bool supports_polarity;
  45. bool supports_lock;
  46. u32 enable_conf;
  47. };
  48. static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
  49. {
  50. return container_of(c, struct rockchip_pwm_chip, chip);
  51. }
  52. static void rockchip_pwm_get_state(struct pwm_chip *chip,
  53. struct pwm_device *pwm,
  54. struct pwm_state *state)
  55. {
  56. struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  57. u32 enable_conf = pc->data->enable_conf;
  58. unsigned long clk_rate;
  59. u64 tmp;
  60. u32 val;
  61. int ret;
  62. ret = clk_enable(pc->pclk);
  63. if (ret)
  64. return;
  65. clk_rate = clk_get_rate(pc->clk);
  66. tmp = readl_relaxed(pc->base + pc->data->regs.period);
  67. tmp *= pc->data->prescaler * NSEC_PER_SEC;
  68. state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
  69. tmp = readl_relaxed(pc->base + pc->data->regs.duty);
  70. tmp *= pc->data->prescaler * NSEC_PER_SEC;
  71. state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
  72. val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  73. state->enabled = (val & enable_conf) == enable_conf;
  74. if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
  75. state->polarity = PWM_POLARITY_INVERSED;
  76. else
  77. state->polarity = PWM_POLARITY_NORMAL;
  78. clk_disable(pc->pclk);
  79. }
  80. static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  81. const struct pwm_state *state)
  82. {
  83. struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  84. unsigned long period, duty;
  85. u64 clk_rate, div;
  86. u32 ctrl;
  87. clk_rate = clk_get_rate(pc->clk);
  88. /*
  89. * Since period and duty cycle registers have a width of 32
  90. * bits, every possible input period can be obtained using the
  91. * default prescaler value for all practical clock rate values.
  92. */
  93. div = clk_rate * state->period;
  94. period = DIV_ROUND_CLOSEST_ULL(div,
  95. pc->data->prescaler * NSEC_PER_SEC);
  96. div = clk_rate * state->duty_cycle;
  97. duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
  98. /*
  99. * Lock the period and duty of previous configuration, then
  100. * change the duty and period, that would not be effective.
  101. */
  102. ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
  103. if (pc->data->supports_lock) {
  104. ctrl |= PWM_LOCK_EN;
  105. writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
  106. }
  107. writel(period, pc->base + pc->data->regs.period);
  108. writel(duty, pc->base + pc->data->regs.duty);
  109. if (pc->data->supports_polarity) {
  110. ctrl &= ~PWM_POLARITY_MASK;
  111. if (state->polarity == PWM_POLARITY_INVERSED)
  112. ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
  113. else
  114. ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
  115. }
  116. /*
  117. * Unlock and set polarity at the same time,
  118. * the configuration of duty, period and polarity
  119. * would be effective together at next period.
  120. */
  121. if (pc->data->supports_lock)
  122. ctrl &= ~PWM_LOCK_EN;
  123. writel(ctrl, pc->base + pc->data->regs.ctrl);
  124. }
  125. static int rockchip_pwm_enable(struct pwm_chip *chip,
  126. struct pwm_device *pwm,
  127. bool enable)
  128. {
  129. struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  130. u32 enable_conf = pc->data->enable_conf;
  131. int ret;
  132. u32 val;
  133. if (enable) {
  134. ret = clk_enable(pc->clk);
  135. if (ret)
  136. return ret;
  137. }
  138. val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  139. if (enable)
  140. val |= enable_conf;
  141. else
  142. val &= ~enable_conf;
  143. writel_relaxed(val, pc->base + pc->data->regs.ctrl);
  144. if (!enable)
  145. clk_disable(pc->clk);
  146. return 0;
  147. }
  148. static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  149. const struct pwm_state *state)
  150. {
  151. struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  152. struct pwm_state curstate;
  153. bool enabled;
  154. int ret = 0;
  155. ret = clk_enable(pc->pclk);
  156. if (ret)
  157. return ret;
  158. pwm_get_state(pwm, &curstate);
  159. enabled = curstate.enabled;
  160. if (state->polarity != curstate.polarity && enabled &&
  161. !pc->data->supports_lock) {
  162. ret = rockchip_pwm_enable(chip, pwm, false);
  163. if (ret)
  164. goto out;
  165. enabled = false;
  166. }
  167. rockchip_pwm_config(chip, pwm, state);
  168. if (state->enabled != enabled) {
  169. ret = rockchip_pwm_enable(chip, pwm, state->enabled);
  170. if (ret)
  171. goto out;
  172. }
  173. out:
  174. clk_disable(pc->pclk);
  175. return ret;
  176. }
  177. static const struct pwm_ops rockchip_pwm_ops = {
  178. .get_state = rockchip_pwm_get_state,
  179. .apply = rockchip_pwm_apply,
  180. .owner = THIS_MODULE,
  181. };
  182. static const struct rockchip_pwm_data pwm_data_v1 = {
  183. .regs = {
  184. .duty = 0x04,
  185. .period = 0x08,
  186. .cntr = 0x00,
  187. .ctrl = 0x0c,
  188. },
  189. .prescaler = 2,
  190. .supports_polarity = false,
  191. .supports_lock = false,
  192. .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
  193. };
  194. static const struct rockchip_pwm_data pwm_data_v2 = {
  195. .regs = {
  196. .duty = 0x08,
  197. .period = 0x04,
  198. .cntr = 0x00,
  199. .ctrl = 0x0c,
  200. },
  201. .prescaler = 1,
  202. .supports_polarity = true,
  203. .supports_lock = false,
  204. .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
  205. PWM_CONTINUOUS,
  206. };
  207. static const struct rockchip_pwm_data pwm_data_vop = {
  208. .regs = {
  209. .duty = 0x08,
  210. .period = 0x04,
  211. .cntr = 0x0c,
  212. .ctrl = 0x00,
  213. },
  214. .prescaler = 1,
  215. .supports_polarity = true,
  216. .supports_lock = false,
  217. .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
  218. PWM_CONTINUOUS,
  219. };
  220. static const struct rockchip_pwm_data pwm_data_v3 = {
  221. .regs = {
  222. .duty = 0x08,
  223. .period = 0x04,
  224. .cntr = 0x00,
  225. .ctrl = 0x0c,
  226. },
  227. .prescaler = 1,
  228. .supports_polarity = true,
  229. .supports_lock = true,
  230. .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
  231. PWM_CONTINUOUS,
  232. };
  233. static const struct of_device_id rockchip_pwm_dt_ids[] = {
  234. { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
  235. { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
  236. { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
  237. { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
  238. { /* sentinel */ }
  239. };
  240. MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
  241. static int rockchip_pwm_probe(struct platform_device *pdev)
  242. {
  243. const struct of_device_id *id;
  244. struct rockchip_pwm_chip *pc;
  245. struct resource *r;
  246. u32 enable_conf, ctrl;
  247. bool enabled;
  248. int ret, count;
  249. id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
  250. if (!id)
  251. return -EINVAL;
  252. pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
  253. if (!pc)
  254. return -ENOMEM;
  255. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  256. pc->base = devm_ioremap_resource(&pdev->dev, r);
  257. if (IS_ERR(pc->base))
  258. return PTR_ERR(pc->base);
  259. pc->clk = devm_clk_get(&pdev->dev, "pwm");
  260. if (IS_ERR(pc->clk)) {
  261. pc->clk = devm_clk_get(&pdev->dev, NULL);
  262. if (IS_ERR(pc->clk))
  263. return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
  264. "Can't get bus clk\n");
  265. }
  266. count = of_count_phandle_with_args(pdev->dev.of_node,
  267. "clocks", "#clock-cells");
  268. if (count == 2)
  269. pc->pclk = devm_clk_get(&pdev->dev, "pclk");
  270. else
  271. pc->pclk = pc->clk;
  272. if (IS_ERR(pc->pclk)) {
  273. ret = PTR_ERR(pc->pclk);
  274. if (ret != -EPROBE_DEFER)
  275. dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
  276. return ret;
  277. }
  278. ret = clk_prepare_enable(pc->clk);
  279. if (ret) {
  280. dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
  281. return ret;
  282. }
  283. ret = clk_prepare_enable(pc->pclk);
  284. if (ret) {
  285. dev_err(&pdev->dev, "Can't prepare enable APB clk: %d\n", ret);
  286. goto err_clk;
  287. }
  288. platform_set_drvdata(pdev, pc);
  289. pc->data = id->data;
  290. pc->chip.dev = &pdev->dev;
  291. pc->chip.ops = &rockchip_pwm_ops;
  292. pc->chip.base = -1;
  293. pc->chip.npwm = 1;
  294. if (pc->data->supports_polarity) {
  295. pc->chip.of_xlate = of_pwm_xlate_with_flags;
  296. pc->chip.of_pwm_n_cells = 3;
  297. }
  298. enable_conf = pc->data->enable_conf;
  299. ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
  300. enabled = (ctrl & enable_conf) == enable_conf;
  301. ret = pwmchip_add(&pc->chip);
  302. if (ret < 0) {
  303. dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
  304. goto err_pclk;
  305. }
  306. /* Keep the PWM clk enabled if the PWM appears to be up and running. */
  307. if (!enabled)
  308. clk_disable(pc->clk);
  309. clk_disable(pc->pclk);
  310. return 0;
  311. err_pclk:
  312. clk_disable_unprepare(pc->pclk);
  313. err_clk:
  314. clk_disable_unprepare(pc->clk);
  315. return ret;
  316. }
  317. static int rockchip_pwm_remove(struct platform_device *pdev)
  318. {
  319. struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
  320. clk_unprepare(pc->pclk);
  321. clk_unprepare(pc->clk);
  322. return pwmchip_remove(&pc->chip);
  323. }
  324. static struct platform_driver rockchip_pwm_driver = {
  325. .driver = {
  326. .name = "rockchip-pwm",
  327. .of_match_table = rockchip_pwm_dt_ids,
  328. },
  329. .probe = rockchip_pwm_probe,
  330. .remove = rockchip_pwm_remove,
  331. };
  332. module_platform_driver(rockchip_pwm_driver);
  333. MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
  334. MODULE_DESCRIPTION("Rockchip SoC PWM driver");
  335. MODULE_LICENSE("GPL v2");