pwm-renesas-tpu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R-Mobile TPU PWM driver
  4. *
  5. * Copyright (C) 2012 Renesas Solutions Corp.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <linux/init.h>
  11. #include <linux/ioport.h>
  12. #include <linux/module.h>
  13. #include <linux/mutex.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/pwm.h>
  18. #include <linux/slab.h>
  19. #include <linux/spinlock.h>
  20. #define TPU_CHANNEL_MAX 4
  21. #define TPU_TSTR 0x00 /* Timer start register (shared) */
  22. #define TPU_TCRn 0x00 /* Timer control register */
  23. #define TPU_TCR_CCLR_NONE (0 << 5)
  24. #define TPU_TCR_CCLR_TGRA (1 << 5)
  25. #define TPU_TCR_CCLR_TGRB (2 << 5)
  26. #define TPU_TCR_CCLR_TGRC (5 << 5)
  27. #define TPU_TCR_CCLR_TGRD (6 << 5)
  28. #define TPU_TCR_CKEG_RISING (0 << 3)
  29. #define TPU_TCR_CKEG_FALLING (1 << 3)
  30. #define TPU_TCR_CKEG_BOTH (2 << 3)
  31. #define TPU_TMDRn 0x04 /* Timer mode register */
  32. #define TPU_TMDR_BFWT (1 << 6)
  33. #define TPU_TMDR_BFB (1 << 5)
  34. #define TPU_TMDR_BFA (1 << 4)
  35. #define TPU_TMDR_MD_NORMAL (0 << 0)
  36. #define TPU_TMDR_MD_PWM (2 << 0)
  37. #define TPU_TIORn 0x08 /* Timer I/O control register */
  38. #define TPU_TIOR_IOA_0 (0 << 0)
  39. #define TPU_TIOR_IOA_0_CLR (1 << 0)
  40. #define TPU_TIOR_IOA_0_SET (2 << 0)
  41. #define TPU_TIOR_IOA_0_TOGGLE (3 << 0)
  42. #define TPU_TIOR_IOA_1 (4 << 0)
  43. #define TPU_TIOR_IOA_1_CLR (5 << 0)
  44. #define TPU_TIOR_IOA_1_SET (6 << 0)
  45. #define TPU_TIOR_IOA_1_TOGGLE (7 << 0)
  46. #define TPU_TIERn 0x0c /* Timer interrupt enable register */
  47. #define TPU_TSRn 0x10 /* Timer status register */
  48. #define TPU_TCNTn 0x14 /* Timer counter */
  49. #define TPU_TGRAn 0x18 /* Timer general register A */
  50. #define TPU_TGRBn 0x1c /* Timer general register B */
  51. #define TPU_TGRCn 0x20 /* Timer general register C */
  52. #define TPU_TGRDn 0x24 /* Timer general register D */
  53. #define TPU_CHANNEL_OFFSET 0x10
  54. #define TPU_CHANNEL_SIZE 0x40
  55. enum tpu_pin_state {
  56. TPU_PIN_INACTIVE, /* Pin is driven inactive */
  57. TPU_PIN_PWM, /* Pin is driven by PWM */
  58. TPU_PIN_ACTIVE, /* Pin is driven active */
  59. };
  60. struct tpu_device;
  61. struct tpu_pwm_device {
  62. bool timer_on; /* Whether the timer is running */
  63. struct tpu_device *tpu;
  64. unsigned int channel; /* Channel number in the TPU */
  65. enum pwm_polarity polarity;
  66. unsigned int prescaler;
  67. u16 period;
  68. u16 duty;
  69. };
  70. struct tpu_device {
  71. struct platform_device *pdev;
  72. struct pwm_chip chip;
  73. spinlock_t lock;
  74. void __iomem *base;
  75. struct clk *clk;
  76. };
  77. #define to_tpu_device(c) container_of(c, struct tpu_device, chip)
  78. static void tpu_pwm_write(struct tpu_pwm_device *pwm, int reg_nr, u16 value)
  79. {
  80. void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET
  81. + pwm->channel * TPU_CHANNEL_SIZE;
  82. iowrite16(value, base + reg_nr);
  83. }
  84. static void tpu_pwm_set_pin(struct tpu_pwm_device *pwm,
  85. enum tpu_pin_state state)
  86. {
  87. static const char * const states[] = { "inactive", "PWM", "active" };
  88. dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n",
  89. pwm->channel, states[state]);
  90. switch (state) {
  91. case TPU_PIN_INACTIVE:
  92. tpu_pwm_write(pwm, TPU_TIORn,
  93. pwm->polarity == PWM_POLARITY_INVERSED ?
  94. TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
  95. break;
  96. case TPU_PIN_PWM:
  97. tpu_pwm_write(pwm, TPU_TIORn,
  98. pwm->polarity == PWM_POLARITY_INVERSED ?
  99. TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
  100. break;
  101. case TPU_PIN_ACTIVE:
  102. tpu_pwm_write(pwm, TPU_TIORn,
  103. pwm->polarity == PWM_POLARITY_INVERSED ?
  104. TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
  105. break;
  106. }
  107. }
  108. static void tpu_pwm_start_stop(struct tpu_pwm_device *pwm, int start)
  109. {
  110. unsigned long flags;
  111. u16 value;
  112. spin_lock_irqsave(&pwm->tpu->lock, flags);
  113. value = ioread16(pwm->tpu->base + TPU_TSTR);
  114. if (start)
  115. value |= 1 << pwm->channel;
  116. else
  117. value &= ~(1 << pwm->channel);
  118. iowrite16(value, pwm->tpu->base + TPU_TSTR);
  119. spin_unlock_irqrestore(&pwm->tpu->lock, flags);
  120. }
  121. static int tpu_pwm_timer_start(struct tpu_pwm_device *pwm)
  122. {
  123. int ret;
  124. if (!pwm->timer_on) {
  125. /* Wake up device and enable clock. */
  126. pm_runtime_get_sync(&pwm->tpu->pdev->dev);
  127. ret = clk_prepare_enable(pwm->tpu->clk);
  128. if (ret) {
  129. dev_err(&pwm->tpu->pdev->dev, "cannot enable clock\n");
  130. return ret;
  131. }
  132. pwm->timer_on = true;
  133. }
  134. /*
  135. * Make sure the channel is stopped, as we need to reconfigure it
  136. * completely. First drive the pin to the inactive state to avoid
  137. * glitches.
  138. */
  139. tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE);
  140. tpu_pwm_start_stop(pwm, false);
  141. /*
  142. * - Clear TCNT on TGRB match
  143. * - Count on rising edge
  144. * - Set prescaler
  145. * - Output 0 until TGRA, output 1 until TGRB (active low polarity)
  146. * - Output 1 until TGRA, output 0 until TGRB (active high polarity
  147. * - PWM mode
  148. */
  149. tpu_pwm_write(pwm, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
  150. pwm->prescaler);
  151. tpu_pwm_write(pwm, TPU_TMDRn, TPU_TMDR_MD_PWM);
  152. tpu_pwm_set_pin(pwm, TPU_PIN_PWM);
  153. tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty);
  154. tpu_pwm_write(pwm, TPU_TGRBn, pwm->period);
  155. dev_dbg(&pwm->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
  156. pwm->channel, pwm->duty, pwm->period);
  157. /* Start the channel. */
  158. tpu_pwm_start_stop(pwm, true);
  159. return 0;
  160. }
  161. static void tpu_pwm_timer_stop(struct tpu_pwm_device *pwm)
  162. {
  163. if (!pwm->timer_on)
  164. return;
  165. /* Disable channel. */
  166. tpu_pwm_start_stop(pwm, false);
  167. /* Stop clock and mark device as idle. */
  168. clk_disable_unprepare(pwm->tpu->clk);
  169. pm_runtime_put(&pwm->tpu->pdev->dev);
  170. pwm->timer_on = false;
  171. }
  172. /* -----------------------------------------------------------------------------
  173. * PWM API
  174. */
  175. static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *_pwm)
  176. {
  177. struct tpu_device *tpu = to_tpu_device(chip);
  178. struct tpu_pwm_device *pwm;
  179. if (_pwm->hwpwm >= TPU_CHANNEL_MAX)
  180. return -EINVAL;
  181. pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
  182. if (pwm == NULL)
  183. return -ENOMEM;
  184. pwm->tpu = tpu;
  185. pwm->channel = _pwm->hwpwm;
  186. pwm->polarity = PWM_POLARITY_NORMAL;
  187. pwm->prescaler = 0;
  188. pwm->period = 0;
  189. pwm->duty = 0;
  190. pwm->timer_on = false;
  191. pwm_set_chip_data(_pwm, pwm);
  192. return 0;
  193. }
  194. static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *_pwm)
  195. {
  196. struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
  197. tpu_pwm_timer_stop(pwm);
  198. kfree(pwm);
  199. }
  200. static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *_pwm,
  201. int duty_ns, int period_ns)
  202. {
  203. static const unsigned int prescalers[] = { 1, 4, 16, 64 };
  204. struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
  205. struct tpu_device *tpu = to_tpu_device(chip);
  206. unsigned int prescaler;
  207. bool duty_only = false;
  208. u32 clk_rate;
  209. u32 period;
  210. u32 duty;
  211. int ret;
  212. /*
  213. * Pick a prescaler to avoid overflowing the counter.
  214. * TODO: Pick the highest acceptable prescaler.
  215. */
  216. clk_rate = clk_get_rate(tpu->clk);
  217. for (prescaler = 0; prescaler < ARRAY_SIZE(prescalers); ++prescaler) {
  218. period = clk_rate / prescalers[prescaler]
  219. / (NSEC_PER_SEC / period_ns);
  220. if (period <= 0xffff)
  221. break;
  222. }
  223. if (prescaler == ARRAY_SIZE(prescalers) || period == 0) {
  224. dev_err(&tpu->pdev->dev, "clock rate mismatch\n");
  225. return -ENOTSUPP;
  226. }
  227. if (duty_ns) {
  228. duty = clk_rate / prescalers[prescaler]
  229. / (NSEC_PER_SEC / duty_ns);
  230. if (duty > period)
  231. return -EINVAL;
  232. } else {
  233. duty = 0;
  234. }
  235. dev_dbg(&tpu->pdev->dev,
  236. "rate %u, prescaler %u, period %u, duty %u\n",
  237. clk_rate, prescalers[prescaler], period, duty);
  238. if (pwm->prescaler == prescaler && pwm->period == period)
  239. duty_only = true;
  240. pwm->prescaler = prescaler;
  241. pwm->period = period;
  242. pwm->duty = duty;
  243. /* If the channel is disabled we're done. */
  244. if (!pwm_is_enabled(_pwm))
  245. return 0;
  246. if (duty_only && pwm->timer_on) {
  247. /*
  248. * If only the duty cycle changed and the timer is already
  249. * running, there's no need to reconfigure it completely, Just
  250. * modify the duty cycle.
  251. */
  252. tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty);
  253. dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel,
  254. pwm->duty);
  255. } else {
  256. /* Otherwise perform a full reconfiguration. */
  257. ret = tpu_pwm_timer_start(pwm);
  258. if (ret < 0)
  259. return ret;
  260. }
  261. if (duty == 0 || duty == period) {
  262. /*
  263. * To avoid running the timer when not strictly required, handle
  264. * 0% and 100% duty cycles as fixed levels and stop the timer.
  265. */
  266. tpu_pwm_set_pin(pwm, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
  267. tpu_pwm_timer_stop(pwm);
  268. }
  269. return 0;
  270. }
  271. static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *_pwm,
  272. enum pwm_polarity polarity)
  273. {
  274. struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
  275. pwm->polarity = polarity;
  276. return 0;
  277. }
  278. static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *_pwm)
  279. {
  280. struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
  281. int ret;
  282. ret = tpu_pwm_timer_start(pwm);
  283. if (ret < 0)
  284. return ret;
  285. /*
  286. * To avoid running the timer when not strictly required, handle 0% and
  287. * 100% duty cycles as fixed levels and stop the timer.
  288. */
  289. if (pwm->duty == 0 || pwm->duty == pwm->period) {
  290. tpu_pwm_set_pin(pwm, pwm->duty ?
  291. TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
  292. tpu_pwm_timer_stop(pwm);
  293. }
  294. return 0;
  295. }
  296. static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *_pwm)
  297. {
  298. struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
  299. /* The timer must be running to modify the pin output configuration. */
  300. tpu_pwm_timer_start(pwm);
  301. tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE);
  302. tpu_pwm_timer_stop(pwm);
  303. }
  304. static const struct pwm_ops tpu_pwm_ops = {
  305. .request = tpu_pwm_request,
  306. .free = tpu_pwm_free,
  307. .config = tpu_pwm_config,
  308. .set_polarity = tpu_pwm_set_polarity,
  309. .enable = tpu_pwm_enable,
  310. .disable = tpu_pwm_disable,
  311. .owner = THIS_MODULE,
  312. };
  313. /* -----------------------------------------------------------------------------
  314. * Probe and remove
  315. */
  316. static int tpu_probe(struct platform_device *pdev)
  317. {
  318. struct tpu_device *tpu;
  319. struct resource *res;
  320. int ret;
  321. tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
  322. if (tpu == NULL)
  323. return -ENOMEM;
  324. spin_lock_init(&tpu->lock);
  325. tpu->pdev = pdev;
  326. /* Map memory, get clock and pin control. */
  327. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  328. tpu->base = devm_ioremap_resource(&pdev->dev, res);
  329. if (IS_ERR(tpu->base))
  330. return PTR_ERR(tpu->base);
  331. tpu->clk = devm_clk_get(&pdev->dev, NULL);
  332. if (IS_ERR(tpu->clk)) {
  333. dev_err(&pdev->dev, "cannot get clock\n");
  334. return PTR_ERR(tpu->clk);
  335. }
  336. /* Initialize and register the device. */
  337. platform_set_drvdata(pdev, tpu);
  338. tpu->chip.dev = &pdev->dev;
  339. tpu->chip.ops = &tpu_pwm_ops;
  340. tpu->chip.of_xlate = of_pwm_xlate_with_flags;
  341. tpu->chip.of_pwm_n_cells = 3;
  342. tpu->chip.base = -1;
  343. tpu->chip.npwm = TPU_CHANNEL_MAX;
  344. pm_runtime_enable(&pdev->dev);
  345. ret = pwmchip_add(&tpu->chip);
  346. if (ret < 0) {
  347. dev_err(&pdev->dev, "failed to register PWM chip\n");
  348. pm_runtime_disable(&pdev->dev);
  349. return ret;
  350. }
  351. return 0;
  352. }
  353. static int tpu_remove(struct platform_device *pdev)
  354. {
  355. struct tpu_device *tpu = platform_get_drvdata(pdev);
  356. int ret;
  357. ret = pwmchip_remove(&tpu->chip);
  358. pm_runtime_disable(&pdev->dev);
  359. return ret;
  360. }
  361. #ifdef CONFIG_OF
  362. static const struct of_device_id tpu_of_table[] = {
  363. { .compatible = "renesas,tpu-r8a73a4", },
  364. { .compatible = "renesas,tpu-r8a7740", },
  365. { .compatible = "renesas,tpu-r8a7790", },
  366. { .compatible = "renesas,tpu", },
  367. { },
  368. };
  369. MODULE_DEVICE_TABLE(of, tpu_of_table);
  370. #endif
  371. static struct platform_driver tpu_driver = {
  372. .probe = tpu_probe,
  373. .remove = tpu_remove,
  374. .driver = {
  375. .name = "renesas-tpu-pwm",
  376. .of_match_table = of_match_ptr(tpu_of_table),
  377. }
  378. };
  379. module_platform_driver(tpu_driver);
  380. MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
  381. MODULE_DESCRIPTION("Renesas TPU PWM Driver");
  382. MODULE_LICENSE("GPL v2");
  383. MODULE_ALIAS("platform:renesas-tpu-pwm");