pwm-rcar.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R-Car PWM Timer driver
  4. *
  5. * Copyright (C) 2015 Renesas Electronics Corporation
  6. *
  7. * Limitations:
  8. * - The hardware cannot generate a 0% duty cycle.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/log2.h>
  14. #include <linux/math64.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/pwm.h>
  20. #include <linux/slab.h>
  21. #define RCAR_PWM_MAX_DIVISION 24
  22. #define RCAR_PWM_MAX_CYCLE 1023
  23. #define RCAR_PWMCR 0x00
  24. #define RCAR_PWMCR_CC0_MASK 0x000f0000
  25. #define RCAR_PWMCR_CC0_SHIFT 16
  26. #define RCAR_PWMCR_CCMD BIT(15)
  27. #define RCAR_PWMCR_SYNC BIT(11)
  28. #define RCAR_PWMCR_SS0 BIT(4)
  29. #define RCAR_PWMCR_EN0 BIT(0)
  30. #define RCAR_PWMCNT 0x04
  31. #define RCAR_PWMCNT_CYC0_MASK 0x03ff0000
  32. #define RCAR_PWMCNT_CYC0_SHIFT 16
  33. #define RCAR_PWMCNT_PH0_MASK 0x000003ff
  34. #define RCAR_PWMCNT_PH0_SHIFT 0
  35. struct rcar_pwm_chip {
  36. struct pwm_chip chip;
  37. void __iomem *base;
  38. struct clk *clk;
  39. };
  40. static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
  41. {
  42. return container_of(chip, struct rcar_pwm_chip, chip);
  43. }
  44. static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
  45. unsigned int offset)
  46. {
  47. writel(data, rp->base + offset);
  48. }
  49. static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
  50. {
  51. return readl(rp->base + offset);
  52. }
  53. static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
  54. unsigned int offset)
  55. {
  56. u32 value;
  57. value = rcar_pwm_read(rp, offset);
  58. value &= ~mask;
  59. value |= data & mask;
  60. rcar_pwm_write(rp, value, offset);
  61. }
  62. static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
  63. {
  64. unsigned long clk_rate = clk_get_rate(rp->clk);
  65. u64 div, tmp;
  66. if (clk_rate == 0)
  67. return -EINVAL;
  68. div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
  69. tmp = (u64)period_ns * clk_rate + div - 1;
  70. tmp = div64_u64(tmp, div);
  71. div = ilog2(tmp - 1) + 1;
  72. return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
  73. }
  74. static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
  75. unsigned int div)
  76. {
  77. u32 value;
  78. value = rcar_pwm_read(rp, RCAR_PWMCR);
  79. value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
  80. if (div & 1)
  81. value |= RCAR_PWMCR_CCMD;
  82. div >>= 1;
  83. value |= div << RCAR_PWMCR_CC0_SHIFT;
  84. rcar_pwm_write(rp, value, RCAR_PWMCR);
  85. }
  86. static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
  87. int period_ns)
  88. {
  89. unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */
  90. unsigned long clk_rate = clk_get_rate(rp->clk);
  91. u32 cyc, ph;
  92. one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div);
  93. do_div(one_cycle, clk_rate);
  94. tmp = period_ns * 100ULL;
  95. do_div(tmp, one_cycle);
  96. cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
  97. tmp = duty_ns * 100ULL;
  98. do_div(tmp, one_cycle);
  99. ph = tmp & RCAR_PWMCNT_PH0_MASK;
  100. /* Avoid prohibited setting */
  101. if (cyc == 0 || ph == 0)
  102. return -EINVAL;
  103. rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
  104. return 0;
  105. }
  106. static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
  107. {
  108. return pm_runtime_get_sync(chip->dev);
  109. }
  110. static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  111. {
  112. pm_runtime_put(chip->dev);
  113. }
  114. static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
  115. {
  116. u32 value;
  117. /* Don't enable the PWM device if CYC0 or PH0 is 0 */
  118. value = rcar_pwm_read(rp, RCAR_PWMCNT);
  119. if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
  120. (value & RCAR_PWMCNT_PH0_MASK) == 0)
  121. return -EINVAL;
  122. rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
  123. return 0;
  124. }
  125. static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
  126. {
  127. rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
  128. }
  129. static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  130. const struct pwm_state *state)
  131. {
  132. struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
  133. int div, ret;
  134. /* This HW/driver only supports normal polarity */
  135. if (state->polarity != PWM_POLARITY_NORMAL)
  136. return -ENOTSUPP;
  137. if (!state->enabled) {
  138. rcar_pwm_disable(rp);
  139. return 0;
  140. }
  141. div = rcar_pwm_get_clock_division(rp, state->period);
  142. if (div < 0)
  143. return div;
  144. rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
  145. ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
  146. if (!ret)
  147. rcar_pwm_set_clock_control(rp, div);
  148. /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
  149. rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
  150. if (!ret)
  151. ret = rcar_pwm_enable(rp);
  152. return ret;
  153. }
  154. static const struct pwm_ops rcar_pwm_ops = {
  155. .request = rcar_pwm_request,
  156. .free = rcar_pwm_free,
  157. .apply = rcar_pwm_apply,
  158. .owner = THIS_MODULE,
  159. };
  160. static int rcar_pwm_probe(struct platform_device *pdev)
  161. {
  162. struct rcar_pwm_chip *rcar_pwm;
  163. struct resource *res;
  164. int ret;
  165. rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
  166. if (rcar_pwm == NULL)
  167. return -ENOMEM;
  168. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  169. rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res);
  170. if (IS_ERR(rcar_pwm->base))
  171. return PTR_ERR(rcar_pwm->base);
  172. rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
  173. if (IS_ERR(rcar_pwm->clk)) {
  174. dev_err(&pdev->dev, "cannot get clock\n");
  175. return PTR_ERR(rcar_pwm->clk);
  176. }
  177. platform_set_drvdata(pdev, rcar_pwm);
  178. rcar_pwm->chip.dev = &pdev->dev;
  179. rcar_pwm->chip.ops = &rcar_pwm_ops;
  180. rcar_pwm->chip.base = -1;
  181. rcar_pwm->chip.npwm = 1;
  182. pm_runtime_enable(&pdev->dev);
  183. ret = pwmchip_add(&rcar_pwm->chip);
  184. if (ret < 0) {
  185. dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
  186. pm_runtime_disable(&pdev->dev);
  187. return ret;
  188. }
  189. return 0;
  190. }
  191. static int rcar_pwm_remove(struct platform_device *pdev)
  192. {
  193. struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
  194. int ret;
  195. ret = pwmchip_remove(&rcar_pwm->chip);
  196. pm_runtime_disable(&pdev->dev);
  197. return ret;
  198. }
  199. static const struct of_device_id rcar_pwm_of_table[] = {
  200. { .compatible = "renesas,pwm-rcar", },
  201. { },
  202. };
  203. MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
  204. static struct platform_driver rcar_pwm_driver = {
  205. .probe = rcar_pwm_probe,
  206. .remove = rcar_pwm_remove,
  207. .driver = {
  208. .name = "pwm-rcar",
  209. .of_match_table = of_match_ptr(rcar_pwm_of_table),
  210. }
  211. };
  212. module_platform_driver(rcar_pwm_driver);
  213. MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
  214. MODULE_DESCRIPTION("Renesas PWM Timer Driver");
  215. MODULE_LICENSE("GPL v2");
  216. MODULE_ALIAS("platform:pwm-rcar");