pwm-lpss.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel Low Power Subsystem PWM controller driver
  4. *
  5. * Copyright (C) 2014, Intel Corporation
  6. * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7. * Author: Chew Kean Ho <kean.ho.chew@intel.com>
  8. * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
  9. * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
  10. * Author: Alan Cox <alan@linux.intel.com>
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/io.h>
  14. #include <linux/iopoll.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/time.h>
  19. #include "pwm-lpss.h"
  20. #define PWM 0x00000000
  21. #define PWM_ENABLE BIT(31)
  22. #define PWM_SW_UPDATE BIT(30)
  23. #define PWM_BASE_UNIT_SHIFT 8
  24. #define PWM_ON_TIME_DIV_MASK 0x000000ff
  25. /* Size of each PWM register space if multiple */
  26. #define PWM_SIZE 0x400
  27. static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
  28. {
  29. return container_of(chip, struct pwm_lpss_chip, chip);
  30. }
  31. static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
  32. {
  33. struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  34. return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
  35. }
  36. static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
  37. {
  38. struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  39. writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
  40. }
  41. static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
  42. {
  43. struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  44. const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
  45. const unsigned int ms = 500 * USEC_PER_MSEC;
  46. u32 val;
  47. int err;
  48. /*
  49. * PWM Configuration register has SW_UPDATE bit that is set when a new
  50. * configuration is written to the register. The bit is automatically
  51. * cleared at the start of the next output cycle by the IP block.
  52. *
  53. * If one writes a new configuration to the register while it still has
  54. * the bit enabled, PWM may freeze. That is, while one can still write
  55. * to the register, it won't have an effect. Thus, we try to sleep long
  56. * enough that the bit gets cleared and make sure the bit is not
  57. * enabled while we update the configuration.
  58. */
  59. err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
  60. if (err)
  61. dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
  62. return err;
  63. }
  64. static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
  65. {
  66. return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
  67. }
  68. static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
  69. int duty_ns, int period_ns)
  70. {
  71. unsigned long long on_time_div;
  72. unsigned long c = lpwm->info->clk_rate, base_unit_range;
  73. unsigned long long base_unit, freq = NSEC_PER_SEC;
  74. u32 ctrl;
  75. do_div(freq, period_ns);
  76. /*
  77. * The equation is:
  78. * base_unit = round(base_unit_range * freq / c)
  79. */
  80. base_unit_range = BIT(lpwm->info->base_unit_bits);
  81. freq *= base_unit_range;
  82. base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
  83. /* base_unit must not be 0 and we also want to avoid overflowing it */
  84. base_unit = clamp_val(base_unit, 1, base_unit_range - 1);
  85. on_time_div = 255ULL * duty_ns;
  86. do_div(on_time_div, period_ns);
  87. on_time_div = 255ULL - on_time_div;
  88. ctrl = pwm_lpss_read(pwm);
  89. ctrl &= ~PWM_ON_TIME_DIV_MASK;
  90. ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
  91. ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
  92. ctrl |= on_time_div;
  93. pwm_lpss_write(pwm, ctrl);
  94. pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
  95. }
  96. static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
  97. {
  98. if (cond)
  99. pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
  100. }
  101. static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm,
  102. struct pwm_device *pwm,
  103. const struct pwm_state *state)
  104. {
  105. int ret;
  106. ret = pwm_lpss_is_updating(pwm);
  107. if (ret)
  108. return ret;
  109. pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
  110. pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
  111. ret = pwm_lpss_wait_for_update(pwm);
  112. if (ret)
  113. return ret;
  114. pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
  115. return 0;
  116. }
  117. static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  118. const struct pwm_state *state)
  119. {
  120. struct pwm_lpss_chip *lpwm = to_lpwm(chip);
  121. int ret = 0;
  122. if (state->enabled) {
  123. if (!pwm_is_enabled(pwm)) {
  124. pm_runtime_get_sync(chip->dev);
  125. ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
  126. if (ret)
  127. pm_runtime_put(chip->dev);
  128. } else {
  129. ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
  130. }
  131. } else if (pwm_is_enabled(pwm)) {
  132. pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
  133. pm_runtime_put(chip->dev);
  134. }
  135. return ret;
  136. }
  137. static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  138. struct pwm_state *state)
  139. {
  140. struct pwm_lpss_chip *lpwm = to_lpwm(chip);
  141. unsigned long base_unit_range;
  142. unsigned long long base_unit, freq, on_time_div;
  143. u32 ctrl;
  144. pm_runtime_get_sync(chip->dev);
  145. base_unit_range = BIT(lpwm->info->base_unit_bits);
  146. ctrl = pwm_lpss_read(pwm);
  147. on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
  148. base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
  149. freq = base_unit * lpwm->info->clk_rate;
  150. do_div(freq, base_unit_range);
  151. if (freq == 0)
  152. state->period = NSEC_PER_SEC;
  153. else
  154. state->period = NSEC_PER_SEC / (unsigned long)freq;
  155. on_time_div *= state->period;
  156. do_div(on_time_div, 255);
  157. state->duty_cycle = on_time_div;
  158. state->polarity = PWM_POLARITY_NORMAL;
  159. state->enabled = !!(ctrl & PWM_ENABLE);
  160. pm_runtime_put(chip->dev);
  161. }
  162. static const struct pwm_ops pwm_lpss_ops = {
  163. .apply = pwm_lpss_apply,
  164. .get_state = pwm_lpss_get_state,
  165. .owner = THIS_MODULE,
  166. };
  167. struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
  168. const struct pwm_lpss_boardinfo *info)
  169. {
  170. struct pwm_lpss_chip *lpwm;
  171. unsigned long c;
  172. int i, ret;
  173. u32 ctrl;
  174. if (WARN_ON(info->npwm > MAX_PWMS))
  175. return ERR_PTR(-ENODEV);
  176. lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
  177. if (!lpwm)
  178. return ERR_PTR(-ENOMEM);
  179. lpwm->regs = devm_ioremap_resource(dev, r);
  180. if (IS_ERR(lpwm->regs))
  181. return ERR_CAST(lpwm->regs);
  182. lpwm->info = info;
  183. c = lpwm->info->clk_rate;
  184. if (!c)
  185. return ERR_PTR(-EINVAL);
  186. lpwm->chip.dev = dev;
  187. lpwm->chip.ops = &pwm_lpss_ops;
  188. lpwm->chip.base = -1;
  189. lpwm->chip.npwm = info->npwm;
  190. ret = pwmchip_add(&lpwm->chip);
  191. if (ret) {
  192. dev_err(dev, "failed to add PWM chip: %d\n", ret);
  193. return ERR_PTR(ret);
  194. }
  195. for (i = 0; i < lpwm->info->npwm; i++) {
  196. ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
  197. if (ctrl & PWM_ENABLE)
  198. pm_runtime_get(dev);
  199. }
  200. return lpwm;
  201. }
  202. EXPORT_SYMBOL_GPL(pwm_lpss_probe);
  203. int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
  204. {
  205. int i;
  206. for (i = 0; i < lpwm->info->npwm; i++) {
  207. if (pwm_is_enabled(&lpwm->chip.pwms[i]))
  208. pm_runtime_put(lpwm->chip.dev);
  209. }
  210. return pwmchip_remove(&lpwm->chip);
  211. }
  212. EXPORT_SYMBOL_GPL(pwm_lpss_remove);
  213. MODULE_DESCRIPTION("PWM driver for Intel LPSS");
  214. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  215. MODULE_LICENSE("GPL v2");