pwm-lpc32xx.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/err.h>
  7. #include <linux/io.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pwm.h>
  14. #include <linux/slab.h>
  15. struct lpc32xx_pwm_chip {
  16. struct pwm_chip chip;
  17. struct clk *clk;
  18. void __iomem *base;
  19. };
  20. #define PWM_ENABLE BIT(31)
  21. #define PWM_PIN_LEVEL BIT(30)
  22. #define to_lpc32xx_pwm_chip(_chip) \
  23. container_of(_chip, struct lpc32xx_pwm_chip, chip)
  24. static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  25. int duty_ns, int period_ns)
  26. {
  27. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  28. unsigned long long c;
  29. int period_cycles, duty_cycles;
  30. u32 val;
  31. c = clk_get_rate(lpc32xx->clk);
  32. /* The highest acceptable divisor is 256, which is represented by 0 */
  33. period_cycles = div64_u64(c * period_ns,
  34. (unsigned long long)NSEC_PER_SEC * 256);
  35. if (!period_cycles || period_cycles > 256)
  36. return -ERANGE;
  37. if (period_cycles == 256)
  38. period_cycles = 0;
  39. /* Compute 256 x #duty/period value and care for corner cases */
  40. duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
  41. period_ns);
  42. if (!duty_cycles)
  43. duty_cycles = 1;
  44. if (duty_cycles > 255)
  45. duty_cycles = 255;
  46. val = readl(lpc32xx->base + (pwm->hwpwm << 2));
  47. val &= ~0xFFFF;
  48. val |= (period_cycles << 8) | duty_cycles;
  49. writel(val, lpc32xx->base + (pwm->hwpwm << 2));
  50. return 0;
  51. }
  52. static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  53. {
  54. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  55. u32 val;
  56. int ret;
  57. ret = clk_prepare_enable(lpc32xx->clk);
  58. if (ret)
  59. return ret;
  60. val = readl(lpc32xx->base + (pwm->hwpwm << 2));
  61. val |= PWM_ENABLE;
  62. writel(val, lpc32xx->base + (pwm->hwpwm << 2));
  63. return 0;
  64. }
  65. static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  66. {
  67. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  68. u32 val;
  69. val = readl(lpc32xx->base + (pwm->hwpwm << 2));
  70. val &= ~PWM_ENABLE;
  71. writel(val, lpc32xx->base + (pwm->hwpwm << 2));
  72. clk_disable_unprepare(lpc32xx->clk);
  73. }
  74. static const struct pwm_ops lpc32xx_pwm_ops = {
  75. .config = lpc32xx_pwm_config,
  76. .enable = lpc32xx_pwm_enable,
  77. .disable = lpc32xx_pwm_disable,
  78. .owner = THIS_MODULE,
  79. };
  80. static int lpc32xx_pwm_probe(struct platform_device *pdev)
  81. {
  82. struct lpc32xx_pwm_chip *lpc32xx;
  83. struct resource *res;
  84. int ret;
  85. u32 val;
  86. lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
  87. if (!lpc32xx)
  88. return -ENOMEM;
  89. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  90. lpc32xx->base = devm_ioremap_resource(&pdev->dev, res);
  91. if (IS_ERR(lpc32xx->base))
  92. return PTR_ERR(lpc32xx->base);
  93. lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
  94. if (IS_ERR(lpc32xx->clk))
  95. return PTR_ERR(lpc32xx->clk);
  96. lpc32xx->chip.dev = &pdev->dev;
  97. lpc32xx->chip.ops = &lpc32xx_pwm_ops;
  98. lpc32xx->chip.npwm = 1;
  99. lpc32xx->chip.base = -1;
  100. /* If PWM is disabled, configure the output to the default value */
  101. val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
  102. val &= ~PWM_PIN_LEVEL;
  103. writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
  104. ret = pwmchip_add(&lpc32xx->chip);
  105. if (ret < 0) {
  106. dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
  107. return ret;
  108. }
  109. platform_set_drvdata(pdev, lpc32xx);
  110. return 0;
  111. }
  112. static int lpc32xx_pwm_remove(struct platform_device *pdev)
  113. {
  114. struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev);
  115. unsigned int i;
  116. for (i = 0; i < lpc32xx->chip.npwm; i++)
  117. pwm_disable(&lpc32xx->chip.pwms[i]);
  118. return pwmchip_remove(&lpc32xx->chip);
  119. }
  120. static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
  121. { .compatible = "nxp,lpc3220-pwm", },
  122. { /* sentinel */ }
  123. };
  124. MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
  125. static struct platform_driver lpc32xx_pwm_driver = {
  126. .driver = {
  127. .name = "lpc32xx-pwm",
  128. .of_match_table = lpc32xx_pwm_dt_ids,
  129. },
  130. .probe = lpc32xx_pwm_probe,
  131. .remove = lpc32xx_pwm_remove,
  132. };
  133. module_platform_driver(lpc32xx_pwm_driver);
  134. MODULE_ALIAS("platform:lpc32xx-pwm");
  135. MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
  136. MODULE_DESCRIPTION("LPC32XX PWM Driver");
  137. MODULE_LICENSE("GPL v2");