pwm-imx27.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * simple driver for PWM (Pulse Width Modulator) controller
  4. *
  5. * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
  6. *
  7. * Limitations:
  8. * - When disabled the output is driven to 0 independent of the configured
  9. * polarity.
  10. */
  11. #include <linux/bitfield.h>
  12. #include <linux/bitops.h>
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pwm.h>
  22. #include <linux/slab.h>
  23. #define MX3_PWMCR 0x00 /* PWM Control Register */
  24. #define MX3_PWMSR 0x04 /* PWM Status Register */
  25. #define MX3_PWMSAR 0x0C /* PWM Sample Register */
  26. #define MX3_PWMPR 0x10 /* PWM Period Register */
  27. #define MX3_PWMCR_FWM GENMASK(27, 26)
  28. #define MX3_PWMCR_STOPEN BIT(25)
  29. #define MX3_PWMCR_DOZEN BIT(24)
  30. #define MX3_PWMCR_WAITEN BIT(23)
  31. #define MX3_PWMCR_DBGEN BIT(22)
  32. #define MX3_PWMCR_BCTR BIT(21)
  33. #define MX3_PWMCR_HCTR BIT(20)
  34. #define MX3_PWMCR_POUTC GENMASK(19, 18)
  35. #define MX3_PWMCR_POUTC_NORMAL 0
  36. #define MX3_PWMCR_POUTC_INVERTED 1
  37. #define MX3_PWMCR_POUTC_OFF 2
  38. #define MX3_PWMCR_CLKSRC GENMASK(17, 16)
  39. #define MX3_PWMCR_CLKSRC_OFF 0
  40. #define MX3_PWMCR_CLKSRC_IPG 1
  41. #define MX3_PWMCR_CLKSRC_IPG_HIGH 2
  42. #define MX3_PWMCR_CLKSRC_IPG_32K 3
  43. #define MX3_PWMCR_PRESCALER GENMASK(15, 4)
  44. #define MX3_PWMCR_SWR BIT(3)
  45. #define MX3_PWMCR_REPEAT GENMASK(2, 1)
  46. #define MX3_PWMCR_REPEAT_1X 0
  47. #define MX3_PWMCR_REPEAT_2X 1
  48. #define MX3_PWMCR_REPEAT_4X 2
  49. #define MX3_PWMCR_REPEAT_8X 3
  50. #define MX3_PWMCR_EN BIT(0)
  51. #define MX3_PWMSR_FWE BIT(6)
  52. #define MX3_PWMSR_CMP BIT(5)
  53. #define MX3_PWMSR_ROV BIT(4)
  54. #define MX3_PWMSR_FE BIT(3)
  55. #define MX3_PWMSR_FIFOAV GENMASK(2, 0)
  56. #define MX3_PWMSR_FIFOAV_EMPTY 0
  57. #define MX3_PWMSR_FIFOAV_1WORD 1
  58. #define MX3_PWMSR_FIFOAV_2WORDS 2
  59. #define MX3_PWMSR_FIFOAV_3WORDS 3
  60. #define MX3_PWMSR_FIFOAV_4WORDS 4
  61. #define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
  62. #define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \
  63. (x)) + 1)
  64. #define MX3_PWM_SWR_LOOP 5
  65. /* PWMPR register value of 0xffff has the same effect as 0xfffe */
  66. #define MX3_PWMPR_MAX 0xfffe
  67. struct pwm_imx27_chip {
  68. struct clk *clk_ipg;
  69. struct clk *clk_per;
  70. void __iomem *mmio_base;
  71. struct pwm_chip chip;
  72. /*
  73. * The driver cannot read the current duty cycle from the hardware if
  74. * the hardware is disabled. Cache the last programmed duty cycle
  75. * value to return in that case.
  76. */
  77. unsigned int duty_cycle;
  78. };
  79. #define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip)
  80. static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
  81. {
  82. int ret;
  83. ret = clk_prepare_enable(imx->clk_ipg);
  84. if (ret)
  85. return ret;
  86. ret = clk_prepare_enable(imx->clk_per);
  87. if (ret) {
  88. clk_disable_unprepare(imx->clk_ipg);
  89. return ret;
  90. }
  91. return 0;
  92. }
  93. static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
  94. {
  95. clk_disable_unprepare(imx->clk_per);
  96. clk_disable_unprepare(imx->clk_ipg);
  97. }
  98. static void pwm_imx27_get_state(struct pwm_chip *chip,
  99. struct pwm_device *pwm, struct pwm_state *state)
  100. {
  101. struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
  102. u32 period, prescaler, pwm_clk, val;
  103. u64 tmp;
  104. int ret;
  105. ret = pwm_imx27_clk_prepare_enable(imx);
  106. if (ret < 0)
  107. return;
  108. val = readl(imx->mmio_base + MX3_PWMCR);
  109. if (val & MX3_PWMCR_EN)
  110. state->enabled = true;
  111. else
  112. state->enabled = false;
  113. switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
  114. case MX3_PWMCR_POUTC_NORMAL:
  115. state->polarity = PWM_POLARITY_NORMAL;
  116. break;
  117. case MX3_PWMCR_POUTC_INVERTED:
  118. state->polarity = PWM_POLARITY_INVERSED;
  119. break;
  120. default:
  121. dev_warn(chip->dev, "can't set polarity, output disconnected");
  122. }
  123. prescaler = MX3_PWMCR_PRESCALER_GET(val);
  124. pwm_clk = clk_get_rate(imx->clk_per);
  125. val = readl(imx->mmio_base + MX3_PWMPR);
  126. period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
  127. /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
  128. tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
  129. state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);
  130. /*
  131. * PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
  132. * use the cached value.
  133. */
  134. if (state->enabled)
  135. val = readl(imx->mmio_base + MX3_PWMSAR);
  136. else
  137. val = imx->duty_cycle;
  138. tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
  139. state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
  140. pwm_imx27_clk_disable_unprepare(imx);
  141. }
  142. static void pwm_imx27_sw_reset(struct pwm_chip *chip)
  143. {
  144. struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
  145. struct device *dev = chip->dev;
  146. int wait_count = 0;
  147. u32 cr;
  148. writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
  149. do {
  150. usleep_range(200, 1000);
  151. cr = readl(imx->mmio_base + MX3_PWMCR);
  152. } while ((cr & MX3_PWMCR_SWR) &&
  153. (wait_count++ < MX3_PWM_SWR_LOOP));
  154. if (cr & MX3_PWMCR_SWR)
  155. dev_warn(dev, "software reset timeout\n");
  156. }
  157. static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
  158. struct pwm_device *pwm)
  159. {
  160. struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
  161. struct device *dev = chip->dev;
  162. unsigned int period_ms;
  163. int fifoav;
  164. u32 sr;
  165. sr = readl(imx->mmio_base + MX3_PWMSR);
  166. fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
  167. if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
  168. period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
  169. NSEC_PER_MSEC);
  170. msleep(period_ms);
  171. sr = readl(imx->mmio_base + MX3_PWMSR);
  172. if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
  173. dev_warn(dev, "there is no free FIFO slot\n");
  174. }
  175. }
  176. static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  177. const struct pwm_state *state)
  178. {
  179. unsigned long period_cycles, duty_cycles, prescale;
  180. struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
  181. struct pwm_state cstate;
  182. unsigned long long c;
  183. unsigned long long clkrate;
  184. int ret;
  185. u32 cr;
  186. pwm_get_state(pwm, &cstate);
  187. clkrate = clk_get_rate(imx->clk_per);
  188. c = clkrate * state->period;
  189. do_div(c, NSEC_PER_SEC);
  190. period_cycles = c;
  191. prescale = period_cycles / 0x10000 + 1;
  192. period_cycles /= prescale;
  193. c = clkrate * state->duty_cycle;
  194. do_div(c, NSEC_PER_SEC);
  195. duty_cycles = c;
  196. duty_cycles /= prescale;
  197. /*
  198. * according to imx pwm RM, the real period value should be PERIOD
  199. * value in PWMPR plus 2.
  200. */
  201. if (period_cycles > 2)
  202. period_cycles -= 2;
  203. else
  204. period_cycles = 0;
  205. /*
  206. * Wait for a free FIFO slot if the PWM is already enabled, and flush
  207. * the FIFO if the PWM was disabled and is about to be enabled.
  208. */
  209. if (cstate.enabled) {
  210. pwm_imx27_wait_fifo_slot(chip, pwm);
  211. } else {
  212. ret = pwm_imx27_clk_prepare_enable(imx);
  213. if (ret)
  214. return ret;
  215. pwm_imx27_sw_reset(chip);
  216. }
  217. writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
  218. writel(period_cycles, imx->mmio_base + MX3_PWMPR);
  219. /*
  220. * Store the duty cycle for future reference in cases where the
  221. * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
  222. */
  223. imx->duty_cycle = duty_cycles;
  224. cr = MX3_PWMCR_PRESCALER_SET(prescale) |
  225. MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
  226. FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
  227. MX3_PWMCR_DBGEN;
  228. if (state->polarity == PWM_POLARITY_INVERSED)
  229. cr |= FIELD_PREP(MX3_PWMCR_POUTC,
  230. MX3_PWMCR_POUTC_INVERTED);
  231. if (state->enabled)
  232. cr |= MX3_PWMCR_EN;
  233. writel(cr, imx->mmio_base + MX3_PWMCR);
  234. if (!state->enabled)
  235. pwm_imx27_clk_disable_unprepare(imx);
  236. return 0;
  237. }
  238. static const struct pwm_ops pwm_imx27_ops = {
  239. .apply = pwm_imx27_apply,
  240. .get_state = pwm_imx27_get_state,
  241. .owner = THIS_MODULE,
  242. };
  243. static const struct of_device_id pwm_imx27_dt_ids[] = {
  244. { .compatible = "fsl,imx27-pwm", },
  245. { /* sentinel */ }
  246. };
  247. MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
  248. static int pwm_imx27_probe(struct platform_device *pdev)
  249. {
  250. struct pwm_imx27_chip *imx;
  251. int ret;
  252. u32 pwmcr;
  253. imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
  254. if (imx == NULL)
  255. return -ENOMEM;
  256. platform_set_drvdata(pdev, imx);
  257. imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  258. if (IS_ERR(imx->clk_ipg)) {
  259. int ret = PTR_ERR(imx->clk_ipg);
  260. if (ret != -EPROBE_DEFER)
  261. dev_err(&pdev->dev,
  262. "getting ipg clock failed with %d\n",
  263. ret);
  264. return ret;
  265. }
  266. imx->clk_per = devm_clk_get(&pdev->dev, "per");
  267. if (IS_ERR(imx->clk_per)) {
  268. int ret = PTR_ERR(imx->clk_per);
  269. if (ret != -EPROBE_DEFER)
  270. dev_err(&pdev->dev,
  271. "failed to get peripheral clock: %d\n",
  272. ret);
  273. return ret;
  274. }
  275. imx->chip.ops = &pwm_imx27_ops;
  276. imx->chip.dev = &pdev->dev;
  277. imx->chip.base = -1;
  278. imx->chip.npwm = 1;
  279. imx->chip.of_xlate = of_pwm_xlate_with_flags;
  280. imx->chip.of_pwm_n_cells = 3;
  281. imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
  282. if (IS_ERR(imx->mmio_base))
  283. return PTR_ERR(imx->mmio_base);
  284. ret = pwm_imx27_clk_prepare_enable(imx);
  285. if (ret)
  286. return ret;
  287. /* keep clks on if pwm is running */
  288. pwmcr = readl(imx->mmio_base + MX3_PWMCR);
  289. if (!(pwmcr & MX3_PWMCR_EN))
  290. pwm_imx27_clk_disable_unprepare(imx);
  291. return pwmchip_add(&imx->chip);
  292. }
  293. static int pwm_imx27_remove(struct platform_device *pdev)
  294. {
  295. struct pwm_imx27_chip *imx;
  296. imx = platform_get_drvdata(pdev);
  297. return pwmchip_remove(&imx->chip);
  298. }
  299. static struct platform_driver imx_pwm_driver = {
  300. .driver = {
  301. .name = "pwm-imx27",
  302. .of_match_table = pwm_imx27_dt_ids,
  303. },
  304. .probe = pwm_imx27_probe,
  305. .remove = pwm_imx27_remove,
  306. };
  307. module_platform_driver(imx_pwm_driver);
  308. MODULE_LICENSE("GPL v2");
  309. MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");